239 lines
6.1 KiB
C
239 lines
6.1 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the VIA VT82C505 VL/PCI Bridge Controller.
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*
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*
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*
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* Authors: Tiseno100,
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Tiseno100.
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* Copyright 2020 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/pic.h>
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#include <86box/pci.h>
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#include <86box/plat_unused.h>
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#include <86box/device.h>
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#include <86box/chipset.h>
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typedef struct vt82c505_t {
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uint8_t index;
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uint8_t pci_slot;
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uint8_t pad;
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uint8_t pad0;
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uint8_t pci_conf[256];
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} vt82c505_t;
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static void
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vt82c505_write(int func, int addr, uint8_t val, void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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uint8_t irq;
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const uint8_t irq_array[8] = { 0, 5, 9, 10, 11, 14, 15, 0 };
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if (func != 0)
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return;
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switch (addr) {
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/* RX00-07h: Mandatory header field */
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case 0x04:
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dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xbf) | (val & 0x40);
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break;
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case 0x07:
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dev->pci_conf[addr] &= ~(val & 0x90);
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break;
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/* RX80-9F: VT82C505 internal configuration registers */
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case 0x80:
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dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x0f) | (val & 0xf0);
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break;
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case 0x81:
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case 0x84:
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case 0x85:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8a:
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case 0x8b:
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case 0x8c:
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case 0x8d:
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case 0x8e:
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case 0x8f:
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case 0x92:
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case 0x94:
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dev->pci_conf[addr] = val;
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break;
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case 0x82:
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dev->pci_conf[addr] = val & 0xdb;
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break;
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case 0x83:
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dev->pci_conf[addr] = val & 0xf9;
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break;
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case 0x86:
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dev->pci_conf[addr] = val & 0xef;
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/* Bit 7 switches between the two PCI configuration mechanisms:
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0 = configuration mechanism 1, 1 = configuration mechanism 2 */
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pci_set_pmc(!(val & 0x80));
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break;
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case 0x90:
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dev->pci_conf[addr] = val;
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irq = irq_array[val & 0x07];
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if ((val & 0x08) && (irq != 0))
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pci_set_irq_routing(PCI_INTC, irq);
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else
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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irq = irq_array[(val & 0x70) >> 4];
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if ((val & 0x80) && (irq != 0))
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pci_set_irq_routing(PCI_INTD, irq);
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else
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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break;
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case 0x91:
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dev->pci_conf[addr] = val;
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irq = irq_array[val & 0x07];
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if ((val & 0x08) && (irq != 0))
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pci_set_irq_routing(PCI_INTA, irq);
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else
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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irq = irq_array[(val & 0x70) >> 4];
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if ((val & 0x80) && (irq != 0))
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pci_set_irq_routing(PCI_INTB, irq);
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else
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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break;
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case 0x93:
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dev->pci_conf[addr] = val & 0xe0;
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break;
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default:
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break;
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}
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}
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static uint8_t
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vt82c505_read(int func, int addr, void *priv)
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{
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const vt82c505_t *dev = (vt82c505_t *) priv;
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uint8_t ret = 0xff;
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if (func != 0)
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return ret;
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ret = dev->pci_conf[addr];
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return ret;
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}
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static void
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vt82c505_out(uint16_t addr, uint8_t val, void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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if (addr == 0xa8)
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dev->index = val;
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else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
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vt82c505_write(0, dev->index, val, priv);
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}
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static uint8_t
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vt82c505_in(uint16_t addr, void *priv)
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{
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const vt82c505_t *dev = (vt82c505_t *) priv;
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uint8_t ret = 0xff;
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if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
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ret = vt82c505_read(0, dev->index, priv);
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return ret;
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}
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static void
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vt82c505_reset(void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) calloc(1, sizeof(vt82c505_t));
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dev->pci_conf[0x04] = 0x07;
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dev->pci_conf[0x07] = 0x00;
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for (uint8_t i = 0x80; i <= 0x9f; i++) {
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switch (i) {
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case 0x81:
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vt82c505_write(0, i, 0x01, priv);
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break;
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case 0x84:
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vt82c505_write(0, i, 0x03, priv);
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break;
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case 0x93:
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vt82c505_write(0, i, 0x40, priv);
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break;
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default:
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vt82c505_write(0, i, 0x00, priv);
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break;
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}
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}
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pic_reset();
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pic_set_pci_flag(1);
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}
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static void
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vt82c505_close(void *priv)
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{
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vt82c505_t *dev = (vt82c505_t *) priv;
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free(dev);
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}
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static void *
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vt82c505_init(UNUSED(const device_t *info))
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{
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vt82c505_t *dev = (vt82c505_t *) calloc(1, sizeof(vt82c505_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev, &dev->pci_slot);
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dev->pci_conf[0x00] = 0x06;
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dev->pci_conf[0x01] = 0x11;
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dev->pci_conf[0x02] = 0x05;
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dev->pci_conf[0x03] = 0x05;
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dev->pci_conf[0x04] = 0x07;
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dev->pci_conf[0x07] = 0x00;
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dev->pci_conf[0x81] = 0x01;
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dev->pci_conf[0x84] = 0x03;
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dev->pci_conf[0x93] = 0x40;
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io_sethandler(0x0a8, 0x0002, vt82c505_in, NULL, NULL, vt82c505_out, NULL, NULL, dev);
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return dev;
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}
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const device_t via_vt82c505_device = {
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.name = "VIA VT82C505",
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.internal_name = "via_vt82c505",
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.flags = DEVICE_PCI,
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.local = 0,
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.init = vt82c505_init,
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.close = vt82c505_close,
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.reset = vt82c505_reset,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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