292 lines
7.7 KiB
C
292 lines
7.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the VLSI VL82c480 chipset.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/machine.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct vl82c480_t {
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uint8_t idx;
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uint8_t regs[256];
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uint32_t banks[4];
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} vl82c480_t;
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static int
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vl82c480_shflags(uint8_t access)
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{
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int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
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switch (access) {
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default:
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case 0x00:
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ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
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break;
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case 0x01:
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ret = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
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break;
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case 0x02:
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ret = MEM_READ_INTERNAL | MEM_WRITE_EXTANY;
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break;
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case 0x03:
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ret = MEM_READ_INTERNAL | MEM_WRITE_INTERNAL;
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break;
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}
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return ret;
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}
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static void
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vl82c480_recalc_shadow(vl82c480_t *dev)
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{
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uint32_t base;
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uint8_t access;
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shadowbios = 0;
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shadowbios_write = 0;
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for (uint8_t i = 0; i < 6; i++) {
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for (uint8_t j = 0; j < 8; j += 2) {
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base = 0x000a0000 + (i << 16) + (j << 13);
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access = (dev->regs[0x0d + i] >> j) & 3;
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mem_set_mem_state(base, 0x4000, vl82c480_shflags(access));
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shadowbios |= ((base >= 0xe0000) && (access & 0x02));
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shadowbios_write |= ((base >= 0xe0000) && (access & 0x01));
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}
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}
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flushmmucache();
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}
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static void
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vl82c480_recalc_banks(vl82c480_t *dev)
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{
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uint32_t sizes[8] = { 0, 0, 1024, 2048, 4096, 8192, 16384, 32768 };
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uint8_t shifts[4] = { 0, 4, 0, 4 };
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uint8_t regs[4] = { 0x02, 0x02, 0x03, 0x03 };
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uint32_t total = 0;
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for (uint8_t i = 0; i < 4; i++) {
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uint8_t shift = shifts[i];
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uint8_t reg = regs[i];
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uint8_t cfg = (dev->regs[reg] >> shift) & 0x7;
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uint32_t size = sizes[cfg];
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total += MIN(dev->banks[i], size);
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}
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if (total > 1024) {
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mem_mapping_set_addr(&ram_low_mapping, 0x00000000, 0x000a0000);
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mem_mapping_set_addr(&ram_high_mapping, 0x00100000, (total - 1024) << 10);
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} else {
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if (total >= 1024)
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mem_mapping_set_addr(&ram_low_mapping, 0x00000000, 0x000a0000);
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else
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mem_mapping_disable(&ram_low_mapping);
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mem_mapping_disable(&ram_high_mapping);
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}
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flushmmucache();
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}
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static void
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vl82c480_write(uint16_t addr, uint8_t val, void *priv)
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{
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vl82c480_t *dev = (vl82c480_t *) priv;
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switch (addr) {
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case 0xec:
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dev->idx = val;
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break;
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case 0xed:
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if (((dev->idx >= 0x01) && (dev->idx <= 0x19)) ||
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((dev->idx >= 0x20) && (dev->idx <= 0x24))) {
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switch (dev->idx) {
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default:
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dev->regs[dev->idx] = val;
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break;
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case 0x02: case 0x03:
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dev->regs[dev->idx] = val;
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if (!strcmp(machine_get_internal_name(), "martin") ||
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!strcmp(machine_get_internal_name(), "prolineamt"))
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vl82c480_recalc_banks(dev);
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break;
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case 0x04:
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if (dev->regs[0x00] == 0x98)
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dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7);
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else
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dev->regs[dev->idx] = val;
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break;
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case 0x05:
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dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x10) | (val & 0xef);
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break;
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case 0x07:
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dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf);
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break;
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case 0x0d ... 0x12:
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dev->regs[dev->idx] = val;
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vl82c480_recalc_shadow(dev);
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break;
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}
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}
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break;
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/* TODO: This is actually Fast A20 disable. */
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#if 0
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case 0xee:
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mem_a20_alt = 0x00;
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mem_a20_recalc();
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break;
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#endif
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default:
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break;
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}
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}
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static uint8_t
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vl82c480_read(uint16_t addr, void *priv)
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{
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const vl82c480_t *dev = (vl82c480_t *) priv;
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uint8_t ret = 0xff;
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switch (addr) {
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case 0xec:
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ret = dev->idx;
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break;
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case 0xed:
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if (((dev->idx >= 0x01) && (dev->idx <= 0x19)) ||
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((dev->idx >= 0x20) && (dev->idx <= 0x24)))
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ret = dev->regs[dev->idx];
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break;
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/* TODO: This is actually Fast A20 enable. */
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#if 0
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case 0xee:
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mem_a20_alt = 0x02;
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mem_a20_recalc();
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break;
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#endif
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case 0xef:
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softresetx86();
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cpu_set_edx();
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break;
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default:
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break;
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}
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return ret;
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}
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static void
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vl82c480_close(void *priv)
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{
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vl82c480_t *dev = (vl82c480_t *) priv;
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free(dev);
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}
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static void *
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vl82c480_init(const device_t *info)
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{
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vl82c480_t *dev = (vl82c480_t *) calloc(1, sizeof(vl82c480_t));
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uint32_t sizes[8] = { 0, 0, 1024, 2048, 4096, 8192, 16384, 32768 };
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uint32_t ms = mem_size;
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uint8_t min_i = !strcmp(machine_get_internal_name(), "prolineamt") ? 1 : 0;
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uint8_t min_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 4 : 2;
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uint8_t max_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 8 : 7;
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dev->regs[0x00] = info->local;
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dev->regs[0x01] = 0xff;
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dev->regs[0x02] = 0x8a;
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dev->regs[0x03] = 0x88;
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dev->regs[0x06] = 0x1b;
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if (info->local == 0x98)
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dev->regs[0x07] = 0x21;
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dev->regs[0x08] = 0x38;
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if (!strcmp(machine_get_internal_name(), "prolineamt")) {
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dev->banks[0] = 4096;
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/* Bank 0 is ignored if 64 MB is installed. */
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if (ms != 65536)
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ms -= 4096;
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}
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if (ms > 0) for (uint8_t i = min_i; i < 4; i++) {
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for (uint8_t j = min_j; j < max_j; j++) {
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if (ms >= sizes[j])
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dev->banks[i] = sizes[j];
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else
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break;
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}
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ms -= dev->banks[i];
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if ((ms == 0) || (dev->banks[i] == 0))
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break;
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}
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io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev);
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device_add(&port_92_pci_device);
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return dev;
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}
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const device_t vl82c480_device = {
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.name = "VLSI VL82c480",
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.internal_name = "vl82c480",
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.flags = 0,
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.local = 0x90,
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.init = vl82c480_init,
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.close = vl82c480_close,
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.reset = NULL,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t vl82c486_device = {
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.name = "VLSI VL82c486",
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.internal_name = "vl82c486",
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.flags = 0,
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.local = 0x98,
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.init = vl82c480_init,
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.close = vl82c480_close,
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.reset = NULL,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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