700 lines
18 KiB
C
700 lines
18 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ALi M1621/2 CPU-to-PCI Bridge.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/plat_fallthrough.h>
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#include <86box/plat_unused.h>
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#include <86box/smram.h>
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#include <86box/spd.h>
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#include <86box/chipset.h>
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typedef struct ali1621_t {
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uint8_t pci_slot;
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uint8_t pad;
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uint8_t pad0;
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uint8_t pad1;
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uint8_t pci_conf[256];
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smram_t *smram[2];
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} ali1621_t;
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#ifdef ENABLE_ALI1621_LOG
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int ali1621_do_log = ENABLE_ALI1621_LOG;
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static void
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ali1621_log(const char *fmt, ...)
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{
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va_list ap;
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if (ali1621_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define ali1621_log(fmt, ...)
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#endif
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/* Table translated to a more sensible format:
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Read cycles:
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SMREN SMM Mode Code Data
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0 X X PCI PCI
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1 0 Close PCI PCI
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1 0 Lock PCI PCI
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1 0 Protect PCI PCI
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1 0 Open DRAM DRAM
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1 1 Open DRAM DRAM
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1 1 Protect DRAM DRAM
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1 1 Close DRAM PCI
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1 1 Lock DRAM PCI
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Write cycles:
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SMWEN SMM Mode Data
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0 X X PCI
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1 0 Close PCI
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1 0 Lock PCI
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1 0 Protect PCI
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1 0 Open DRAM
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1 1 Open DRAM
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1 1 Protect DRAM
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1 1 Close PCI
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1 1 Lock PCI
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Explanation of the modes based above:
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If SM*EN = 0, SMRAM is entirely disabled, otherwise:
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If mode is Close or Lock, then SMRAM always goes to PCI outside SMM,
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and data to PCI, code to DRAM in SMM;
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If mode is Protect, then SMRAM always goes to PCI outside SMM and
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DRAM in SMM;
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If mode is Open, then SMRAM always goes to DRAM.
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Read and write are enabled separately.
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*/
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static void
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ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
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{
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uint16_t access_smm = 0x0000;
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uint16_t access_normal = 0x0000;
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smram_disable_all();
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if (val & 0xc0) {
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/* SMRAM 0: A0000-BFFFF */
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if (val & 0x80) {
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access_smm = ACCESS_SMRAM_X;
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switch (val & 0x30) {
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case 0x10: /* Open. */
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access_normal = ACCESS_SMRAM_RX;
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fallthrough;
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case 0x30: /* Protect. */
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access_smm |= ACCESS_SMRAM_R;
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break;
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default:
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break;
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}
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}
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if (val & 0x40)
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switch (val & 0x30) {
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case 0x10: /* Open. */
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access_normal |= ACCESS_SMRAM_W;
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fallthrough;
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case 0x30: /* Protect. */
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access_smm |= ACCESS_SMRAM_W;
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break;
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default:
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break;
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}
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smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30));
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mem_set_access(ACCESS_NORMAL, 3, 0xa0000, 0x20000, access_normal);
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mem_set_access(ACCESS_SMM, 3, 0xa0000, 0x20000, access_smm);
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}
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if (val & 0x08)
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smram_enable(dev->smram[1], 0x38000, 0xa8000, 0x08000, 0, 1);
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flushmmucache_nopc();
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}
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static void
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ali1621_shadow_recalc(UNUSED(int cur_reg), ali1621_t *dev)
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{
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int r_bit;
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int w_bit;
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int reg;
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uint32_t base;
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uint32_t flags = 0;
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shadowbios = shadowbios_write = 0;
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/* C0000-EFFFF */
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for (uint8_t i = 0; i < 12; i++) {
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base = 0x000c0000 + (i << 14);
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r_bit = (i << 1) + 4;
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reg = 0x84;
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if (r_bit > 23) {
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r_bit &= 7;
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reg += 3;
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} else if (r_bit > 15) {
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r_bit &= 7;
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reg += 2;
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} else if (r_bit > 7) {
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r_bit &= 7;
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reg++;
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}
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w_bit = r_bit + 1;
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flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
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if (base >= 0x000e0000) {
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if (dev->pci_conf[reg] & (1 << r_bit))
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shadowbios |= 1;
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if (dev->pci_conf[reg] & (1 << r_bit))
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shadowbios_write |= 1;
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}
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ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
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(dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E');
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mem_set_mem_state_both(base, 0x00004000, flags);
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}
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/* F0000-FFFFF */
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base = 0x000f0000;
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r_bit = 4;
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w_bit = 5;
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reg = 0x87;
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flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
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if (dev->pci_conf[reg] & (1 << r_bit))
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shadowbios |= 1;
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if (dev->pci_conf[reg] & (1 << r_bit))
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shadowbios_write |= 1;
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ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x0000ffff,
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(dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E');
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mem_set_mem_state_both(base, 0x00010000, flags);
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flushmmucache_nopc();
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}
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static void
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ali1621_mask_bar(ali1621_t *dev)
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{
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uint32_t bar;
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uint32_t mask;
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switch (dev->pci_conf[0xbc] & 0x0f) {
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default:
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case 0x00:
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mask = 0x00000000;
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break;
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case 0x01:
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mask = 0xfff00000;
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break;
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case 0x02:
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mask = 0xffe00000;
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break;
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case 0x03:
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mask = 0xffc00000;
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break;
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case 0x04:
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mask = 0xff800000;
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break;
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case 0x06:
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mask = 0xff000000;
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break;
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case 0x07:
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mask = 0xfe000000;
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break;
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case 0x08:
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mask = 0xfc000000;
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break;
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case 0x09:
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mask = 0xf8000000;
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break;
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case 0x0a:
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mask = 0xf0000000;
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break;
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}
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bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask;
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dev->pci_conf[0x12] = (bar >> 16) & 0xff;
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dev->pci_conf[0x13] = (bar >> 24) & 0xff;
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}
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static void
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ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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{
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ali1621_t *dev = (ali1621_t *) priv;
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switch (addr) {
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case 0x04:
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dev->pci_conf[addr] = val & 0x01;
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break;
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case 0x05:
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dev->pci_conf[addr] = val & 0x01;
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break;
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case 0x07:
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dev->pci_conf[addr] &= ~(val & 0xf0);
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break;
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case 0x0d:
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x12:
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dev->pci_conf[0x12] = (val & 0xc0);
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ali1621_mask_bar(dev);
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break;
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case 0x13:
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dev->pci_conf[0x13] = val;
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ali1621_mask_bar(dev);
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break;
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case 0x34:
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dev->pci_conf[addr] = val;
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break;
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case 0x40:
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dev->pci_conf[addr] = val;
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break;
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case 0x41:
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dev->pci_conf[addr] = val;
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break;
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case 0x42:
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dev->pci_conf[addr] = val;
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break;
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case 0x43:
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dev->pci_conf[addr] = val;
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break;
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case 0x44:
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dev->pci_conf[addr] = val;
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break;
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case 0x45:
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dev->pci_conf[addr] = val;
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break;
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case 0x46:
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dev->pci_conf[addr] = val;
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break;
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case 0x47:
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dev->pci_conf[addr] = val;
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break;
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case 0x48:
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dev->pci_conf[addr] = val;
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break;
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case 0x49:
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dev->pci_conf[addr] = val;
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break;
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case 0x4a:
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dev->pci_conf[addr] = val;
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break;
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case 0x4b:
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dev->pci_conf[addr] = val & 0x0f;
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break;
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case 0x4c:
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dev->pci_conf[addr] = val;
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break;
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case 0x4d:
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dev->pci_conf[addr] = val;
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break;
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case 0x4e:
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dev->pci_conf[addr] = val;
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break;
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case 0x4f:
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dev->pci_conf[addr] = val;
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break;
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case 0x50:
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dev->pci_conf[addr] = val & 0xef;
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break;
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case 0x51:
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dev->pci_conf[addr] = val;
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break;
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case 0x52:
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dev->pci_conf[addr] = val & 0x9f;
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break;
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case 0x53:
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dev->pci_conf[addr] = val;
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break;
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case 0x54:
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dev->pci_conf[addr] = val & 0xb4;
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break;
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case 0x55:
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dev->pci_conf[addr] = val & 0x01;
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break;
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case 0x56:
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dev->pci_conf[addr] = val & 0x3f;
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break;
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case 0x57:
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dev->pci_conf[addr] = val & 0x08;
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break;
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case 0x58:
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dev->pci_conf[addr] = val;
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break;
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case 0x59:
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dev->pci_conf[addr] = val;
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break;
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case 0x5a:
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dev->pci_conf[addr] = val;
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break;
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case 0x5c:
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dev->pci_conf[addr] = val & 0x01;
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break;
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case 0x60:
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dev->pci_conf[addr] = val;
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break;
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case 0x61:
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dev->pci_conf[addr] = val;
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break;
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case 0x62:
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dev->pci_conf[addr] = val;
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break;
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case 0x63:
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dev->pci_conf[addr] = val;
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break;
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case 0x64:
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dev->pci_conf[addr] = val & 0xb7;
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break;
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case 0x65:
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dev->pci_conf[addr] = val & 0x01;
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break;
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case 0x66:
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dev->pci_conf[addr] &= ~(val & 0x33);
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break;
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case 0x67:
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dev->pci_conf[addr] = val;
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break;
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case 0x68:
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dev->pci_conf[addr] = val;
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break;
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case 0x69:
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dev->pci_conf[addr] = val;
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break;
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case 0x6c ... 0x7b:
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/* Bits 22:20 = DRAM Row size:
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- 000: 4 MB;
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- 001: 8 MB;
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- 010: 16 MB;
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- 011: 32 MB;
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- 100: 64 MB;
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- 101: 128 MB;
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- 110: 256 MB;
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- 111: Reserved. */
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dev->pci_conf[addr] = val;
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spd_write_drbs_ali1621(dev->pci_conf, 0x6c, 0x7b);
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break;
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case 0x7c ... 0x7f:
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dev->pci_conf[addr] = val;
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break;
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case 0x80:
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dev->pci_conf[addr] = val;
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break;
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case 0x81:
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dev->pci_conf[addr] = val & 0xdf;
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break;
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case 0x82:
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dev->pci_conf[addr] = val & 0xf7;
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break;
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case 0x83:
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dev->pci_conf[addr] = val & 0xfc;
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ali1621_smram_recalc(val & 0xfc, dev);
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break;
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case 0x84 ... 0x87:
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if (addr == 0x87)
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dev->pci_conf[addr] = val & 0x3f;
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else
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dev->pci_conf[addr] = val;
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ali1621_shadow_recalc(val, dev);
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break;
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case 0x88:
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case 0x89:
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dev->pci_conf[addr] = val;
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break;
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case 0x8a:
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dev->pci_conf[addr] = val & 0xc5;
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break;
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case 0x8b:
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dev->pci_conf[addr] = val & 0xbf;
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break;
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case 0x8c ... 0x8f:
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dev->pci_conf[addr] = val;
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break;
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case 0x90:
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dev->pci_conf[addr] = val;
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break;
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case 0x91:
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dev->pci_conf[addr] = val & 0x07;
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break;
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case 0x94 ... 0x97:
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dev->pci_conf[addr] = val;
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break;
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case 0x98 ... 0x9b:
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dev->pci_conf[addr] = val;
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break;
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case 0x9c ... 0x9f:
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dev->pci_conf[addr] = val;
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break;
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case 0xa0:
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case 0xa1:
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dev->pci_conf[addr] = val;
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break;
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case 0xbc:
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dev->pci_conf[addr] = val & 0x0f;
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ali1621_mask_bar(dev);
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break;
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case 0xbd:
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dev->pci_conf[addr] = val & 0xf0;
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break;
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case 0xbe:
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case 0xbf:
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dev->pci_conf[addr] = val;
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break;
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case 0xc0:
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dev->pci_conf[addr] = val & 0xb1;
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break;
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case 0xc4 ... 0xc7:
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dev->pci_conf[addr] = val;
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break;
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case 0xc8:
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dev->pci_conf[addr] = val & 0x8c;
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break;
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case 0xc9:
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dev->pci_conf[addr] = val;
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break;
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case 0xca:
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dev->pci_conf[addr] = val & 0x7f;
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break;
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case 0xcb:
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dev->pci_conf[addr] = val & 0x87;
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break;
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case 0xcc ... 0xcf:
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dev->pci_conf[addr] = val;
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break;
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case 0xd0:
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dev->pci_conf[addr] = val & 0x80;
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break;
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case 0xd2:
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dev->pci_conf[addr] = val & 0x40;
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break;
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case 0xd3:
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dev->pci_conf[addr] = val & 0xb0;
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break;
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case 0xd4:
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dev->pci_conf[addr] = val;
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break;
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case 0xd5:
|
|
dev->pci_conf[addr] = val & 0xef;
|
|
break;
|
|
case 0xd6:
|
|
case 0xd7:
|
|
dev->pci_conf[addr] = val;
|
|
break;
|
|
|
|
case 0xf0 ... 0xff:
|
|
dev->pci_conf[addr] = val;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint8_t
|
|
ali1621_read(UNUSED(int func), int addr, void *priv)
|
|
{
|
|
const ali1621_t *dev = (ali1621_t *) priv;
|
|
uint8_t ret = 0xff;
|
|
|
|
ret = dev->pci_conf[addr];
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
ali1621_reset(void *priv)
|
|
{
|
|
ali1621_t *dev = (ali1621_t *) priv;
|
|
|
|
/* Default Registers */
|
|
dev->pci_conf[0x00] = 0xb9;
|
|
dev->pci_conf[0x01] = 0x10;
|
|
dev->pci_conf[0x02] = 0x21;
|
|
dev->pci_conf[0x03] = 0x16;
|
|
dev->pci_conf[0x04] = 0x06;
|
|
dev->pci_conf[0x05] = 0x00;
|
|
dev->pci_conf[0x06] = 0x10;
|
|
dev->pci_conf[0x07] = 0x04;
|
|
dev->pci_conf[0x08] = 0x01;
|
|
dev->pci_conf[0x09] = 0x00;
|
|
dev->pci_conf[0x0a] = 0x00;
|
|
dev->pci_conf[0x0b] = 0x06;
|
|
dev->pci_conf[0x10] = 0x08;
|
|
dev->pci_conf[0x34] = 0xb0;
|
|
dev->pci_conf[0x40] = 0x0c;
|
|
dev->pci_conf[0x41] = 0x0c;
|
|
dev->pci_conf[0x4c] = 0x04;
|
|
dev->pci_conf[0x4d] = 0x04;
|
|
dev->pci_conf[0x4e] = 0x7f;
|
|
dev->pci_conf[0x4f] = 0x7f;
|
|
dev->pci_conf[0x50] = 0x0c;
|
|
dev->pci_conf[0x53] = 0x02;
|
|
dev->pci_conf[0x5a] = 0x02;
|
|
dev->pci_conf[0x63] = 0x02;
|
|
dev->pci_conf[0x6c] = dev->pci_conf[0x70] = dev->pci_conf[0x74] = dev->pci_conf[0x78] = 0xff;
|
|
dev->pci_conf[0x6d] = dev->pci_conf[0x71] = dev->pci_conf[0x75] = dev->pci_conf[0x79] = 0xff;
|
|
dev->pci_conf[0x6e] = dev->pci_conf[0x72] = dev->pci_conf[0x76] = dev->pci_conf[0x7a] = 0x00;
|
|
dev->pci_conf[0x6f] = dev->pci_conf[0x73] = dev->pci_conf[0x77] = dev->pci_conf[0x7b] = 0xe0;
|
|
dev->pci_conf[0x6f] |= 0x06;
|
|
dev->pci_conf[0x7c] = 0x11;
|
|
dev->pci_conf[0x7d] = 0xc4;
|
|
dev->pci_conf[0x7e] = 0xc7;
|
|
dev->pci_conf[0x80] = 0x01;
|
|
dev->pci_conf[0x81] = 0xc0;
|
|
dev->pci_conf[0x8e] = 0x01;
|
|
dev->pci_conf[0xa0] = 0x20;
|
|
dev->pci_conf[0xb0] = 0x02;
|
|
dev->pci_conf[0xb2] = 0x10;
|
|
dev->pci_conf[0xb4] = 0x03;
|
|
dev->pci_conf[0xb5] = 0x02;
|
|
dev->pci_conf[0xb7] = 0x20;
|
|
dev->pci_conf[0xc0] = 0x80;
|
|
dev->pci_conf[0xc9] = 0x28;
|
|
dev->pci_conf[0xd4] = 0x10;
|
|
dev->pci_conf[0xd5] = 0x01;
|
|
dev->pci_conf[0xf0] = dev->pci_conf[0xf4] = dev->pci_conf[0xf8] = dev->pci_conf[0xfc] = 0x20;
|
|
dev->pci_conf[0xf1] = dev->pci_conf[0xf5] = dev->pci_conf[0xf9] = dev->pci_conf[0xfd] = 0x43;
|
|
dev->pci_conf[0xf2] = dev->pci_conf[0xf6] = dev->pci_conf[0xfa] = dev->pci_conf[0xfe] = 0x21;
|
|
dev->pci_conf[0xf3] = dev->pci_conf[0xf7] = dev->pci_conf[0xfb] = dev->pci_conf[0xff] = 0x43;
|
|
|
|
ali1621_write(0, 0x83, 0x08, dev);
|
|
|
|
for (uint8_t i = 0; i < 4; i++)
|
|
ali1621_write(0, 0x84 + i, 0x00, dev);
|
|
}
|
|
|
|
static void
|
|
ali1621_close(void *priv)
|
|
{
|
|
ali1621_t *dev = (ali1621_t *) priv;
|
|
|
|
smram_del(dev->smram[1]);
|
|
smram_del(dev->smram[0]);
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void *
|
|
ali1621_init(UNUSED(const device_t *info))
|
|
{
|
|
ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
|
|
memset(dev, 0, sizeof(ali1621_t));
|
|
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev, &dev->pci_slot);
|
|
|
|
dev->smram[0] = smram_add();
|
|
dev->smram[1] = smram_add();
|
|
|
|
ali1621_reset(dev);
|
|
|
|
device_add(&ali5247_agp_device);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t ali1621_device = {
|
|
.name = "ALi M1621 CPU-to-PCI Bridge",
|
|
.internal_name = "ali1621",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0,
|
|
.init = ali1621_init,
|
|
.close = ali1621_close,
|
|
.reset = ali1621_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = NULL,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|