601 lines
16 KiB
C
601 lines
16 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of Intel 82420EX chipset that acts as both the
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* northbridge and the southbridge.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#define USE_DRB_HACK
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/apm.h>
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#include <86box/dma.h>
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#include <86box/mem.h>
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#include <86box/smram.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc.h>
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#include <86box/machine.h>
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#include <86box/chipset.h>
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#include <86box/spd.h>
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#ifndef USE_DRB_HACK
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#include <86box/row.h>
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#endif
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#define MEM_STATE_SHADOW_R 0x01
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#define MEM_STATE_SHADOW_W 0x02
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#define MEM_STATE_SMRAM 0x04
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typedef struct i420ex_t {
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uint8_t has_ide;
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uint8_t smram_locked;
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uint8_t pci_slot;
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uint8_t pad;
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uint8_t regs[256];
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uint16_t timer_base;
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uint16_t timer_latch;
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smram_t *smram;
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double fast_off_period;
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pc_timer_t timer;
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pc_timer_t fast_off_timer;
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apm_t *apm;
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port_92_t *port_92;
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} i420ex_t;
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#ifdef ENABLE_I420EX_LOG
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int i420ex_do_log = ENABLE_I420EX_LOG;
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static void
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i420ex_log(const char *fmt, ...)
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{
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va_list ap;
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if (i420ex_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define i420ex_log(fmt, ...)
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#endif
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static void
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i420ex_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3) {
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case 0:
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mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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break;
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case 2:
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mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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default:
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break;
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}
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flushmmucache_nopc();
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}
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static void
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i420ex_smram_handler_phase0(void)
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{
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/* Disable low extended SMRAM. */
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smram_disable_all();
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}
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static void
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i420ex_smram_handler_phase1(i420ex_t *dev)
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{
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const uint8_t *regs = (uint8_t *) dev->regs;
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uint32_t host_base = 0x000a0000;
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uint32_t ram_base = 0x000a0000;
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uint32_t size = 0x00010000;
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switch (regs[0x70] & 0x07) {
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default:
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case 0:
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case 1:
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host_base = ram_base = 0x00000000;
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size = 0x00000000;
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break;
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case 2:
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host_base = 0x000a0000;
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ram_base = 0x000a0000;
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break;
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case 3:
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host_base = 0x000b0000;
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ram_base = 0x000b0000;
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break;
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case 4:
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host_base = 0x000c0000;
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ram_base = 0x000a0000;
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break;
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case 5:
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host_base = 0x000d0000;
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ram_base = 0x000a0000;
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break;
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case 6:
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host_base = 0x000e0000;
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ram_base = 0x000a0000;
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break;
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case 7:
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host_base = 0x000f0000;
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ram_base = 0x000a0000;
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break;
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}
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smram_enable(dev->smram, host_base, ram_base, size,
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(regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20));
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}
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#ifndef USE_DRB_HACK
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static void
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i420ex_drb_recalc(i420ex_t *dev)
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{
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uint32_t boundary;
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for (int8_t i = 4; i >= 0; i--)
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row_disable(i);
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for (uint8_t i = 0; i <= 4; i++) {
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boundary = ((uint32_t) dev->regs[0x60 + i]) & 0xff;
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row_set_boundary(i, boundary);
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}
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flushmmucache();
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}
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#endif
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static void
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i420ex_write(int func, int addr, uint8_t val, void *priv)
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{
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i420ex_t *dev = (i420ex_t *) priv;
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if (func > 0)
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return;
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if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40))
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return;
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switch (addr) {
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case 0x05:
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dev->regs[addr] = (val & 0x01);
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break;
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case 0x07:
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dev->regs[addr] &= ~(val & 0xf0);
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break;
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case 0x40:
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dev->regs[addr] = (val & 0x7f);
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break;
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case 0x44:
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dev->regs[addr] = (val & 0x07);
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break;
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case 0x48:
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dev->regs[addr] = (val & 0x3f);
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if (dev->has_ide) {
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ide_pri_disable();
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switch (val & 0x03) {
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case 0x01:
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ide_set_base(0, 0x01f0);
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ide_set_side(0, 0x03f6);
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ide_pri_enable();
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break;
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case 0x02:
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ide_set_base(0, 0x0170);
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ide_set_side(0, 0x0376);
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ide_pri_enable();
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break;
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default:
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break;
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}
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}
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break;
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case 0x49:
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case 0x53:
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dev->regs[addr] = (val & 0x1f);
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break;
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case 0x4c:
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case 0x51:
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case 0x57:
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case 0x68:
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case 0x69:
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dev->regs[addr] = val;
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if (addr == 0x4c) {
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dma_alias_remove();
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if (!(val & 0x80))
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dma_alias_set();
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}
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break;
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case 0x4d:
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dev->regs[addr] = (dev->regs[addr] & 0xef) | (val & 0x10);
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break;
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case 0x4e:
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dev->regs[addr] = (val & 0xf7);
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break;
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case 0x50:
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dev->regs[addr] = (val & 0x0f);
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break;
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case 0x52:
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dev->regs[addr] = (val & 0x7f);
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break;
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case 0x56:
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dev->regs[addr] = (val & 0x3e);
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break;
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case 0x59: /* PAM0 */
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if ((dev->regs[0x59] ^ val) & 0xf0) {
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i420ex_map(0xf0000, 0x10000, val >> 4);
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shadowbios = (val & 0x10);
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}
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dev->regs[0x59] = val & 0xf0;
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break;
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case 0x5a: /* PAM1 */
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if ((dev->regs[0x5a] ^ val) & 0x0f)
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i420ex_map(0xc0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5a] ^ val) & 0xf0)
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i420ex_map(0xc4000, 0x04000, val >> 4);
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dev->regs[0x5a] = val;
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break;
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case 0x5b: /*PAM2 */
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if ((dev->regs[0x5b] ^ val) & 0x0f)
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i420ex_map(0xc8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5b] ^ val) & 0xf0)
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i420ex_map(0xcc000, 0x04000, val >> 4);
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dev->regs[0x5b] = val;
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break;
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case 0x5c: /*PAM3 */
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if ((dev->regs[0x5c] ^ val) & 0x0f)
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i420ex_map(0xd0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5c] ^ val) & 0xf0)
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i420ex_map(0xd4000, 0x04000, val >> 4);
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dev->regs[0x5c] = val;
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break;
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case 0x5d: /* PAM4 */
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if ((dev->regs[0x5d] ^ val) & 0x0f)
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i420ex_map(0xd8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5d] ^ val) & 0xf0)
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i420ex_map(0xdc000, 0x04000, val >> 4);
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dev->regs[0x5d] = val;
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break;
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case 0x5e: /* PAM5 */
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if ((dev->regs[0x5e] ^ val) & 0x0f)
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i420ex_map(0xe0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5e] ^ val) & 0xf0)
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i420ex_map(0xe4000, 0x04000, val >> 4);
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dev->regs[0x5e] = val;
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break;
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case 0x5f: /* PAM6 */
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if ((dev->regs[0x5f] ^ val) & 0x0f)
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i420ex_map(0xe8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5f] ^ val) & 0xf0)
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i420ex_map(0xec000, 0x04000, val >> 4);
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dev->regs[0x5f] = val;
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break;
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case 0x60:
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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#ifdef USE_DRB_HACK
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spd_write_drbs(dev->regs, 0x60, 0x64, 1);
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#else
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dev->regs[addr] = val;
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i420ex_drb_recalc(dev);
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#endif
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break;
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case 0x66:
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case 0x67:
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i420ex_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x01), val);
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dev->regs[addr] = val & 0x8f;
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA + (addr & 0x01), PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA + (addr & 0x01), val & 0xf);
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break;
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case 0x70: /* SMRAM */
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i420ex_smram_handler_phase0();
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if (dev->smram_locked)
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dev->regs[0x70] = (dev->regs[0x70] & 0xdf) | (val & 0x20);
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else {
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dev->regs[0x70] = (dev->regs[0x70] & 0x88) | (val & 0x77);
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dev->smram_locked = (val & 0x10);
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if (dev->smram_locked)
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dev->regs[0x70] &= 0xbf;
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}
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i420ex_smram_handler_phase1(dev);
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break;
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case 0xa0:
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dev->regs[addr] = val & 0x1f;
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apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80));
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switch ((val & 0x18) >> 3) {
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case 0x00:
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dev->fast_off_period = PCICLK * 32768.0 * 60000.0;
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break;
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case 0x01:
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default:
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dev->fast_off_period = 0.0;
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break;
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case 0x02:
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dev->fast_off_period = PCICLK;
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break;
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case 0x03:
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dev->fast_off_period = PCICLK * 32768.0;
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break;
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}
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cpu_fast_off_count = cpu_fast_off_val + 1;
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cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
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break;
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case 0xa2:
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dev->regs[addr] = val & 0xff;
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apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80));
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break;
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case 0xaa:
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dev->regs[addr] &= (val & 0xff);
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break;
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case 0xac:
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case 0xae:
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dev->regs[addr] = val & 0xff;
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break;
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case 0xa4:
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dev->regs[addr] = val & 0xfb;
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cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr];
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break;
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case 0xa5:
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dev->regs[addr] = val;
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cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8);
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break;
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case 0xa7:
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dev->regs[addr] = val & 0xe0;
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cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24);
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break;
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case 0xa8:
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dev->regs[addr] = val & 0xff;
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cpu_fast_off_val = val;
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cpu_fast_off_count = val + 1;
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cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
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break;
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default:
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break;
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}
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}
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static uint8_t
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i420ex_read(int func, int addr, void *priv)
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{
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const i420ex_t *dev = (i420ex_t *) priv;
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uint8_t ret;
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ret = 0xff;
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if (func == 0)
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ret = dev->regs[addr];
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return ret;
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}
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static void
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i420ex_reset_hard(void *priv)
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{
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i420ex_t *dev = (i420ex_t *) priv;
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memset(dev->regs, 0, 256);
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dev->regs[0x00] = 0x86;
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dev->regs[0x01] = 0x80; /*Intel*/
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dev->regs[0x02] = 0x86;
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dev->regs[0x03] = 0x04; /*82378IB (I420EX)*/
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dev->regs[0x04] = 0x07;
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dev->regs[0x07] = 0x02;
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dev->regs[0x4c] = 0x4d;
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dev->regs[0x4e] = 0x03;
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/* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */
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if (cpu_busspeed >= 33333333)
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dev->regs[0x50] |= 0x02;
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dev->regs[0x51] = 0x80;
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dev->regs[0x60] = dev->regs[0x61] = dev->regs[0x62] = dev->regs[0x63] = dev->regs[0x64] = 0x01;
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dev->regs[0x66] = 0x80;
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dev->regs[0x67] = 0x80;
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dev->regs[0x69] = 0x02;
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dev->regs[0xa0] = 0x08;
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dev->regs[0xa8] = 0x0f;
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mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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if (dev->has_ide)
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ide_pri_disable();
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}
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static void
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i420ex_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
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{
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i420ex_t *dev = (i420ex_t *) priv;
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if (dev->apm->do_smi)
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dev->regs[0xaa] |= 0x80;
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}
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static void
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i420ex_fast_off_count(void *priv)
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{
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i420ex_t *dev = (i420ex_t *) priv;
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cpu_fast_off_count--;
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smi_raise();
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dev->regs[0xaa] |= 0x20;
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}
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static void
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i420ex_reset(void *priv)
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{
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i420ex_t *dev = (i420ex_t *) priv;
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i420ex_write(0, 0x48, 0x00, priv);
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/* Disable the PIC mouse latch. */
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i420ex_write(0, 0x4e, 0x03, priv);
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for (uint8_t i = 0; i < 7; i++)
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i420ex_write(0, 0x59 + i, 0x00, priv);
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for (uint8_t i = 0; i <= 4; i++)
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dev->regs[0x60 + i] = 0x01;
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dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
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dev->smram_locked = 0;
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i420ex_write(0, 0x70, 0x00, priv);
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mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
|
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
|
|
|
|
i420ex_write(0, 0xa0, 0x08, priv);
|
|
i420ex_write(0, 0xa2, 0x00, priv);
|
|
i420ex_write(0, 0xa4, 0x00, priv);
|
|
i420ex_write(0, 0xa5, 0x00, priv);
|
|
i420ex_write(0, 0xa6, 0x00, priv);
|
|
i420ex_write(0, 0xa7, 0x00, priv);
|
|
i420ex_write(0, 0xa8, 0x0f, priv);
|
|
}
|
|
|
|
static void
|
|
i420ex_close(void *priv)
|
|
{
|
|
i420ex_t *dev = (i420ex_t *) priv;
|
|
|
|
smram_del(dev->smram);
|
|
|
|
free(dev);
|
|
}
|
|
|
|
static void
|
|
i420ex_speed_changed(void *priv)
|
|
{
|
|
i420ex_t *dev = (i420ex_t *) priv;
|
|
int te;
|
|
|
|
te = timer_is_enabled(&dev->timer);
|
|
|
|
timer_disable(&dev->timer);
|
|
if (te)
|
|
timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
|
|
|
|
te = timer_is_on(&dev->fast_off_timer);
|
|
|
|
timer_stop(&dev->fast_off_timer);
|
|
if (te)
|
|
timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
|
|
}
|
|
|
|
static void *
|
|
i420ex_init(const device_t *info)
|
|
{
|
|
i420ex_t *dev = (i420ex_t *) malloc(sizeof(i420ex_t));
|
|
memset(dev, 0, sizeof(i420ex_t));
|
|
|
|
dev->smram = smram_add();
|
|
|
|
pci_add_card(PCI_ADD_NORTHBRIDGE, i420ex_read, i420ex_write, dev, &dev->pci_slot);
|
|
|
|
dev->has_ide = info->local;
|
|
|
|
timer_add(&dev->fast_off_timer, i420ex_fast_off_count, dev, 0);
|
|
|
|
cpu_fast_off_flags = 0x00000000;
|
|
|
|
cpu_fast_off_val = dev->regs[0xa8];
|
|
cpu_fast_off_count = cpu_fast_off_val + 1;
|
|
|
|
cpu_register_fast_off_handler(&dev->fast_off_timer);
|
|
|
|
dev->apm = device_add(&apm_pci_device);
|
|
/* APM intercept handler to update 82420EX SMI status on APM SMI. */
|
|
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, i420ex_apm_out, NULL, NULL, dev);
|
|
|
|
dev->port_92 = device_add(&port_92_pci_device);
|
|
|
|
dma_alias_set();
|
|
|
|
device_add(&ide_pci_2ch_device);
|
|
|
|
#ifndef USE_DRB_HACK
|
|
row_device.local = 4 | (1 << 8) | (0x01 << 16) | (8 << 24);
|
|
device_add((const device_t *) &row_device);
|
|
#endif
|
|
|
|
i420ex_reset_hard(dev);
|
|
|
|
return dev;
|
|
}
|
|
|
|
const device_t i420ex_device = {
|
|
.name = "Intel 82420EX",
|
|
.internal_name = "i420ex",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x00,
|
|
.init = i420ex_init,
|
|
.close = i420ex_close,
|
|
.reset = i420ex_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = i420ex_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|
|
|
|
const device_t i420ex_ide_device = {
|
|
.name = "Intel 82420EX (With IDE)",
|
|
.internal_name = "i420ex_ide",
|
|
.flags = DEVICE_PCI,
|
|
.local = 0x01,
|
|
.init = i420ex_init,
|
|
.close = i420ex_close,
|
|
.reset = i420ex_reset,
|
|
{ .available = NULL },
|
|
.speed_changed = i420ex_speed_changed,
|
|
.force_redraw = NULL,
|
|
.config = NULL
|
|
};
|