155 lines
5.7 KiB
C
155 lines
5.7 KiB
C
/*87C716 'SDAC' true colour RAMDAC emulation*/
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/*Misidentifies as AT&T 21C504*/
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#include "ibm.h"
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#include "mem.h"
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#include "video.h"
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#include "vid_svga.h"
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#include "vid_sdac_ramdac.h"
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/* Returning divider * 2 */
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int sdac_get_clock_divider(sdac_ramdac_t *ramdac)
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{
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switch (ramdac->command >> 4)
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{
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case 0x1: return 1;
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case 0x0: case 0x3: case 0x5: return 2;
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case 0x9: return 3;
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case 0x2: case 0x6: case 0x7: case 0x8: case 0xa: case 0xc: return 4;
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case 0x4: case 0xe: return 6;
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default: return 2;
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}
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}
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void sdac_ramdac_out(uint16_t addr, uint8_t val, sdac_ramdac_t *ramdac, svga_t *svga)
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{
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// /*if (CS!=0xC000) */pclog("OUT RAMDAC %04X %02X %i %04X:%04X %i\n",addr,val,sdac_ramdac.magic_count,CS,pc, sdac_ramdac.rs2);
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switch (addr)
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{
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case 0x3C6:
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if (val == 0xff)
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{
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ramdac->rs2 = 0;
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ramdac->magic_count = 0;
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break;
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}
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if (ramdac->magic_count < 4) break;
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if (ramdac->magic_count == 4)
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{
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ramdac->command = val;
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// pclog("RAMDAC command reg now %02X\n", val);
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switch (val >> 4)
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{
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case 0x2: case 0x3: case 0x8: case 0xa: svga->bpp = 15; break;
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case 0x4: case 0x9: case 0xe: svga->bpp = 24; break;
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case 0x5: case 0x6: case 0xc: svga->bpp = 16; break;
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case 0x7: svga->bpp = 32; break;
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case 0: case 1: default: svga->bpp = 8; break;
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}
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svga_recalctimings(svga);
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}
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//ramdac->magic_count = 0;
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break;
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case 0x3C7:
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ramdac->magic_count = 0;
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if (ramdac->rs2)
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ramdac->rindex = val;
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break;
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case 0x3C8:
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ramdac->magic_count = 0;
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if (ramdac->rs2)
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ramdac->windex = val;
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break;
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case 0x3C9:
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ramdac->magic_count = 0;
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if (ramdac->rs2)
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{
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if (!ramdac->reg_ff) ramdac->regs[ramdac->windex] = (ramdac->regs[ramdac->windex] & 0xff00) | val;
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else ramdac->regs[ramdac->windex] = (ramdac->regs[ramdac->windex] & 0x00ff) | (val << 8);
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ramdac->reg_ff = !ramdac->reg_ff;
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// pclog("RAMDAC reg %02X now %04X\n", ramdac->windex, ramdac->regs[ramdac->windex]);
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if (!ramdac->reg_ff) ramdac->windex++;
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}
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break;
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}
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svga_out(addr, val, svga);
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}
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uint8_t sdac_ramdac_in(uint16_t addr, sdac_ramdac_t *ramdac, svga_t *svga)
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{
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uint8_t temp;
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// /*if (CS!=0xC000) */pclog("IN RAMDAC %04X %04X:%04X %i\n",addr,CS,pc, ramdac->rs2);
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switch (addr)
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{
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case 0x3C6:
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ramdac->reg_ff = 0;
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if (ramdac->magic_count < 5)
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ramdac->magic_count++;
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if (ramdac->magic_count == 4)
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{
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temp = 0x70; /*SDAC ID*/
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ramdac->rs2 = 1;
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}
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if (ramdac->magic_count == 5)
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{
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temp = ramdac->command;
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ramdac->magic_count = 0;
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}
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return temp;
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case 0x3C7:
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// if (ramdac->magic_count < 4)
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// {
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ramdac->magic_count=0;
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// break;
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// }
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if (ramdac->rs2) return ramdac->rindex;
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break;
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case 0x3C8:
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// if (ramdac->magic_count < 4)
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// {
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ramdac->magic_count=0;
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// break;
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// }
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if (ramdac->rs2) return ramdac->windex;
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break;
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case 0x3C9:
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// if (ramdac->magic_count < 4)
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// {
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ramdac->magic_count=0;
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// break;
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// }
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if (ramdac->rs2)
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{
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if (!ramdac->reg_ff) temp = ramdac->regs[ramdac->rindex] & 0xff;
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else temp = ramdac->regs[ramdac->rindex] >> 8;
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ramdac->reg_ff = !ramdac->reg_ff;
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if (!ramdac->reg_ff)
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{
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ramdac->rindex++;
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ramdac->magic_count = 0;
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}
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return temp;
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}
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break;
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}
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return svga_in(addr, svga);
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}
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float sdac_getclock(int clock, void *p)
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{
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sdac_ramdac_t *ramdac = (sdac_ramdac_t *)p;
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float t;
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int m, n1, n2;
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// pclog("SDAC_Getclock %i %04X\n", clock, ramdac->regs[clock]);
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if (clock == 0) return 25175000.0;
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if (clock == 1) return 28322000.0;
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clock ^= 1; /*Clocks 2 and 3 seem to be reversed*/
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m = (ramdac->regs[clock] & 0x7f) + 2;
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n1 = ((ramdac->regs[clock] >> 8) & 0x1f) + 2;
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n2 = ((ramdac->regs[clock] >> 13) & 0x07);
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t = (14318184.0 * ((float)m / (float)n1)) / (float)(1 << n2);
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// pclog("SDAC clock %i %i %i %f %04X %f %i\n", m, n1, n2, t, ramdac->regs[2], 14318184.0 * ((float)m / (float)n1), 1 << n2);
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return t;
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}
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