315 lines
9.1 KiB
C
315 lines
9.1 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of a generic ALi M7101-compatible SMBus host
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* controller.
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*
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* Authors: RichardG, <richardg867@gmail.com>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020-2021 RichardG.
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* Copyright 2021 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/timer.h>
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#include <86box/i2c.h>
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#include <86box/smbus.h>
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#include <86box/plat_fallthrough.h>
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#ifdef ENABLE_SMBUS_ALI7101_LOG
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int smbus_ali7101_do_log = ENABLE_SMBUS_ALI7101_LOG;
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static void
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smbus_ali7101_log(const char *fmt, ...)
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{
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va_list ap;
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if (smbus_ali7101_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define smbus_ali7101_log(fmt, ...)
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#endif
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static uint8_t
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smbus_ali7101_read(uint16_t addr, void *priv)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
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uint8_t ret = 0x00;
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switch (addr - dev->io_base) {
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case 0x00:
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ret = dev->stat;
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break;
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case 0x03:
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ret = dev->addr;
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break;
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case 0x04:
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ret = dev->data0;
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break;
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case 0x05:
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ret = dev->data1;
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break;
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case 0x06:
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ret = dev->data[dev->index++];
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if (dev->index >= SMBUS_ALI7101_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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case 0x07:
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ret = dev->cmd;
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break;
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default:
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break;
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}
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smbus_ali7101_log("SMBus ALI7101: read(%02X) = %02x\n", addr, ret);
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return ret;
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}
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static void
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smbus_ali7101_write(uint16_t addr, uint8_t val, void *priv)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
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uint8_t smbus_addr;
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uint8_t cmd;
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uint8_t read;
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uint8_t prev_stat;
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uint16_t timer_bytes = 0;
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smbus_ali7101_log("SMBus ALI7101: write(%02X, %02X)\n", addr, val);
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prev_stat = dev->next_stat;
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dev->next_stat = 0x04;
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switch (addr - dev->io_base) {
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case 0x00:
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dev->stat &= ~(val & 0xf2);
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/* Make sure IDLE is set if we're not busy or errored. */
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if (dev->stat == 0x00)
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dev->stat = 0x04;
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break;
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case 0x01:
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dev->ctl = val & 0xfc;
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if (val & 0x04) { /* cancel an in-progress command if KILL is set */
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if (prev_stat) { /* cancel only if a command is in progress */
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timer_disable(&dev->response_timer);
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dev->stat = 0x80; /* raise FAILED */
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}
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} else if (val & 0x08) { /* T_OUT_CMD */
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if (prev_stat) { /* cancel only if a command is in progress */
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timer_disable(&dev->response_timer);
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dev->stat = 0x20; /* raise DEVICE_ERR */
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}
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}
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if (val & 0x80)
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dev->index = 0;
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break;
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case 0x02:
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/* dispatch command if START is set */
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timer_bytes++; /* address */
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smbus_addr = (dev->addr >> 1);
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read = dev->addr & 0x01;
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cmd = (dev->ctl >> 4) & 0x7;
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smbus_ali7101_log("SMBus ALI7101: addr=%02X read=%d protocol=%X cmd=%02X data0=%02X data1=%02X\n", smbus_addr, read, cmd, dev->cmd, dev->data0, dev->data1);
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/* Raise DEV_ERR if no device is at this address, or if the device returned NAK when starting the transfer. */
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if (!i2c_start(i2c_smbus, smbus_addr, read)) {
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dev->next_stat = 0x40;
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break;
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}
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dev->next_stat = 0x10; /* raise INTER (command completed) by default */
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/* Decode the command protocol. */
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switch (cmd) {
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case 0x0: /* quick R/W */
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break;
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case 0x1: /* byte R/W */
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if (read) /* byte read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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timer_bytes++;
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break;
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case 0x2: /* byte data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) /* byte read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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else /* byte write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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timer_bytes++;
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break;
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case 0x3: /* word data R/W */
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/* command write */
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i2c_write(i2c_smbus, smbus_addr, dev->cmd);
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timer_bytes++;
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if (read) { /* word read */
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dev->data0 = i2c_read(i2c_smbus, smbus_addr);
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dev->data1 = i2c_read(i2c_smbus, smbus_addr);
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} else { /* word write */
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i2c_write(i2c_smbus, smbus_addr, dev->data0);
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i2c_write(i2c_smbus, smbus_addr, dev->data1);
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}
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timer_bytes += 2;
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break;
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case 0x4: /* block R/W */
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timer_bytes++; /* count the SMBus length byte now */
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fallthrough;
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default: /* unknown */
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dev->next_stat = 0x20; /* raise DEV_ERR */
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timer_bytes = 0;
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break;
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}
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/* Finish transfer. */
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i2c_stop(i2c_smbus, smbus_addr);
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break;
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case 0x03:
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dev->addr = val;
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break;
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case 0x04:
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dev->data0 = val;
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break;
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case 0x05:
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dev->data1 = val;
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break;
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case 0x06:
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dev->data[dev->index++] = val;
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if (dev->index >= SMBUS_ALI7101_BLOCK_DATA_SIZE)
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dev->index = 0;
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break;
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case 0x07:
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dev->cmd = val;
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break;
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default:
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break;
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}
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if (dev->next_stat != 0x04) { /* schedule dispatch of any pending status register update */
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dev->stat = 0x08; /* raise HOST_BUSY while waiting */
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timer_disable(&dev->response_timer);
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/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * 60us period measured on real VIA 686B */
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timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * 60 * TIMER_USEC);
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}
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}
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static void
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smbus_ali7101_response(void *priv)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
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/* Dispatch the status register update. */
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dev->stat = dev->next_stat;
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}
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void
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smbus_ali7101_remap(smbus_ali7101_t *dev, uint16_t new_io_base, uint8_t enable)
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{
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if (dev->io_base)
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io_removehandler(dev->io_base, 0x10, smbus_ali7101_read, NULL, NULL, smbus_ali7101_write, NULL, NULL, dev);
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dev->io_base = new_io_base;
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smbus_ali7101_log("SMBus ALI7101: remap to %04Xh (%sabled)\n", dev->io_base, enable ? "en" : "dis");
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if (enable && dev->io_base)
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io_sethandler(dev->io_base, 0x10, smbus_ali7101_read, NULL, NULL, smbus_ali7101_write, NULL, NULL, dev);
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}
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static void
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smbus_ali7101_reset(void *priv)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
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timer_disable(&dev->response_timer);
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dev->stat = 0x04;
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}
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static void *
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smbus_ali7101_init(const device_t *info)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) malloc(sizeof(smbus_ali7101_t));
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memset(dev, 0, sizeof(smbus_ali7101_t));
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dev->local = info->local;
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dev->stat = 0x04;
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/* We save the I2C bus handle on dev but use i2c_smbus for all operations because
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dev and therefore dev->i2c will be invalidated if a device triggers a hard reset. */
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i2c_smbus = dev->i2c = i2c_addbus("smbus_ali7101");
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timer_add(&dev->response_timer, smbus_ali7101_response, dev, 0);
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return dev;
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}
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static void
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smbus_ali7101_close(void *priv)
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{
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smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
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if (i2c_smbus == dev->i2c)
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i2c_smbus = NULL;
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i2c_removebus(dev->i2c);
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free(dev);
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}
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const device_t ali7101_smbus_device = {
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.name = "ALi M7101-compatible SMBus Host Controller",
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.internal_name = "ali7101_smbus",
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.flags = DEVICE_AT,
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.local = 0,
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.init = smbus_ali7101_init,
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.close = smbus_ali7101_close,
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.reset = smbus_ali7101_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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