0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
275 lines
7.6 KiB
C
275 lines
7.6 KiB
C
/*Cyrix-only instructions*/
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/*System Management Mode*/
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static void opSVDC_common(uint32_t fetchdat)
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{
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_es);
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writememw(0, easeg+cpu_state.eaaddr+8, ES);
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break;
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case 0x08: /*CS*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_cs);
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writememw(0, easeg+cpu_state.eaaddr+8, CS);
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break;
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case 0x18: /*DS*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ds);
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writememw(0, easeg+cpu_state.eaaddr+8, DS);
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break;
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case 0x10: /*SS*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ss);
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writememw(0, easeg+cpu_state.eaaddr+8, SS);
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break;
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case 0x20: /*FS*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_fs);
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writememw(0, easeg+cpu_state.eaaddr+8, FS);
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break;
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case 0x28: /*GS*/
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_gs);
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writememw(0, easeg+cpu_state.eaaddr+8, GS);
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break;
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default:
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pclog("opSVDC: unknown rmdat %02x\n", rmdat);
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x86illegal();
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}
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}
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static int opSVDC_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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opSVDC_common(fetchdat);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSVDC_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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opSVDC_common(fetchdat);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static void opRSDC_common(uint32_t fetchdat)
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{
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_es);
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break;
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case 0x18: /*DS*/
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ds);
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break;
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case 0x10: /*SS*/
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_ss);
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break;
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case 0x20: /*FS*/
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_fs);
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break;
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case 0x28: /*GS*/
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_gs);
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break;
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default:
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pclog("opRSDC: unknown rmdat %02x\n", rmdat);
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x86illegal();
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}
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}
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static int opRSDC_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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opRSDC_common(fetchdat);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opRSDC_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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opRSDC_common(fetchdat);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSVLDT_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
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writememw(0, easeg+cpu_state.eaaddr+8, ldt.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSVLDT_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
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writememw(0, easeg+cpu_state.eaaddr+8, ldt.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opRSLDT_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opRSLDT_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_READ(cpu_state.ea_seg);
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cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &ldt);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSVTS_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
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writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSVTS_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
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writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opRSTS_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_16(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
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writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opRSTS_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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{
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fetch_ea_32(fetchdat);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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cyrix_write_seg_descriptor(easeg+cpu_state.eaaddr, &tr);
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writememw(0, easeg+cpu_state.eaaddr+8, tr.seg);
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}
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else
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x86illegal();
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return cpu_state.abrt;
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}
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static int opSMINT(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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fatal("opSMINT\n");
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else
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x86illegal();
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return 1;
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}
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static int opRDSHR_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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fatal("opRDSHR_a16\n");
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else
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x86illegal();
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return 1;
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}
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static int opRDSHR_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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fatal("opRDSHR_a32\n");
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else
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x86illegal();
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return 1;
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}
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static int opWRSHR_a16(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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fatal("opWRSHR_a16\n");
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else
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x86illegal();
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return 1;
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}
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static int opWRSHR_a32(uint32_t fetchdat)
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{
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if (cpu_cur_status & CPU_STATUS_SMM)
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fatal("opWRSHR_a32\n");
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else
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x86illegal();
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return 1;
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}
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