162 lines
4.2 KiB
C
162 lines
4.2 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ETEQ Cheetah ET6000 chipset.
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*
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* Authors: Tiseno100
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*
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* Copyright 2021 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/pit.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#define INDEX (dev->index - 0x10)
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typedef struct
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{
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uint8_t index, regs[6];
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} et6000_t;
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#ifdef ENABLE_ET6000_LOG
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int et6000_do_log = ENABLE_ET6000_LOG;
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static void
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et6000_log(const char *fmt, ...)
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{
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va_list ap;
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if (et6000_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define et6000_log(fmt, ...)
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#endif
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static void et6000_shadow_control(int base, int size, int can_read, int can_write)
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{
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mem_set_mem_state_both(base, size, (can_read ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (can_write ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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flushmmucache_nopc();
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}
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static void
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et6000_write(uint16_t addr, uint8_t val, void *priv)
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{
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et6000_t *dev = (et6000_t *)priv;
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switch (addr)
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{
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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switch (INDEX)
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{
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case 0: /* System Configuration Register */
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dev->regs[INDEX] = val & 0xdf;
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et6000_shadow_control(0xa0000, 0x20000, val & 1, val & 1);
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refresh_at_enable = !(val & 0x10);
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break;
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case 1: /* CACHE Configuration and Non-Cacheable Block Size */
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dev->regs[INDEX] = val & 0xf0;
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break;
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case 2: /* Non-Cacheable Block Address Register */
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dev->regs[INDEX] = val & 0xfe;
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break;
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case 3: /* DRAM Bank and Type Configuration Register */
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dev->regs[INDEX] = val;
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break;
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case 4: /* DRAM Configuration Register */
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dev->regs[INDEX] = val;
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et6000_shadow_control(0xc0000, 0x10000, (dev->regs[0x15] & 2) && (val & 0x20), (dev->regs[0x15] & 2) && (val & 0x20) && (dev->regs[0x15] & 1));
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et6000_shadow_control(0xd0000, 0x10000, (dev->regs[0x15] & 8) && (val & 0x20), (dev->regs[0x15] & 8) && (val & 0x20) && (dev->regs[0x15] & 4));
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break;
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case 5: /* Shadow RAM Configuration Register */
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dev->regs[INDEX] = val;
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et6000_shadow_control(0xc0000, 0x10000, (val & 2) && (dev->regs[0x14] & 0x20), (val & 2) && (dev->regs[0x14] & 0x20) && (val & 1));
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et6000_shadow_control(0xd0000, 0x10000, (val & 8) && (dev->regs[0x14] & 0x20), (val & 8) && (dev->regs[0x14] & 0x20) && (val & 4));
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et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10));
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et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40));
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break;
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}
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et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]);
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break;
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}
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}
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static uint8_t
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et6000_read(uint16_t addr, void *priv)
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{
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et6000_t *dev = (et6000_t *)priv;
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return ((addr == 0x23) && (INDEX >= 0) && (INDEX <= 5)) ? dev->regs[INDEX] : 0xff;
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}
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static void
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et6000_close(void *priv)
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{
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et6000_t *dev = (et6000_t *)priv;
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free(dev);
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}
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static void *
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et6000_init(const device_t *info)
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{
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et6000_t *dev = (et6000_t *)malloc(sizeof(et6000_t));
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memset(dev, 0, sizeof(et6000_t));
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/* Port 92h */
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device_add(&port_92_device);
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/* Defaults */
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dev->regs[3] = 1;
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/* Shadow Programming */
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et6000_shadow_control(0xf0000, 0x10000, 0, 1);
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io_sethandler(0x0022, 2, et6000_read, NULL, NULL, et6000_write, NULL, NULL, dev); /* Ports 22h-23h: ETEQ Cheetah ET6000 */
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return dev;
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}
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const device_t et6000_device = {
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"ETEQ Cheetah ET6000",
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0,
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0,
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et6000_init,
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et6000_close,
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NULL,
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{NULL},
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NULL,
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NULL,
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NULL};
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