193 lines
5.1 KiB
C
193 lines
5.1 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Chips & Technologies CS4031 chipset.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2021 Tiseno100
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/plat_unused.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct cs4031_t {
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uint8_t index;
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uint8_t regs[256];
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port_92_t *port_92;
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} cs4031_t;
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#ifdef ENABLE_CS4031_LOG
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int cs4031_do_log = ENABLE_CS4031_LOG;
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static void
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cs4031_log(const char *fmt, ...)
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{
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va_list ap;
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if (cs4031_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define cs4031_log(fmt, ...)
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#endif
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static void
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cs4031_shadow_recalc(cs4031_t *dev)
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{
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mem_set_mem_state_both(0xa0000, 0x10000, (dev->regs[0x18] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xb0000, 0x10000, (dev->regs[0x18] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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for (uint32_t i = 0; i < 7; i++) {
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if (i < 4)
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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else
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mem_set_mem_state_both(0xd0000 + ((i - 4) << 16), 0x10000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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}
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shadowbios = !!(dev->regs[0x19] & 0x40);
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shadowbios_write = !!(dev->regs[0x1a] & 0x40);
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}
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static void
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cs4031_write(uint16_t addr, uint8_t val, void *priv)
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{
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cs4031_t *dev = (cs4031_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
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switch (dev->index) {
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case 0x05:
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dev->regs[dev->index] = val & 0x3f;
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break;
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case 0x06:
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dev->regs[dev->index] = val & 0xbc;
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break;
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case 0x07:
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dev->regs[dev->index] = val & 0x0f;
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break;
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case 0x10:
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dev->regs[dev->index] = val & 0x3d;
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break;
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case 0x11:
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dev->regs[dev->index] = val & 0x8d;
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break;
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case 0x12:
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case 0x13:
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dev->regs[dev->index] = val & 0x8d;
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break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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dev->regs[dev->index] = val & 0x7f;
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break;
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case 0x18:
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dev->regs[dev->index] = val & 0xf3;
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cs4031_shadow_recalc(dev);
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break;
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case 0x19:
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case 0x1a:
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dev->regs[dev->index] = val & 0x7f;
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cs4031_shadow_recalc(dev);
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break;
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case 0x1b:
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dev->regs[dev->index] = val;
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break;
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case 0x1c:
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dev->regs[dev->index] = val & 0xb3;
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port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static uint8_t
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cs4031_read(uint16_t addr, void *priv)
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{
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const cs4031_t *dev = (cs4031_t *) priv;
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return (addr == 0x23) ? dev->regs[dev->index] : 0xff;
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}
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static void
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cs4031_close(void *priv)
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{
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cs4031_t *dev = (cs4031_t *) priv;
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free(dev);
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}
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static void *
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cs4031_init(UNUSED(const device_t *info))
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{
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cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
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memset(dev, 0, sizeof(cs4031_t));
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dev->port_92 = device_add(&port_92_device);
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dev->regs[0x05] = 0x05;
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dev->regs[0x1b] = 0x60;
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io_sethandler(0x0022, 0x0002, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
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return dev;
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}
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const device_t cs4031_device = {
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.name = "Chips & Technogies CS4031",
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.internal_name = "cs4031",
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.flags = 0,
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.local = 0,
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.init = cs4031_init,
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.close = cs4031_close,
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.reset = NULL,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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