472 lines
11 KiB
C
472 lines
11 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of the SFF-8038i IDE Bus Master.
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*
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* PRD format :
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* word 0 - base address
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* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
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*
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* Version: @(#)hdc_ide_sff8038i.c 1.0.1 2019/10/30
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2016-2019 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include "../86box.h"
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#include "../cdrom/cdrom.h"
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#include "../scsi/scsi_device.h"
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#include "../scsi/scsi_cdrom.h"
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#include "../dma.h"
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#include "../io.h"
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#include "../device.h"
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#include "../keyboard.h"
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#include "../mem.h"
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#include "../pci.h"
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#include "../pic.h"
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#include "hdc.h"
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#include "hdc_ide.h"
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#include "hdc_ide_sff8038i.h"
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#include "zip.h"
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static int next_id = 0;
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static uint8_t sff_bus_master_read(uint16_t port, void *priv);
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static uint16_t sff_bus_master_readw(uint16_t port, void *priv);
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static uint32_t sff_bus_master_readl(uint16_t port, void *priv);
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static void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
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static void sff_bus_master_writew(uint16_t port, uint16_t val, void *priv);
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static void sff_bus_master_writel(uint16_t port, uint32_t val, void *priv);
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#ifdef ENABLE_SFF_LOG
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int sff_do_log = ENABLE_SFF_LOG;
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static void
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sff_log(const char *fmt, ...)
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{
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va_list ap;
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if (sff_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define sff_log(fmt, ...)
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#endif
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void
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sff_bus_master_handlers(sff8038i_t *dev, uint16_t old_base, uint16_t new_base, int enabled)
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{
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io_removehandler(old_base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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if (enabled && new_base) {
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io_sethandler(new_base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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}
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dev->enabled = enabled;
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}
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static void
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sff_bus_master_next_addr(sff8038i_t *dev)
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{
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DMAPageRead(dev->ptr_cur, (uint8_t *)&(dev->addr), 4);
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DMAPageRead(dev->ptr_cur + 4, (uint8_t *)&(dev->count), 4);
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sff_log("SFF-8038i Bus master DWORDs: %08X %08X\n", dev->addr, dev->count);
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dev->eot = dev->count >> 31;
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dev->count &= 0xfffe;
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if (!dev->count)
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dev->count = 65536;
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dev->addr &= 0xfffffffe;
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dev->ptr_cur += 8;
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}
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static void
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sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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#ifdef ENABLE_SFF_LOG
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int channel = (port & 8) ? 1 : 0;
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#endif
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sff_log("SFF-8038i Bus master BYTE write: %04X %02X\n", port, val);
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switch (port & 7) {
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case 0:
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sff_log("sff Cmd : val = %02X, old = %02X\n", val, dev->command);
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if ((val & 1) && !(dev->command & 1)) { /*Start*/
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sff_log("sff Bus Master start on channel %i\n", channel);
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dev->ptr_cur = dev->ptr;
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sff_bus_master_next_addr(dev);
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dev->status |= 1;
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}
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if (!(val & 1) && (dev->command & 1)) { /*Stop*/
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sff_log("sff Bus Master stop on channel %i\n", channel);
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dev->status &= ~1;
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}
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dev->command = val;
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break;
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case 2:
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sff_log("sff Status: val = %02X, old = %02X\n", val, dev->status);
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dev->status &= 0x07;
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dev->status |= (val & 0x60);
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if (val & 0x04)
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dev->status &= ~0x04;
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if (val & 0x02)
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dev->status &= ~0x02;
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffffff00) | (val & 0xfc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val;
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break;
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case 5:
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dev->ptr = (dev->ptr & 0xffff00fc) | (val << 8);
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dev->ptr %= (mem_size * 1024);
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break;
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case 6:
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dev->ptr = (dev->ptr & 0xff00fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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case 7:
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dev->ptr = (dev->ptr & 0x00fffffc) | (val << 24);
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dev->ptr %= (mem_size * 1024);
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break;
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}
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}
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static void
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sff_bus_master_writew(uint16_t port, uint16_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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sff_log("SFF-8038i Bus master WORD write: %04X %04X\n", port, val);
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switch (port & 7) {
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case 0:
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case 2:
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sff_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (dev->ptr & 0xffff0000) | (val & 0xfffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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case 6:
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dev->ptr = (dev->ptr & 0x0000fffc) | (val << 16);
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dev->ptr %= (mem_size * 1024);
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break;
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}
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}
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static void
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sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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sff_log("SFF-8038i Bus master DWORD write: %04X %08X\n", port, val);
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switch (port & 7) {
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case 0:
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case 2:
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sff_bus_master_write(port, val & 0xff, priv);
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break;
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case 4:
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dev->ptr = (val & 0xfffffffc);
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dev->ptr %= (mem_size * 1024);
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dev->ptr0 = val & 0xff;
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break;
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}
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}
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static uint8_t
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sff_bus_master_read(uint16_t port, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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uint8_t ret = 0xff;
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switch (port & 7) {
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case 0:
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ret = dev->command;
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break;
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case 2:
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ret = dev->status & 0x67;
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break;
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case 4:
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ret = dev->ptr0;
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break;
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case 5:
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ret = dev->ptr >> 8;
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break;
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case 6:
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ret = dev->ptr >> 16;
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break;
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case 7:
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ret = dev->ptr >> 24;
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break;
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}
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sff_log("SFF-8038i Bus master BYTE read : %04X %02X\n", port, ret);
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return ret;
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}
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static uint16_t
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sff_bus_master_readw(uint16_t port, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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uint16_t ret = 0xffff;
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switch (port & 7) {
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case 0:
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case 2:
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ret = (uint16_t) sff_bus_master_read(port, priv);
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break;
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case 4:
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ret = dev->ptr0 | (dev->ptr & 0xff00);
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break;
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case 6:
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ret = dev->ptr >> 16;
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break;
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}
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sff_log("SFF-8038i Bus master WORD read : %04X %04X\n", port, ret);
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return ret;
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}
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static uint32_t
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sff_bus_master_readl(uint16_t port, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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uint32_t ret = 0xffffffff;
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switch (port & 7) {
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case 0:
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case 2:
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ret = (uint32_t) sff_bus_master_read(port, priv);
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break;
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case 4:
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ret = dev->ptr0 | (dev->ptr & 0xffffff00);
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break;
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}
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sff_log("sff Bus master DWORD read : %04X %08X\n", port, ret);
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return ret;
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}
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static int
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sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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#ifdef ENABLE_SFF_LOG
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char *sop;
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#endif
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int force_end = 0, buffer_pos = 0;
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#ifdef ENABLE_SFF_LOG
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sop = out ? "Read" : "Writ";
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#endif
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if (!(dev->status & 1))
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return 2; /*DMA disabled*/
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sff_log("SFF-8038i Bus master %s: %i bytes\n", out ? "write" : "read", transfer_length);
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while (1) {
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if (dev->count <= transfer_length) {
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sff_log("%sing %i bytes to %08X\n", sop, dev->count, dev->addr);
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if (out)
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DMAPageRead(dev->addr, (uint8_t *)(data + buffer_pos), dev->count);
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else
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DMAPageWrite(dev->addr, (uint8_t *)(data + buffer_pos), dev->count);
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transfer_length -= dev->count;
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buffer_pos += dev->count;
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} else {
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sff_log("%sing %i bytes to %08X\n", sop, transfer_length, dev->addr);
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if (out)
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DMAPageRead(dev->addr, (uint8_t *)(data + buffer_pos), transfer_length);
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else
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DMAPageWrite(dev->addr, (uint8_t *)(data + buffer_pos), transfer_length);
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/* Increase addr and decrease count so that resumed transfers do not mess up. */
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dev->addr += transfer_length;
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dev->count -= transfer_length;
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transfer_length = 0;
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force_end = 1;
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}
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if (force_end) {
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sff_log("Total transfer length smaller than sum of all blocks, partial block\n");
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dev->status &= ~2;
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return 1; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
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} else {
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if (!transfer_length && !dev->eot) {
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sff_log("Total transfer length smaller than sum of all blocks, full block\n");
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dev->status &= ~2;
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return 1; /* We have exhausted the data to transfer but there's more blocks left, break. */
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} else if (transfer_length && dev->eot) {
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sff_log("Total transfer length greater than sum of all blocks\n");
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dev->status |= 2;
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return 0; /* There is data left to transfer but we have reached EOT - return with error. */
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} else if (dev->eot) {
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sff_log("Regular EOT\n");
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dev->status &= ~3;
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return 1; /* We have regularly reached EOT - clear status and break. */
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} else {
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/* We have more to transfer and there are blocks left, get next block. */
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sff_bus_master_next_addr(dev);
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}
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}
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}
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return 1;
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}
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void
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sff_bus_master_set_irq(int channel, void *priv)
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{
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sff8038i_t *dev = (sff8038i_t *) priv;
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dev->status &= ~4;
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dev->status |= (channel >> 4);
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channel &= 0x01;
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if (dev->status & 0x04) {
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if (channel && pci_use_mirq(0))
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pci_set_mirq(0, 0);
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else
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picint(1 << (14 + channel));
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} else {
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if ((channel & 1) && pci_use_mirq(0))
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pci_clear_mirq(0, 0);
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else
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picintc(1 << (14 + channel));
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}
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}
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void
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sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base)
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{
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if (dev->enabled) {
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io_removehandler(old_base, 0x08,
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sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
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sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
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dev);
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dev->enabled = 0;
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}
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dev->command = 0x00;
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dev->status = 0x00;
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dev->ptr = dev->ptr_cur = 0x00000000;
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dev->addr = 0x00000000;
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dev->ptr0 = 0x00;
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dev->count = dev->eot = 0x00000000;
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ide_pri_disable();
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ide_sec_disable();
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}
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static void
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sff_reset(void *p)
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{
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int i = 0;
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for (i = 0; i < CDROM_NUM; i++) {
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if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
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(cdrom[i].ide_channel < 4) && cdrom[i].priv)
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scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
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}
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for (i = 0; i < ZIP_NUM; i++) {
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if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) &&
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(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
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zip_reset((scsi_common_t *) zip_drives[i].priv);
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}
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}
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static void
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sff_close(void *p)
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{
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sff8038i_t *dev = (sff8038i_t *)p;
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free(dev);
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next_id--;
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if (next_id < 0)
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next_id = 0;
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}
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static void
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*sff_init(const device_t *info)
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{
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sff8038i_t *dev = (sff8038i_t *) malloc(sizeof(sff8038i_t));
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memset(dev, 0, sizeof(sff8038i_t));
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/* Make sure to only add IDE once. */
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if (next_id == 0)
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device_add(&ide_pci_2ch_device);
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ide_set_bus_master(next_id, sff_bus_master_dma, sff_bus_master_set_irq, dev);
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next_id++;
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return dev;
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}
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const device_t sff8038i_device =
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{
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"SFF-8038i IDE Bus Master",
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DEVICE_PCI,
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0,
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sff_init,
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sff_close,
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sff_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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