511 lines
12 KiB
C
511 lines
12 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the SMC FDC37C932FR Super I/O Chip.
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*
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* Version: @(#)fdc37c932fr.c 1.0.0 2017/05/30
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*
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* Author: Miran Grca, <mgrca8@gmail.com>
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* Copyright 2016-2017 Miran Grca.
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*/
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#include "ibm.h"
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#include "disc.h"
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#include "fdc.h"
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#include "fdd.h"
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#include "ide.h"
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#include "io.h"
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#include "lpt.h"
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#include "serial.h"
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#include "fdc37c932fr.h"
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static int fdc37c932fr_locked;
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static int fdc37c932fr_curreg = 0;
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static int fdc37c932fr_gpio_curreg = 0;
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static uint8_t fdc37c932fr_regs[48];
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static uint8_t fdc37c932fr_ld_regs[10][256];
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static uint8_t fdc37c932fr_gpio_regs[16] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
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static uint8_t tries;
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static uint16_t ld0_valid_ports[2] = {0x3F0, 0x370};
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static uint16_t ld1_valid_ports[2] = {0x1F0, 0x170};
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static uint16_t ld1_valid_ports2[2] = {0x3F6, 0x376};
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static uint16_t ld2_valid_ports[2] = {0x170, 0x1F0};
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static uint16_t ld2_valid_ports2[2] = {0x376, 0x3F6};
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static uint16_t ld3_valid_ports[3] = {0x3BC, 0x378, 0x278};
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static uint16_t ld4_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
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static uint16_t ld5_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
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static uint16_t ld5_valid_ports2[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
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static uint8_t is_in_array(uint16_t *port_array, uint8_t max, uint16_t port)
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{
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uint8_t i = 0;
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for (i = 0; i < max; i++)
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{
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if (port_array[i] == port) return 1;
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}
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return 0;
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}
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static uint16_t make_port(uint8_t ld)
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{
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uint16_t r0 = fdc37c932fr_ld_regs[ld][0x60];
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uint16_t r1 = fdc37c932fr_ld_regs[ld][0x61];
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uint16_t p = (r0 << 8) + r1;
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switch(ld)
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{
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case 0:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x3F0;
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if (!(is_in_array(ld0_valid_ports, 2, p))) p = 0x3F0;
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break;
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case 1:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x1F0;
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if (!(is_in_array(ld1_valid_ports, 2, p))) p = 0x1F0;
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break;
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case 2:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x170;
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if (!(is_in_array(ld2_valid_ports, 2, p))) p = 0x170;
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break;
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case 3:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x378;
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if (!(is_in_array(ld3_valid_ports, 3, p))) p = 0x378;
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break;
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case 4:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x3F8;
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if (!(is_in_array(ld4_valid_ports, 9, p))) p = 0x3F8;
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break;
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case 5:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x2F8;
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if (!(is_in_array(ld5_valid_ports, 9, p))) p = 0x2F8;
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break;
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}
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fdc37c932fr_ld_regs[ld][0x60] = (p >> 8);
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fdc37c932fr_ld_regs[ld][0x61] = (p & 0xFF);
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return p;
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}
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uint16_t make_port2(uint8_t ld)
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{
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uint16_t r0 = fdc37c932fr_ld_regs[ld][0x62];
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uint16_t r1 = fdc37c932fr_ld_regs[ld][0x63];
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uint16_t p = (r0 << 8) + r1;
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switch(ld)
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{
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case 1:
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p &= 0xFFF;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x3F6;
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if (!(is_in_array(ld1_valid_ports2, 2, p))) p = 0x3F6;
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break;
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case 2:
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p &= 0xFFF;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x376;
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if (!(is_in_array(ld2_valid_ports2, 2, p))) p = 0x376;
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break;
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case 5:
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0xFF8)) p = 0x3E8;
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if (!(is_in_array(ld5_valid_ports2, 9, p))) p = 0x3E8;
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break;
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}
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fdc37c932fr_ld_regs[ld][0x62] = (p >> 8);
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fdc37c932fr_ld_regs[ld][0x63] = (p & 0xFF);
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return p;
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}
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void fdc37c932fr_gpio_write(uint16_t port, uint8_t val, void *priv)
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{
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if (port & 1)
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{
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if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
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fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg] = val;
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}
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else
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{
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fdc37c932fr_gpio_curreg = val;
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}
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}
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void fdc37c932fr_write(uint16_t port, uint8_t val, void *priv)
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{
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t valxor = 0;
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uint16_t ld_port = 0;
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if (index)
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{
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if ((val == 0x55) && !fdc37c932fr_locked)
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{
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if (tries)
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{
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fdc37c932fr_locked = 1;
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fdc_3f1_enable(0);
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tries = 0;
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}
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else
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{
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tries++;
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}
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}
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else
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{
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if (fdc37c932fr_locked)
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{
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if (val == 0xaa)
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{
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fdc37c932fr_locked = 0;
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fdc_3f1_enable(1);
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return;
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}
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fdc37c932fr_curreg = val;
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}
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else
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{
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if (tries)
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tries = 0;
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}
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}
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}
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else
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{
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if (fdc37c932fr_locked)
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{
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if (fdc37c932fr_curreg < 48)
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{
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valxor = val ^ fdc37c932fr_regs[fdc37c932fr_curreg];
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fdc37c932fr_regs[fdc37c932fr_curreg] = val;
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}
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else
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{
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valxor = val ^ fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
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if (((fdc37c932fr_curreg & 0xF0) == 0x70) && (fdc37c932fr_regs[7] < 4)) return;
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/* Block writes to IDE configuration. */
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if (fdc37c932fr_regs[7] == 1) return;
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if (fdc37c932fr_regs[7] == 2) return;
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if (fdc37c932fr_regs[7] > 5) return;
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fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg] = val;
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goto process_value;
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}
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}
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}
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return;
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process_value:
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switch(fdc37c932fr_regs[7])
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{
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case 0:
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/* FDD */
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switch(fdc37c932fr_curreg)
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{
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case 0x30:
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/* Activate */
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if (valxor)
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{
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if (!val)
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fdc_remove();
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else
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{
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fdc_add();
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}
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}
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break;
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case 0x60:
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case 0x61:
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if (valxor && fdc37c932fr_ld_regs[0][0x30])
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{
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fdc_remove();
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ld_port = make_port(0);
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fdc37c932fr_ld_regs[0][0x60] = make_port(0) >> 8;
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fdc37c932fr_ld_regs[0][0x61] = make_port(0) & 0xFF;
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fdc_add();
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}
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break;
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case 0xF0:
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if (valxor & 0x01) fdc_update_enh_mode(val & 0x01);
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if (valxor & 0x10) fdd_swap = ((val & 0x10) >> 4);
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break;
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case 0xF1:
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if (valxor & 0xC) fdc_update_densel_force((val & 0xC) >> 2);
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break;
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case 0xF2:
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if (valxor & 0xC0) fdc_update_rwc(3, (valxor & 0xC0) >> 6);
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if (valxor & 0x30) fdc_update_rwc(2, (valxor & 0x30) >> 4);
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if (valxor & 0x0C) fdc_update_rwc(1, (valxor & 0x0C) >> 2);
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if (valxor & 0x03) fdc_update_rwc(0, (valxor & 0x03));
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break;
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case 0xF4:
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if (valxor & 0x18) fdc_update_drvrate(0, (val & 0x18) >> 3);
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break;
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case 0xF5:
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if (valxor & 0x18) fdc_update_drvrate(1, (val & 0x18) >> 3);
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break;
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case 0xF6:
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if (valxor & 0x18) fdc_update_drvrate(2, (val & 0x18) >> 3);
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break;
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case 0xF7:
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if (valxor & 0x18) fdc_update_drvrate(3, (val & 0x18) >> 3);
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break;
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}
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break;
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case 3:
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/* Parallel port */
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switch(fdc37c932fr_curreg)
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{
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case 0x30:
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/* Activate */
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if (valxor)
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{
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if (!val)
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lpt1_remove();
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else
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{
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ld_port = make_port(3);
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lpt1_init(ld_port);
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}
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}
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break;
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case 0x60:
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case 0x61:
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if (valxor && fdc37c932fr_ld_regs[3][0x30])
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{
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lpt1_remove();
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ld_port = make_port(3);
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lpt1_init(ld_port);
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}
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break;
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}
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break;
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case 4:
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/* Serial port 1 */
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switch(fdc37c932fr_curreg)
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{
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case 0x30:
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/* Activate */
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if (valxor)
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{
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if (!val)
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serial_remove(1);
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else
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{
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ld_port = make_port(4);
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serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
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}
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}
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break;
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor && fdc37c932fr_ld_regs[4][0x30])
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{
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ld_port = make_port(4);
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serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
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}
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break;
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}
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break;
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case 5:
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/* Serial port 2 */
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switch(fdc37c932fr_curreg)
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{
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case 0x30:
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/* Activate */
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if (valxor)
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{
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if (!val)
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serial_remove(2);
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else
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{
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ld_port = make_port(5);
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serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
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}
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}
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break;
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case 0x60:
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case 0x61:
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case 0x70:
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if (valxor && fdc37c932fr_ld_regs[5][0x30])
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{
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ld_port = make_port(5);
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serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
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}
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break;
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}
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break;
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}
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}
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uint8_t fdc37c932fr_gpio_read(uint16_t port, void *priv)
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{
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if (port & 1)
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{
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if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
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return fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg];
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else
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return 0xff;
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}
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else
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{
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return fdc37c932fr_gpio_curreg;
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}
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}
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uint8_t fdc37c932fr_read(uint16_t port, void *priv)
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{
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uint8_t index = (port & 1) ? 0 : 1;
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if (!fdc37c932fr_locked)
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{
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return 0xff;
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}
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if (index)
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return fdc37c932fr_curreg;
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else
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{
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if (fdc37c932fr_curreg < 0x30)
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{
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return fdc37c932fr_regs[fdc37c932fr_curreg];
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}
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else
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{
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if ((fdc37c932fr_regs[7] == 0) && (fdc37c932fr_curreg == 0xF2)) return (fdc_get_rwc(0) | (fdc_get_rwc(1) << 2));
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return fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
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}
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}
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}
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void fdc37c932fr_reset(void)
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{
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int i = 0;
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fdc37c932fr_regs[3] = 3;
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fdc37c932fr_regs[0x20] = 3;
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fdc37c932fr_regs[0x21] = 1;
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fdc37c932fr_regs[0x24] = 4;
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fdc37c932fr_regs[0x26] = 0xF0;
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fdc37c932fr_regs[0x27] = 3;
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for (i = 0; i < 10; i++)
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{
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memset(fdc37c932fr_ld_regs[i], 0, 256);
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}
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/* Logical device 0: FDD */
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fdc37c932fr_ld_regs[0][0x30] = 1;
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fdc37c932fr_ld_regs[0][0x60] = 3;
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fdc37c932fr_ld_regs[0][0x61] = 0xF0;
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fdc37c932fr_ld_regs[0][0x70] = 6;
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fdc37c932fr_ld_regs[0][0x74] = 2;
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fdc37c932fr_ld_regs[0][0xF0] = 0xE;
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fdc37c932fr_ld_regs[0][0xF2] = 0xFF;
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/* Logical device 1: IDE1 */
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fdc37c932fr_ld_regs[1][0x30] = 1;
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fdc37c932fr_ld_regs[1][0x60] = 1;
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fdc37c932fr_ld_regs[1][0x61] = 0xF0;
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fdc37c932fr_ld_regs[1][0x62] = 3;
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fdc37c932fr_ld_regs[1][0x63] = 0xF6;
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fdc37c932fr_ld_regs[1][0x70] = 0xE;
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fdc37c932fr_ld_regs[1][0xF0] = 0xC;
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/* Logical device 2: IDE2 */
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fdc37c932fr_ld_regs[2][0x30] = 1;
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fdc37c932fr_ld_regs[2][0x60] = 1;
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fdc37c932fr_ld_regs[2][0x61] = 0x70;
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fdc37c932fr_ld_regs[2][0x62] = 3;
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fdc37c932fr_ld_regs[2][0x63] = 0x76;
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fdc37c932fr_ld_regs[2][0x70] = 0xF;
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/* Logical device 3: Parallel Port */
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fdc37c932fr_ld_regs[3][0x30] = 1;
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fdc37c932fr_ld_regs[3][0x60] = 3;
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fdc37c932fr_ld_regs[3][0x61] = 0x78;
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fdc37c932fr_ld_regs[3][0x70] = 7;
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fdc37c932fr_ld_regs[3][0x74] = 4;
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fdc37c932fr_ld_regs[3][0xF0] = 0x3C;
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/* Logical device 4: Serial Port 1 */
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fdc37c932fr_ld_regs[4][0x30] = 1;
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fdc37c932fr_ld_regs[4][0x60] = 3;
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fdc37c932fr_ld_regs[4][0x61] = 0xf8;
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fdc37c932fr_ld_regs[4][0x70] = 4;
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fdc37c932fr_ld_regs[4][0xF0] = 3;
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serial_setup(1, 0x3f8, fdc37c932fr_ld_regs[4][0x70]);
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/* Logical device 5: Serial Port 2 */
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fdc37c932fr_ld_regs[5][0x30] = 1;
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fdc37c932fr_ld_regs[5][0x60] = 2;
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fdc37c932fr_ld_regs[5][0x61] = 0xf8;
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fdc37c932fr_ld_regs[5][0x70] = 3;
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fdc37c932fr_ld_regs[5][0x74] = 4;
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fdc37c932fr_ld_regs[5][0xF1] = 2;
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fdc37c932fr_ld_regs[5][0xF2] = 3;
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serial_setup(2, 0x2f8, fdc37c932fr_ld_regs[5][0x70]);
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|
|
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/* Logical device 6: RTC */
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fdc37c932fr_ld_regs[6][0x63] = 0x70;
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fdc37c932fr_ld_regs[6][0xF4] = 3;
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|
|
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/* Logical device 7: Keyboard */
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fdc37c932fr_ld_regs[7][0x30] = 1;
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fdc37c932fr_ld_regs[7][0x61] = 0x60;
|
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fdc37c932fr_ld_regs[7][0x70] = 1;
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|
|
|
/* Logical device 8: AUX I/O */
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|
|
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/* Logical device 9: ACCESS.bus */
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|
|
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fdc_update_densel_force(0);
|
|
fdd_swap = 0;
|
|
fdc_update_rwc(0, 0);
|
|
fdc_update_rwc(1, 0);
|
|
fdc_update_rwc(2, 0);
|
|
fdc_update_rwc(3, 0);
|
|
fdc_update_drvrate(0, 0);
|
|
fdc_update_drvrate(1, 0);
|
|
fdc_update_drvrate(2, 0);
|
|
fdc_update_drvrate(3, 0);
|
|
fdc_update_max_track(79);
|
|
|
|
memset(fdc37c932fr_gpio_regs, 0, sizeof(fdc37c932fr_gpio_regs));
|
|
fdc37c932fr_gpio_regs[2] = 0xfd;
|
|
|
|
fdc37c932fr_locked = 0;
|
|
}
|
|
|
|
void fdc37c932fr_init()
|
|
{
|
|
lpt2_remove();
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|
|
|
fdc37c932fr_reset();
|
|
|
|
io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
|
io_sethandler(0xe2, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
|
io_sethandler(0xe4, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
|
io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
|
|
io_sethandler(0x3f0, 0x0002, fdc37c932fr_read, NULL, NULL, fdc37c932fr_write, NULL, NULL, NULL);
|
|
|
|
pci_reset_handler.super_io_reset = fdc37c932fr_reset;
|
|
}
|