0faf6692c9
Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
172 lines
3.7 KiB
C
172 lines
3.7 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C283 chipset.
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*
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*
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*
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* Authors: Tiseno100
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*
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* Copyright 2020 Tiseno100
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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typedef struct
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{
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uint8_t index,
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regs[256];
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} opti283_t;
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static void opti283_shadow_recalc(opti283_t *dev)
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{
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uint32_t base, i;
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uint32_t shflagsc, shflagsd, shflagse, shflagsf;
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shadowbios = !(dev->regs[0x11] & 0x80);
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shadowbios_write = (dev->regs[0x11] & 0x80);
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if(dev->regs[0x11] & 0x10){
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shflagsc = MEM_READ_INTERNAL;
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shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagsc = disabled_shadow;
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if(dev->regs[0x11] & 0x20){
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shflagsd = MEM_READ_INTERNAL;
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shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagsd = disabled_shadow;
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if(dev->regs[0x11] & 0x40){
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shflagse = MEM_READ_INTERNAL;
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shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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} else shflagse = disabled_shadow;
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if(!(dev->regs[0x11] & 0x80)){
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shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
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} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
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mem_set_mem_state_both(0xf0000, 0x10000, shflagsf);
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for(i = 4; i < 8; i++){
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base = 0xc0000 + ((i-4) << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow);
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}
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for(i = 0; i < 4; i++){
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base = 0xd0000 + (i << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow);
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}
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for(i = 4; i < 8; i++){
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base = 0xe0000 + ((i-4) << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow);
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}
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}
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static void
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opti283_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti283_t *dev = (opti283_t *) priv;
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x24:
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/* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */
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dev->regs[dev->index] = val;
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switch(dev->index){
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case 0x10:
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cpu_update_waitstates();
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break;
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case 0x11:
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case 0x12:
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case 0x13:
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opti283_shadow_recalc(dev);
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break;
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}
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break;
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}
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}
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static uint8_t
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opti283_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti283_t *dev = (opti283_t *) priv;
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switch (addr) {
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case 0x24:
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ret = dev->regs[dev->index];
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break;
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}
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return ret;
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}
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static void
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opti283_close(void *priv)
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{
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opti283_t *dev = (opti283_t *) priv;
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free(dev);
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}
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static void *
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opti283_init(const device_t *info)
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{
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opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
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memset(dev, 0, sizeof(opti283_t));
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io_sethandler(0x022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
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io_sethandler(0x024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
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dev->regs[0x10] = 0x3f;
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dev->regs[0x11] = 0xf0;
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opti283_shadow_recalc(dev);
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return dev;
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}
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const device_t opti283_device = {
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"OPTi 82C283",
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0,
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0,
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opti283_init, opti283_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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