2018-02-20 21:44:51 -05:00
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/*
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2018-03-08 15:58:46 -05:00
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* VARCem Virtual ARchaeological Computer EMulator.
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2018-02-20 21:44:51 -05:00
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* An emulator of (mostly) x86-based PC systems and devices,
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* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
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* spanning the era between 1981 and 1995.
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*
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* This file is part of the VARCem Project.
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*
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* Implementation of 8250-style serial port.
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*
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* Version: @(#)serial.c 1.0.1 2018/02/14
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*
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* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
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* Miran Grca, <mgrca8@gmail.com>
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* Sarah Walker, <tommowalker@tommowalker.co.uk>
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*
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* Copyright 2017,2018 Fred N. van Kempen.
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* Copyright 2016-2018 Miran Grca.
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* Copyright 2008-2018 Sarah Walker.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the:
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*
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* Free Software Foundation, Inc.
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* 59 Temple Place - Suite 330
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* Boston, MA 02111-1307
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* USA.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include "emu.h"
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#include "machine/machine.h"
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#include "io.h"
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#include "pic.h"
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#include "mem.h"
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#include "rom.h"
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#include "serial.h"
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#include "timer.h"
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#include "mouse.h"
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enum {
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SERIAL_INT_LSR = 1,
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SERIAL_INT_RECEIVE = 2,
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SERIAL_INT_TRANSMIT = 4,
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SERIAL_INT_MSR = 8
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};
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SERIAL serial1, serial2;
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int serial_do_log = 0;
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void
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serial_reset(void)
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{
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serial1.iir = serial1.ier = serial1.lcr = 0;
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serial2.iir = serial2.ier = serial2.lcr = 0;
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serial1.fifo_read = serial1.fifo_write = 0;
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serial2.fifo_read = serial2.fifo_write = 0;
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}
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void
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serial_update_ints(SERIAL *serial)
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{
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int stat = 0;
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serial->iir = 1;
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if ((serial->ier & 4) && (serial->int_status & SERIAL_INT_LSR)) /*Line status interrupt*/ {
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stat = 1;
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serial->iir = 6;
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} else if ((serial->ier & 1) && (serial->int_status & SERIAL_INT_RECEIVE)) /*Recieved data available*/ {
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stat = 1;
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serial->iir = 4;
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} else if ((serial->ier & 2) && (serial->int_status & SERIAL_INT_TRANSMIT)) /*Transmit data empty*/ {
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stat = 1;
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serial->iir = 2;
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} else if ((serial->ier & 8) && (serial->int_status & SERIAL_INT_MSR)) /*Modem status interrupt*/ {
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stat = 1;
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serial->iir = 0;
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}
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if (stat && ((serial->mctrl & 8) || PCJR))
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picintlevel(1 << serial->irq);
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else
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picintc(1 << serial->irq);
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}
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void
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serial_clear_fifo(SERIAL *serial)
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{
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memset(serial->fifo, 0, 256);
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serial->fifo_read = serial->fifo_write = 0;
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}
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void
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serial_write_fifo(SERIAL *serial, uint8_t dat)
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{
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serial->fifo[serial->fifo_write] = dat;
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serial->fifo_write = (serial->fifo_write + 1) & 0xFF;
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if (!(serial->lsr & 1)) {
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serial->lsr |= 1;
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serial->int_status |= SERIAL_INT_RECEIVE;
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serial_update_ints(serial);
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}
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}
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uint8_t
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serial_read_fifo(SERIAL *serial)
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{
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if (serial->fifo_read != serial->fifo_write) {
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serial->dat = serial->fifo[serial->fifo_read];
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serial->fifo_read = (serial->fifo_read + 1) & 0xFF;
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}
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return serial->dat;
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}
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void
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serial_write(uint16_t addr, uint8_t val, void *p)
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{
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SERIAL *serial = (SERIAL *)p;
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switch (addr&7) {
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case 0:
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if (serial->lcr & 0x80) {
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serial->dlab1 = val;
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return;
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}
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serial->thr = val;
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serial->lsr |= 0x20;
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serial->int_status |= SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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if (serial->mctrl & 0x10) {
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serial_write_fifo(serial, val);
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}
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break;
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case 1:
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if (serial->lcr & 0x80) {
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serial->dlab2 = val;
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return;
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}
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serial->ier = val & 0xf;
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serial_update_ints(serial);
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break;
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case 2:
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serial->fcr = val;
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break;
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case 3:
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serial->lcr = val;
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break;
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case 4:
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if ((val & 2) && !(serial->mctrl & 2)) {
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if (serial->rcr_callback)
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serial->rcr_callback((struct SERIAL *)serial, serial->rcr_callback_p);
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}
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serial->mctrl = val;
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if (val & 0x10) {
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uint8_t new_msr;
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new_msr = (val & 0x0c) << 4;
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new_msr |= (val & 0x02) ? 0x10: 0;
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new_msr |= (val & 0x01) ? 0x20: 0;
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if ((serial->msr ^ new_msr) & 0x10)
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new_msr |= 0x01;
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if ((serial->msr ^ new_msr) & 0x20)
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new_msr |= 0x02;
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if ((serial->msr ^ new_msr) & 0x80)
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new_msr |= 0x08;
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if ((serial->msr & 0x40) && !(new_msr & 0x40))
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new_msr |= 0x04;
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serial->msr = new_msr;
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}
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break;
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case 5:
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serial->lsr = val;
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if (serial->lsr & 0x01)
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serial->int_status |= SERIAL_INT_RECEIVE;
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if (serial->lsr & 0x1e)
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serial->int_status |= SERIAL_INT_LSR;
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if (serial->lsr & 0x20)
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serial->int_status |= SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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break;
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case 6:
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serial->msr = val;
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if (serial->msr & 0x0f)
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serial->int_status |= SERIAL_INT_MSR;
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serial_update_ints(serial);
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break;
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case 7:
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serial->scratch = val;
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break;
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}
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}
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uint8_t
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serial_read(uint16_t addr, void *p)
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{
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SERIAL *serial = (SERIAL *)p;
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uint8_t temp = 0;
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switch (addr&7) {
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case 0:
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if (serial->lcr & 0x80) {
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temp = serial->dlab1;
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break;
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}
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serial->lsr &= ~1;
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serial->int_status &= ~SERIAL_INT_RECEIVE;
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serial_update_ints(serial);
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temp = serial_read_fifo(serial);
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if (serial->fifo_read != serial->fifo_write) {
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serial->recieve_delay = 1000LL * TIMER_USEC;
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}
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break;
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case 1:
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if (serial->lcr & 0x80)
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temp = serial->dlab2;
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else
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temp = serial->ier;
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break;
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case 2:
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temp = serial->iir;
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if ((temp & 0xe) == 2) {
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serial->int_status &= ~SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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}
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if (serial->fcr & 1)
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temp |= 0xc0;
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break;
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case 3:
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temp = serial->lcr;
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break;
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case 4:
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temp = serial->mctrl;
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break;
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case 5:
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if (serial->lsr & 0x20)
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serial->lsr |= 0x40;
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serial->lsr |= 0x20;
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temp = serial->lsr;
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if (serial->lsr & 0x1f)
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serial->lsr &= ~0x1e;
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serial->int_status &= ~SERIAL_INT_LSR;
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serial_update_ints(serial);
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break;
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case 6:
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temp = serial->msr;
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serial->msr &= ~0x0f;
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serial->int_status &= ~SERIAL_INT_MSR;
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serial_update_ints(serial);
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break;
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case 7:
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temp = serial->scratch;
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break;
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}
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return temp;
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}
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void
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serial_recieve_callback(void *p)
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{
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SERIAL *serial = (SERIAL *)p;
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serial->recieve_delay = 0;
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if (serial->fifo_read != serial->fifo_write) {
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serial->lsr |= 1;
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serial->int_status |= SERIAL_INT_RECEIVE;
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serial_update_ints(serial);
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}
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}
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uint16_t base_address[2] = { 0x0000, 0x0000 };
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void
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serial_remove(int port)
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{
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if ((port < 1) || (port > 2)) {
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fatal("serial_remove(): Invalid serial port: %i\n", port);
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exit(-1);
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}
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if (! serial_enabled[port - 1]) return;
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if (! base_address[port - 1]) return;
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/* pclog("Removing serial port %i at %04X...\n", port, base_address[port - 1]); */
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switch(port) {
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case 1:
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io_removehandler(base_address[0], 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
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base_address[0] = 0x0000;
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break;
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case 2:
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io_removehandler(base_address[1], 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
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base_address[1] = 0x0000;
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break;
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}
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}
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void
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serial_setup(int port, uint16_t addr, int irq)
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{
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/* pclog("Adding serial port %i at %04X...\n", port, addr); */
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switch(port) {
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case 1:
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if (!serial_enabled[0]) return;
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if (base_address[0] != 0x0000)
|
|
|
|
|
serial_remove(port);
|
|
|
|
|
if (addr != 0x0000) {
|
|
|
|
|
base_address[0] = addr;
|
|
|
|
|
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
|
|
|
|
|
}
|
|
|
|
|
serial1.irq = irq;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 2:
|
|
|
|
|
if (! serial_enabled[1]) return;
|
|
|
|
|
|
|
|
|
|
if (base_address[1] != 0x0000)
|
|
|
|
|
serial_remove(port);
|
|
|
|
|
if (addr != 0x0000) {
|
|
|
|
|
base_address[1] = addr;
|
|
|
|
|
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
|
|
|
|
|
}
|
|
|
|
|
serial2.irq = irq;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
fatal("serial_setup(): Invalid serial port: %i\n", port);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
serial_init(void)
|
|
|
|
|
{
|
|
|
|
|
base_address[0] = 0x03f8;
|
|
|
|
|
base_address[1] = 0x02f8;
|
|
|
|
|
|
|
|
|
|
if (serial_enabled[0]) {
|
|
|
|
|
/* pclog("Adding serial port 1...\n"); */
|
|
|
|
|
memset(&serial1, 0, sizeof(serial1));
|
|
|
|
|
io_sethandler(0x3f8, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
|
|
|
|
|
serial1.irq = 4;
|
|
|
|
|
serial1.rcr_callback = NULL;
|
|
|
|
|
timer_add(serial_recieve_callback, &serial1.recieve_delay, &serial1.recieve_delay, &serial1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (serial_enabled[1]) {
|
|
|
|
|
/* pclog("Adding serial port 2...\n"); */
|
|
|
|
|
memset(&serial2, 0, sizeof(serial2));
|
|
|
|
|
io_sethandler(0x2f8, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
|
|
|
|
|
serial2.irq = 3;
|
|
|
|
|
serial2.rcr_callback = NULL;
|
|
|
|
|
timer_add(serial_recieve_callback, &serial2.recieve_delay, &serial2.recieve_delay, &serial2);
|
|
|
|
|
}
|
|
|
|
|
}
|