diff --git a/src/cpu/386.c b/src/cpu/386.c index 6e6b2b0..cd31ad1 100644 --- a/src/cpu/386.c +++ b/src/cpu/386.c @@ -8,7 +8,7 @@ * * Implementation of 80286+ CPU interpreter. * - * Version: @(#)386.c 1.0.8 2019/04/20 + * Version: @(#)386.c 1.0.9 2019/04/21 * * Authors: Fred N. van Kempen, * Sarah Walker, @@ -82,7 +82,6 @@ int timetolive = 0; /* Also in 386_dynarec.c: */ cpu_state_t cpu_state; int inscounts[256]; -//uint32_t oldcs2, oldpc2; uint32_t oxpc; int trap; int inttype; @@ -150,9 +149,9 @@ uint32_t rmdat32; void exec386(int cycs) { - int64_t cycdiff; uint32_t addr; uint8_t temp; + int cycdiff; int oldcyc; int tempi; diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index 563a820..8f4f202 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -8,7 +8,7 @@ * * Implementation of the CPU's dynamic recompiler. * - * Version: @(#)386_dynarec.c 1.0.8 2019/04/20 + * Version: @(#)386_dynarec.c 1.0.9 2019/04/21 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -87,7 +87,6 @@ int cpu_recomp_blocks_latched, cpu_recomp_ins_latched, int inrecomp = 0; int cpu_block_end = 0; -//int nmi_enable = 1; 808x.c int cpl_override=0; int fpucount=0; @@ -95,8 +94,6 @@ int oddeven=0; uint32_t rmdat32; -//static uint32_t backupregs[16]; -//static uint32_t oldecx; static INLINE void fetch_ea_32_long(uint32_t rmdat) diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 61f3da6..0880849 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -8,7 +8,7 @@ * * CPU type handler. * - * Version: @(#)cpu.c 1.0.11 2019/04/11 + * Version: @(#)cpu.c 1.0.12 2019/04/21 * * Authors: Fred N. van Kempen, * Sarah Walker, @@ -116,17 +116,16 @@ const OpFn *x86_dynarec_opcodes_REPNE; int cpu_busspeed; int cpu_16bitbus; +int isa_cycles; int cpu_cyrix_alignment; int CPUID; uint64_t cpu_CR4_mask; -int isa_cycles; int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; int cpu_waitstates; int cpu_cache_int_enabled, cpu_cache_ext_enabled; -int cpu_pci_speed; int is186, /* 80186 */ is286, /* 80286 */ @@ -146,9 +145,6 @@ int cpu_hasrdtsc, uint64_t tsc = 0; msr_t msr; cr0_t CR0; -uint64_t pmc[2] = {0, 0}; - -uint16_t temp_seg_data[4] = {0, 0, 0, 0}; /* Variables for the 686+ processors. */ uint16_t cs_msr = 0; @@ -178,9 +174,7 @@ uint64_t ecx570_msr = 0; #if defined(DEV_BRANCH) && defined(USE_AMD_K) /* Variables for the AMD "K" processors. */ -uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */ uint64_t star = 0; /* These are K6-only. */ -uint64_t sfmask = 0; #endif int timing_rr; @@ -204,6 +198,13 @@ static const CPU *cpu_list, static int cpu_turbo = -1, cpu_effective = -1; +#if defined(DEV_BRANCH) && defined(USE_AMD_K) +/* Variables for the AMD "K" processors. */ +static uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */ +static uint64_t sfmask = 0; +#endif + +/* Variables for the Cyrix processors. */ static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6; static int cyrix_addr; diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index 0198369..0df5c5e 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -8,7 +8,7 @@ * * Definitions for the CPU module. * - * Version: @(#)cpu.h 1.0.10 2019/04/20 + * Version: @(#)cpu.h 1.0.11 2019/04/21 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -348,10 +348,8 @@ extern uint32_t cpu_cur_status; extern uint64_t cpu_CR4_mask; extern uint64_t tsc; extern msr_t msr; -extern int cycles_lost; extern uint8_t opcode; extern int fpucount; -extern float mips,flops; extern int cgate16; extern int cpl_override; extern int CPUID; @@ -360,14 +358,8 @@ extern int isa_cycles; extern uint16_t flags,eflags; extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; extern int ins; // FIXME: get rid of this! -extern int cycdiff; -extern uint32_t pccache; -extern uint8_t *pccache2; -extern float isa_timing, - bus_timing; -extern uint64_t pmc[2]; -extern uint16_t temp_seg_data[4]; +extern float bus_timing; extern uint16_t cs_msr; extern uint32_t esp_msr; extern uint32_t eip_msr; @@ -414,7 +406,6 @@ extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; extern int cpu_waitstates; -extern int cpu_pci_speed; extern int timing_rr; extern int timing_mr, timing_mrl; diff --git a/src/devices/video/vid_svga.c b/src/devices/video/vid_svga.c index bdc1498..df444e2 100644 --- a/src/devices/video/vid_svga.c +++ b/src/devices/video/vid_svga.c @@ -11,10 +11,11 @@ * This is intended to be used by another SVGA driver, * and not as a card in it's own right. * - * Version: @(#)vid_svga.c 1.0.17 2019/04/11 + * Version: @(#)vid_svga.c 1.0.18 2019/04/22 * * Authors: Fred N. van Kempen, * Miran Grca, + * TheCollector1995, * Sarah Walker, * * Copyright 2017-2019 Fred N. van Kempen. @@ -1282,10 +1283,10 @@ svga_writel_common(uint32_t addr, uint32_t val, uint8_t linear, void *p) svga_t *svga = (svga_t *)p; if (!svga->fast) { - svga_write(addr, val, p); - svga_write(addr + 1, val >> 8, p); - svga_write(addr + 2, val >> 16, p); - svga_write(addr + 3, val >> 24, p); + svga_write_common(addr, val, linear, p); + svga_write_common(addr + 1, val >> 8, linear, p); + svga_write_common(addr + 2, val >> 16, linear, p); + svga_write_common(addr + 3, val >> 24, linear, p); return; } diff --git a/src/mem.h b/src/mem.h index cf45d7b..8ef6eb1 100644 --- a/src/mem.h +++ b/src/mem.h @@ -8,7 +8,7 @@ * * Definitions for the memory interface. * - * Version: @(#)mem.h 1.0.14 2019/03/29 + * Version: @(#)mem.h 1.0.15 2019/04/21 * * Authors: Fred N. van Kempen, * Sarah Walker, @@ -125,6 +125,9 @@ extern page_t *pages, extern uint32_t get_phys_virt,get_phys_phys; +extern uint32_t pccache; +extern uint8_t *pccache2; + extern int memspeed[11]; extern int mmu_perm;