claunia/VARCem
Archived
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Small fixes here and there.

Browse Source 
Applied upstream commits where needed.
Renamed some of the CirrusLogic bioses.
This commit is contained in:
waltje
2018-03-22 20:20:30 -05:00
parent 85d291205f
commit 6898e2776c
6 changed files with 428 additions and 542 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/keyboard.h
View File

@@ -8,7 +8,7 @@
* *
* Definitions for the keyboard interface. * Definitions for the keyboard interface.
* *
* Version: @(#)keyboard.h 1.0.3 2018/03/15 * Version: @(#)keyboard.h 1.0.4 2018/03/22
* *
* Authors: Fred N. van Kempen, <decwiz@yahoo.com> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -86,6 +86,7 @@ extern const device_t keyboard_at_toshiba_device;
extern const device_t keyboard_ps2_device; extern const device_t keyboard_ps2_device;
extern const device_t keyboard_ps2_ami_device; extern const device_t keyboard_ps2_ami_device;
extern const device_t keyboard_ps2_mca_device; extern const device_t keyboard_ps2_mca_device;
extern const device_t keyboard_ps2_mca_2_device;
extern const device_t keyboard_ps2_quadtel_device; extern const device_t keyboard_ps2_quadtel_device;
#endif #endif

20
src/keyboard_at.c
View File

@@ -8,7 +8,7 @@
* *
* Intel 8042 (AT keyboard controller) emulation. * Intel 8042 (AT keyboard controller) emulation.
* *
* Version: @(#)keyboard_at.c 1.0.8 2018/03/18 * Version: @(#)keyboard_at.c 1.0.9 2018/03/22
* *
* Authors: Fred N. van Kempen, <decwiz@yahoo.com> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -1916,6 +1916,14 @@ kbd_init(const device_t *info)
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, kbd); timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, kbd);
if ((kbd->flags & KBC_TYPE_MASK) != KBC_TYPE_ISA) { if ((kbd->flags & KBC_TYPE_MASK) != KBC_TYPE_ISA) {
if ((kbd->flags & KBC_TYPE_MASK) == KBC_TYPE_PS2_2) {
/*
* These machines force translation off, so the
* the keyboard must start in scan code set 0.
*/
keyboard_mode &= ~0x03;
}
timer_add(kbd_refresh, timer_add(kbd_refresh,
&kbd->refresh_time, TIMER_ALWAYS_ENABLED, kbd); &kbd->refresh_time, TIMER_ALWAYS_ENABLED, kbd);
} }
@@ -2040,6 +2048,16 @@ const device_t keyboard_ps2_mca_device = {
NULL, NULL, NULL, NULL NULL, NULL, NULL, NULL
}; };
const device_t keyboard_ps2_mca_2_device = {
"PS/2 Keyboard",
0,
KBC_TYPE_PS2_2 | KBC_VEN_IBM_MCA,
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
};
const device_t keyboard_ps2_quadtel_device = { const device_t keyboard_ps2_quadtel_device = {
"PS/2 Keyboard (Quadtel/MegaPC)", "PS/2 Keyboard (Quadtel/MegaPC)",
0, 0,

199
src/machine/m_ps2_mca.c
View File

@@ -8,7 +8,7 @@
* *
* Implementation of MCA-based PS/2 machines. * Implementation of MCA-based PS/2 machines.
* *
* Version: @(#)m_ps2_mca.c 1.0.6 2018/03/21 * Version: @(#)m_ps2_mca.c 1.0.7 2018/03/22
* *
* Authors: Fred N. van Kempen, <decwiz@yahoo.com> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -780,6 +780,68 @@ static void ps2_mem_expansion_write(int port, uint8_t val, void *p)
mem_mapping_disable(&ps2.expansion_mapping); mem_mapping_disable(&ps2.expansion_mapping);
} }
static void ps2_mca_mem_fffc_init(int start_mb)
{
uint32_t planar_size, expansion_start;
if (start_mb == 2) {
planar_size = 0x160000;
expansion_start = 0x260000;
} else {
planar_size = (start_mb - 1) << 20;
expansion_start = start_mb << 20;
}
mem_mapping_set_addr(&ram_high_mapping, 0x100000, planar_size);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch ((mem_size / 1024) - start_mb)
{
case 1:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 2:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 3:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 4:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 5:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
expansion_start,
(mem_size - (start_mb << 10)) << 10,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[expansion_start],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
static void ps2_mca_board_model_50_init() static void ps2_mca_board_model_50_init()
{ {
ps2_mca_board_common_init(); ps2_mca_board_common_init();
@@ -793,53 +855,7 @@ static void ps2_mca_board_model_50_init()
if (mem_size > 2048) if (mem_size > 2048)
{ {
/* Only 2 MB supported on planar, create a memory expansion card for the rest */ /* Only 2 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x160000); ps2_mca_mem_fffc_init(2);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 3:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 4:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 5:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 9:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 10:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x260000,
(mem_size - 2048)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x260000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
} }
device_add(&ps1vga_device); device_add(&ps1vga_device);
@@ -1043,7 +1059,6 @@ static void ps2_mca_board_model_70_type34_init(int is_type4)
{ {
ps2_mca_board_common_init(); ps2_mca_board_common_init();
mem_remap_top_256k();
ps2.split_addr = mem_size * 1024; ps2.split_addr = mem_size * 1024;
mca_init(4); mca_init(4);
@@ -1111,41 +1126,7 @@ static void ps2_mca_board_model_70_type34_init(int is_type4)
if (mem_size > 8192) if (mem_size > 8192)
{ {
/* Only 8 MB supported on planar, create a memory expansion card for the rest */ /* Only 8 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x700000); ps2_mca_mem_fffc_init(8);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 10:
ps2.mem_pos_regs[4] = 0xfe;
break;
case 12:
ps2.mem_pos_regs[4] = 0xfa;
break;
case 14:
ps2.mem_pos_regs[4] = 0xea;
break;
case 16:
ps2.mem_pos_regs[4] = 0xaa;
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x800000,
(mem_size - 8192)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x800000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
} }
device_add(&ps1vga_device); device_add(&ps1vga_device);
@@ -1214,55 +1195,7 @@ static void ps2_mca_board_model_80_type2_init(int is486)
if ((mem_size > 4096) && !is486) if ((mem_size > 4096) && !is486)
{ {
/* Only 4 MB supported on planar, create a memory expansion card for the rest */ /* Only 4 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x300000); ps2_mca_mem_fffc_init(4);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 5:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 9:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 10:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 11:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 12:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
/* pclog("ps2.mem_pos_regs[4] = %08X\n", ps2.mem_pos_regs[4]); */
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x400000,
(mem_size - 4096)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x400000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
} }
device_add(&ps1vga_device); device_add(&ps1vga_device);

8
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS. * NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine. * PS2_M80-486 wip, pending receipt of TRM's for machine.
* *
* Version: @(#)machine_table.c 1.0.13 2018/03/19 * Version: @(#)machine_table.c 1.0.14 2018/03/22
* *
* Authors: Fred N. van Kempen, <decwiz@yahoo.com> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -109,7 +109,7 @@ const machine_t machines[] = {
{ "[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibm_ps1_2121", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL }, { "[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibm_ps1_2121", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibm_ps1_2121_isa", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL }, { "[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibm_ps1_2121_isa", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibm_ps2_m55sx", L"ibm/ps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 8, 1, 68, machine_ps2_model_55sx_init, NULL, NULL }, { "[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibm_ps2_m55sx", L"ibm/ps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 8, 1, 128, machine_ps2_model_55sx_init, NULL, NULL },
{ "[386SX ISA] KMX-C-02", ROM_KMXC02, "kmxc02", L"unknown/kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 128, machine_at_scatsx_init, NULL, NULL }, { "[386SX ISA] KMX-C-02", ROM_KMXC02, "kmxc02", L"unknown/kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 128, machine_at_scatsx_init, NULL, NULL },
{ "[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami_386dx", L"generic/ami/386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_ami_init, NULL, NULL }, { "[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami_386dx", L"generic/ami/386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_ami_init, NULL, NULL },
@@ -120,7 +120,7 @@ const machine_t machines[] = {
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portable3_386", L"compaq/deskpro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, machine_at_compaq_init, NULL, NULL }, { "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portable3_386", L"compaq/deskpro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, machine_at_compaq_init, NULL, NULL },
#endif #endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL, NULL }, { "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type3_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibm_ps2_m80", L"ibm/ps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 12, 1, 64, machine_ps2_model_80_init, NULL, NULL }, { "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibm_ps2_m80", L"ibm/ps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 12, 1, 64, machine_ps2_model_80_init, NULL, NULL },
{ "[486 ISA] AMI 486 clone", ROM_AMI486, "ami_486", L"generic/ami/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, NULL }, { "[486 ISA] AMI 486 clone", ROM_AMI486, "ami_486", L"generic/ami/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, NULL },
@@ -128,7 +128,7 @@ const machine_t machines[] = {
{ "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award_486", L"generic/award/opti495", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_init, NULL, NULL }, { "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award_486", L"generic/award/opti495", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_init, NULL, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk_486", L"dtk/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_dtk486_init, NULL, NULL }, { "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk_486", L"dtk/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_dtk486_init, NULL, NULL },
{ "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibm_ps1_2133", L"ibm/ps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 128, machine_ps1_m2133_init, NULL, NULL }, { "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibm_ps1_2133", L"ibm/ps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 128, machine_ps1_m2133_init, NULL, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 64, 2, 63, machine_ps2_model_70_type4_init, NULL, NULL }, { "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type4_init, NULL, NULL },
{ "[486 PCI] Rise Computer R418", ROM_R418, "rise_r418", L"rise/r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_r418_init, NULL, NULL }, { "[486 PCI] Rise Computer R418", ROM_R418, "rise_r418", L"rise/r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_r418_init, NULL, NULL },

248
src/video/vid_cl54xx.c
View File

@@ -9,7 +9,7 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428, * Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, 5430, 5434 and 5436 are supported). * CL-GD 5429, 5430, 5434 and 5436 are supported).
* *
* Version: @(#)vid_cl54xx.c 1.0.11 2018/03/21 * Version: @(#)vid_cl54xx.c 1.0.12 2018/03/22
* *
* Authors: Fred N. van Kempen, <decwiz@yahoo.com> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -61,14 +61,14 @@
#define BIOS_GD5426_PATH L"roms/video/cirruslogic/diamond speedstar pro vlb v3.04.bin" #define BIOS_GD5426_PATH L"roms/video/cirruslogic/diamond speedstar pro vlb v3.04.bin"
#define BIOS_GD5428_PATH L"roms/video/cirruslogic/vlbusjapan.bin" #define BIOS_GD5428_PATH L"roms/video/cirruslogic/vlbusjapan.bin"
#define BIOS_GD5429_PATH L"roms/video/cirruslogic/5429.vbi" #define BIOS_GD5429_PATH L"roms/video/cirruslogic/gd5429.vbi"
#define BIOS_GD5430_VLB_PATH L"roms/video/cirruslogic/diamondvlbus.bin" #define BIOS_GD5430_VLB_PATH L"roms/video/cirruslogic/diamondvlbus.bin"
#define BIOS_GD5430_PCI_PATH L"roms/video/cirruslogic/pci.bin" #define BIOS_GD5430_PCI_PATH L"roms/video/cirruslogic/gd5430pci.bin"
#define BIOS_GD5434_PATH L"roms/video/cirruslogic/gd5434.bin" #define BIOS_GD5434_PATH L"roms/video/cirruslogic/gd5434.bin"
#define BIOS_GD5436_PATH L"roms/video/cirruslogic/5436.vbi" #define BIOS_GD5436_PATH L"roms/video/cirruslogic/gd5436.vbi"
#define BIOS_GD5446_PATH L"roms/video/cirruslogic/5446bv.vbi" #define BIOS_GD5446_PATH L"roms/video/cirruslogic/gd5446bv.vbi"
#define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb nitro64v.bin" #define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb_nitro64v.bin"
#define BIOS_GD5480_PATH L"roms/video/cirruslogic/clgd5480.rom" #define BIOS_GD5480_PATH L"roms/video/cirruslogic/gd5480.rom"
#define CIRRUS_ID_CLGD5426 0x90 #define CIRRUS_ID_CLGD5426 0x90
#define CIRRUS_ID_CLGD5428 0x98 #define CIRRUS_ID_CLGD5428 0x98
@@ -1883,6 +1883,8 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
{ {
int blt_mask = 0; int blt_mask = 0;
int x_max = 0; int x_max = 0;
int shift = 0, last_x = 0;
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8: case CIRRUS_BLTMODE_PIXELWIDTH8:
@@ -1903,7 +1905,9 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
x_max = 32; x_max = 32;
blt_mask *= 4; blt_mask *= 4;
break; break;
} }
last_x = (x_max >> 3) - 1;
if (count == -1) { if (count == -1) {
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr; gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr;
@@ -1917,26 +1921,20 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.y_count = 0; gd54xx->blt.y_count = 0;
if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) == (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) { if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) == (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) {
if (!(svga->seqregs[7] & 0xf0)) if (!(svga->seqregs[7] & 0xf0)) {
{
mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l); mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l);
mem_mapping_set_p(&svga->mapping, gd54xx); mem_mapping_set_p(&svga->mapping, gd54xx);
} } else {
else
{
mem_mapping_set_handler(&gd54xx->linear_mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l); mem_mapping_set_handler(&gd54xx->linear_mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l);
mem_mapping_set_p(&gd54xx->linear_mapping, gd54xx); mem_mapping_set_p(&gd54xx->linear_mapping, gd54xx);
} }
gd543x_recalc_mapping(gd54xx); gd543x_recalc_mapping(gd54xx);
return; return;
} else if (gd54xx->blt.mode != CIRRUS_BLTMODE_MEMSYSSRC) { } else if (gd54xx->blt.mode != CIRRUS_BLTMODE_MEMSYSSRC) {
if (!(svga->seqregs[7] & 0xf0)) if (!(svga->seqregs[7] & 0xf0)) {
{
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel); mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_set_p(&gd54xx->svga.mapping, gd54xx); mem_mapping_set_p(&gd54xx->svga.mapping, gd54xx);
} } else {
else
{
mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear); mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear);
mem_mapping_set_p(&gd54xx->linear_mapping, svga); mem_mapping_set_p(&gd54xx->linear_mapping, svga);
} }
@@ -1951,59 +1949,33 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) { if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) { if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY) if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
mask = (cpu_dat >> 31); mask = (cpu_dat >> 31);
else else
mask = cpu_dat & 0x80; mask = cpu_dat & 0x80;
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
{ case CIRRUS_BLTMODE_PIXELWIDTH8:
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col; src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
cpu_dat <<= 1; shift = 0;
count--;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH16: case CIRRUS_BLTMODE_PIXELWIDTH16:
if (gd54xx->blt.x_count & 1) shift = (gd54xx->blt.x_count & 1);
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if (gd54xx->blt.x_count & 1)
{
cpu_dat <<= 1;
count--;
}
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH24: case CIRRUS_BLTMODE_PIXELWIDTH24:
if ((gd54xx->blt.x_count % 3) == 2) shift = (gd54xx->blt.x_count % 3);
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.x_count % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if ((gd54xx->blt.x_count % 3) == 2)
{
cpu_dat <<= 1;
count--;
}
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH32: case CIRRUS_BLTMODE_PIXELWIDTH32:
if ((gd54xx->blt.x_count & 3) == 3) shift = (gd54xx->blt.x_count & 3);
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.x_count & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.x_count & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if ((gd54xx->blt.x_count & 3) == 3)
{
cpu_dat <<= 1;
count--;
}
break; break;
} }
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
if (shift == last_x) {
cpu_dat <<= 1;
count--;
}
} }
} else { } else {
switch (gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) { switch (gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) {
@@ -2013,134 +1985,82 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
mask = 1; mask = 1;
break; break;
case CIRRUS_BLTMODE_PATTERNCOPY: case CIRRUS_BLTMODE_PATTERNCOPY:
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
{ case CIRRUS_BLTMODE_PIXELWIDTH8:
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~7)) + (gd54xx->blt.y_count << 3) + (gd54xx->blt.x_count & 7)]; src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~7)) + (gd54xx->blt.y_count << 3) + (gd54xx->blt.x_count & 7)];
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH16: case CIRRUS_BLTMODE_PIXELWIDTH16:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~15)) + (gd54xx->blt.y_count << 4) + (gd54xx->blt.x_count & 15)]; src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~15)) + (gd54xx->blt.y_count << 4) + (gd54xx->blt.x_count & 15)];
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH24: case CIRRUS_BLTMODE_PIXELWIDTH24:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count % 31)]; src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count % 24)];
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH32: case CIRRUS_BLTMODE_PIXELWIDTH32:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count & 31)]; src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count & 31)];
break; break;
} }
mask = 1; mask = 1;
break; break;
case CIRRUS_BLTMODE_COLOREXPAND: case CIRRUS_BLTMODE_COLOREXPAND:
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
{ case CIRRUS_BLTMODE_PIXELWIDTH8:
case CIRRUS_BLTMODE_PIXELWIDTH8:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> gd54xx->blt.x_count); mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> gd54xx->blt.x_count);
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col; shift = 0;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH16: case CIRRUS_BLTMODE_PIXELWIDTH16:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 1)); mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 1));
if (gd54xx->blt.dst_addr & 1) shift = (gd54xx->blt.dst_addr & 1);
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH24: case CIRRUS_BLTMODE_PIXELWIDTH24:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count / 3)); mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count / 3));
if ((gd54xx->blt.dst_addr % 3) == 2) shift = (gd54xx->blt.dst_addr % 3);
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH32: case CIRRUS_BLTMODE_PIXELWIDTH32:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 2)); mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 2));
if ((gd54xx->blt.dst_addr & 3) == 3) shift = (gd54xx->blt.dst_addr & 3);
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
break; break;
} }
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
break; break;
case CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND: case CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND:
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) {
{ switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) case CIRRUS_BLTMODE_PIXELWIDTH8:
{ shift = 0;
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = gd54xx->blt.fg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH16: case CIRRUS_BLTMODE_PIXELWIDTH16:
if (gd54xx->blt.dst_addr & 1) shift = (gd54xx->blt.dst_addr & 1);
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH24: case CIRRUS_BLTMODE_PIXELWIDTH24:
if ((gd54xx->blt.dst_addr % 3) == 2) shift = (gd54xx->blt.dst_addr % 3);
src = (gd54xx->blt.fg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH32: case CIRRUS_BLTMODE_PIXELWIDTH32:
if ((gd54xx->blt.dst_addr & 3) == 3) shift = (gd54xx->blt.dst_addr & 3);
src = (gd54xx->blt.fg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = (gd54xx->blt.fg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
break; break;
} }
} src = (gd54xx->blt.fg_col >> (shift << 3));
else } else {
{ switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) case CIRRUS_BLTMODE_PIXELWIDTH8:
{
case CIRRUS_BLTMODE_PIXELWIDTH8:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> gd54xx->blt.x_count); mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> gd54xx->blt.x_count);
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col; shift = 0;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH16: case CIRRUS_BLTMODE_PIXELWIDTH16:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 1)); mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 1));
if (gd54xx->blt.dst_addr & 1) shift = (gd54xx->blt.dst_addr & 1);
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH24: case CIRRUS_BLTMODE_PIXELWIDTH24:
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5436) mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count / 3));
{ shift = (gd54xx->blt.dst_addr % 3);
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count / 3));
if ((gd54xx->blt.dst_addr % 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
}
break; break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
case CIRRUS_BLTMODE_PIXELWIDTH32:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 2)); mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 2));
if ((gd54xx->blt.dst_addr & 3) == 3) shift = (gd54xx->blt.dst_addr & 3);
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
break; break;
} }
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
} }
break; break;
} }
@@ -2168,14 +2088,11 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
case 0xda: dst = ~(src & dst); break; case 0xda: dst = ~(src & dst); break;
} }
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
{
if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask && if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask &&
!((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && mask)) !((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && mask))
svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst; svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst;
} } else {
else
{
if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask && if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask &&
!((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && !mask)) !((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && !mask))
svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst; svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst;
@@ -2185,8 +2102,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.x_count++; gd54xx->blt.x_count++;
if (gd54xx->blt.x_count == x_max) if (gd54xx->blt.x_count == x_max) {
{
gd54xx->blt.x_count = 0; gd54xx->blt.x_count = 0;
if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) == CIRRUS_BLTMODE_COLOREXPAND) if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) == CIRRUS_BLTMODE_COLOREXPAND)
gd54xx->blt.src_addr++; gd54xx->blt.src_addr++;
@@ -2217,15 +2133,11 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.height_internal--; gd54xx->blt.height_internal--;
if (gd54xx->blt.height_internal == 0xffff) { if (gd54xx->blt.height_internal == 0xffff) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) {
{ if (!(svga->seqregs[7] & 0xf0)) {
if (!(svga->seqregs[7] & 0xf0))
{
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel); mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_set_p(&svga->mapping, gd54xx); mem_mapping_set_p(&svga->mapping, gd54xx);
} } else {
else
{
mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear); mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear);
mem_mapping_set_p(&gd54xx->linear_mapping, svga); mem_mapping_set_p(&gd54xx->linear_mapping, svga);
} }

492
src/video/vid_s3_virge.c
View File

File diff suppressed because it is too large Load Diff