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Small fixes here and there.

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Applied upstream commits where needed.
Renamed some of the CirrusLogic bioses.
This commit is contained in:
waltje
2018-03-22 20:20:30 -05:00
parent 85d291205f
commit 6898e2776c
6 changed files with 428 additions and 542 deletions
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3
src/keyboard.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the keyboard interface.
*
* Version: @(#)keyboard.h 1.0.3 2018/03/15
* Version: @(#)keyboard.h 1.0.4 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -86,6 +86,7 @@ extern const device_t keyboard_at_toshiba_device;
extern const device_t keyboard_ps2_device;
extern const device_t keyboard_ps2_ami_device;
extern const device_t keyboard_ps2_mca_device;
extern const device_t keyboard_ps2_mca_2_device;
extern const device_t keyboard_ps2_quadtel_device;
#endif

20
src/keyboard_at.c
View File

@@ -8,7 +8,7 @@
*
* Intel 8042 (AT keyboard controller) emulation.
*
* Version: @(#)keyboard_at.c 1.0.8 2018/03/18
* Version: @(#)keyboard_at.c 1.0.9 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -1916,6 +1916,14 @@ kbd_init(const device_t *info)
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, kbd);
if ((kbd->flags & KBC_TYPE_MASK) != KBC_TYPE_ISA) {
if ((kbd->flags & KBC_TYPE_MASK) == KBC_TYPE_PS2_2) {
/*
* These machines force translation off, so the
* the keyboard must start in scan code set 0.
*/
keyboard_mode &= ~0x03;
}
timer_add(kbd_refresh,
&kbd->refresh_time, TIMER_ALWAYS_ENABLED, kbd);
}
@@ -2040,6 +2048,16 @@ const device_t keyboard_ps2_mca_device = {
NULL, NULL, NULL, NULL
};
const device_t keyboard_ps2_mca_2_device = {
"PS/2 Keyboard",
0,
KBC_TYPE_PS2_2 | KBC_VEN_IBM_MCA,
kbd_init,
kbd_close,
kbd_reset,
NULL, NULL, NULL, NULL
};
const device_t keyboard_ps2_quadtel_device = {
"PS/2 Keyboard (Quadtel/MegaPC)",
0,

199
src/machine/m_ps2_mca.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of MCA-based PS/2 machines.
*
* Version: @(#)m_ps2_mca.c 1.0.6 2018/03/21
* Version: @(#)m_ps2_mca.c 1.0.7 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -780,6 +780,68 @@ static void ps2_mem_expansion_write(int port, uint8_t val, void *p)
mem_mapping_disable(&ps2.expansion_mapping);
}
static void ps2_mca_mem_fffc_init(int start_mb)
{
uint32_t planar_size, expansion_start;
if (start_mb == 2) {
planar_size = 0x160000;
expansion_start = 0x260000;
} else {
planar_size = (start_mb - 1) << 20;
expansion_start = start_mb << 20;
}
mem_mapping_set_addr(&ram_high_mapping, 0x100000, planar_size);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch ((mem_size / 1024) - start_mb)
{
case 1:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 2:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 3:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 4:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 5:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
expansion_start,
(mem_size - (start_mb << 10)) << 10,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[expansion_start],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
static void ps2_mca_board_model_50_init()
{
ps2_mca_board_common_init();
@@ -793,53 +855,7 @@ static void ps2_mca_board_model_50_init()
if (mem_size > 2048)
{
/* Only 2 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x160000);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 3:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 4:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 5:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 9:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 10:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x260000,
(mem_size - 2048)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x260000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
ps2_mca_mem_fffc_init(2);
}
device_add(&ps1vga_device);
@@ -1043,7 +1059,6 @@ static void ps2_mca_board_model_70_type34_init(int is_type4)
{
ps2_mca_board_common_init();
mem_remap_top_256k();
ps2.split_addr = mem_size * 1024;
mca_init(4);
@@ -1111,41 +1126,7 @@ static void ps2_mca_board_model_70_type34_init(int is_type4)
if (mem_size > 8192)
{
/* Only 8 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x700000);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 10:
ps2.mem_pos_regs[4] = 0xfe;
break;
case 12:
ps2.mem_pos_regs[4] = 0xfa;
break;
case 14:
ps2.mem_pos_regs[4] = 0xea;
break;
case 16:
ps2.mem_pos_regs[4] = 0xaa;
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x800000,
(mem_size - 8192)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x800000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
ps2_mca_mem_fffc_init(8);
}
device_add(&ps1vga_device);
@@ -1214,55 +1195,7 @@ static void ps2_mca_board_model_80_type2_init(int is486)
if ((mem_size > 4096) && !is486)
{
/* Only 4 MB supported on planar, create a memory expansion card for the rest */
mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x300000);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch (mem_size/1024)
{
case 5:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 9:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 10:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 11:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 12:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
}
/* pclog("ps2.mem_pos_regs[4] = %08X\n", ps2.mem_pos_regs[4]); */
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
mem_mapping_add(&ps2.expansion_mapping,
0x400000,
(mem_size - 4096)*1024,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[0x400000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
ps2_mca_mem_fffc_init(4);
}
device_add(&ps1vga_device);

8
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.13 2018/03/19
* Version: @(#)machine_table.c 1.0.14 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -109,7 +109,7 @@ const machine_t machines[] = {
{ "[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibm_ps1_2121", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibm_ps1_2121_isa", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 128, machine_ps1_m2121_init, NULL, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibm_ps2_m55sx", L"ibm/ps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 8, 1, 68, machine_ps2_model_55sx_init, NULL, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", ROM_IBMPS2_M55SX, "ibm_ps2_m55sx", L"ibm/ps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 8, 1, 128, machine_ps2_model_55sx_init, NULL, NULL },
{ "[386SX ISA] KMX-C-02", ROM_KMXC02, "kmxc02", L"unknown/kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 128, machine_at_scatsx_init, NULL, NULL },
{ "[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami_386dx", L"generic/ami/386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_ami_init, NULL, NULL },
@@ -120,7 +120,7 @@ const machine_t machines[] = {
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portable3_386", L"compaq/deskpro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, machine_at_compaq_init, NULL, NULL },
#endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", ROM_IBMPS2_M70_TYPE3, "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type3_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 80", ROM_IBMPS2_M80, "ibm_ps2_m80", L"ibm/ps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 12, 1, 64, machine_ps2_model_80_init, NULL, NULL },
{ "[486 ISA] AMI 486 clone", ROM_AMI486, "ami_486", L"generic/ami/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, NULL },
@@ -128,7 +128,7 @@ const machine_t machines[] = {
{ "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award_486", L"generic/award/opti495", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_init, NULL, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk_486", L"dtk/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_dtk486_init, NULL, NULL },
{ "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibm_ps1_2133", L"ibm/ps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 128, machine_ps1_m2133_init, NULL, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 64, 2, 63, machine_ps2_model_70_type4_init, NULL, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", ROM_IBMPS2_M70_TYPE4, "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type4_init, NULL, NULL },
{ "[486 PCI] Rise Computer R418", ROM_R418, "rise_r418", L"rise/r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_r418_init, NULL, NULL },

198
src/video/vid_cl54xx.c
View File

@@ -9,7 +9,7 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, 5430, 5434 and 5436 are supported).
*
* Version: @(#)vid_cl54xx.c 1.0.11 2018/03/21
* Version: @(#)vid_cl54xx.c 1.0.12 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -61,14 +61,14 @@
#define BIOS_GD5426_PATH L"roms/video/cirruslogic/diamond speedstar pro vlb v3.04.bin"
#define BIOS_GD5428_PATH L"roms/video/cirruslogic/vlbusjapan.bin"
#define BIOS_GD5429_PATH L"roms/video/cirruslogic/5429.vbi"
#define BIOS_GD5429_PATH L"roms/video/cirruslogic/gd5429.vbi"
#define BIOS_GD5430_VLB_PATH L"roms/video/cirruslogic/diamondvlbus.bin"
#define BIOS_GD5430_PCI_PATH L"roms/video/cirruslogic/pci.bin"
#define BIOS_GD5430_PCI_PATH L"roms/video/cirruslogic/gd5430pci.bin"
#define BIOS_GD5434_PATH L"roms/video/cirruslogic/gd5434.bin"
#define BIOS_GD5436_PATH L"roms/video/cirruslogic/5436.vbi"
#define BIOS_GD5446_PATH L"roms/video/cirruslogic/5446bv.vbi"
#define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb nitro64v.bin"
#define BIOS_GD5480_PATH L"roms/video/cirruslogic/clgd5480.rom"
#define BIOS_GD5436_PATH L"roms/video/cirruslogic/gd5436.vbi"
#define BIOS_GD5446_PATH L"roms/video/cirruslogic/gd5446bv.vbi"
#define BIOS_GD5446_STB_PATH L"roms/video/cirruslogic/stb_nitro64v.bin"
#define BIOS_GD5480_PATH L"roms/video/cirruslogic/gd5480.rom"
#define CIRRUS_ID_CLGD5426 0x90
#define CIRRUS_ID_CLGD5428 0x98
@@ -1884,6 +1884,8 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
int blt_mask = 0;
int x_max = 0;
int shift = 0, last_x = 0;
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
blt_mask = gd54xx->blt.mask & 7;
@@ -1905,6 +1907,8 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
break;
}
last_x = (x_max >> 3) - 1;
if (count == -1) {
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr;
gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr;
@@ -1917,26 +1921,20 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.y_count = 0;
if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) == (CIRRUS_BLTMODE_MEMSYSSRC|CIRRUS_BLTMODE_COLOREXPAND)) {
if (!(svga->seqregs[7] & 0xf0))
{
if (!(svga->seqregs[7] & 0xf0)) {
mem_mapping_set_handler(&svga->mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l);
mem_mapping_set_p(&svga->mapping, gd54xx);
}
else
{
} else {
mem_mapping_set_handler(&gd54xx->linear_mapping, NULL, NULL, NULL, NULL, gd54xx_blt_write_w, gd54xx_blt_write_l);
mem_mapping_set_p(&gd54xx->linear_mapping, gd54xx);
}
gd543x_recalc_mapping(gd54xx);
return;
} else if (gd54xx->blt.mode != CIRRUS_BLTMODE_MEMSYSSRC) {
if (!(svga->seqregs[7] & 0xf0))
{
if (!(svga->seqregs[7] & 0xf0)) {
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_set_p(&gd54xx->svga.mapping, gd54xx);
}
else
{
} else {
mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear);
mem_mapping_set_p(&gd54xx->linear_mapping, svga);
}
@@ -1951,59 +1949,33 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
mask = (cpu_dat >> 31);
else
mask = cpu_dat & 0x80;
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
cpu_dat <<= 1;
count--;
shift = 0;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
if (gd54xx->blt.x_count & 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if (gd54xx->blt.x_count & 1)
{
cpu_dat <<= 1;
count--;
}
shift = (gd54xx->blt.x_count & 1);
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
if ((gd54xx->blt.x_count % 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.x_count % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if ((gd54xx->blt.x_count % 3) == 2)
{
cpu_dat <<= 1;
count--;
}
shift = (gd54xx->blt.x_count % 3);
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
if ((gd54xx->blt.x_count & 3) == 3)
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.x_count & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.x_count & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
if ((gd54xx->blt.x_count & 3) == 3)
{
shift = (gd54xx->blt.x_count & 3);
break;
}
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
if (shift == last_x) {
cpu_dat <<= 1;
count--;
}
break;
}
}
} else {
switch (gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) {
@@ -2013,8 +1985,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
mask = 1;
break;
case CIRRUS_BLTMODE_PATTERNCOPY:
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~7)) + (gd54xx->blt.y_count << 3) + (gd54xx->blt.x_count & 7)];
break;
@@ -2022,7 +1993,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~15)) + (gd54xx->blt.y_count << 4) + (gd54xx->blt.x_count & 15)];
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count % 31)];
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count % 24)];
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
src = svga->vram[(gd54xx->blt.src_addr & (svga->vram_mask & ~31)) + (gd54xx->blt.y_count << 5) + (gd54xx->blt.x_count & 31)];
@@ -2031,116 +2002,65 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
mask = 1;
break;
case CIRRUS_BLTMODE_COLOREXPAND:
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> gd54xx->blt.x_count);
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = 0;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 1));
if (gd54xx->blt.dst_addr & 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = (gd54xx->blt.dst_addr & 1);
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count / 3));
if ((gd54xx->blt.dst_addr % 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = (gd54xx->blt.dst_addr % 3);
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
mask = svga->vram[gd54xx->blt.src_addr & svga->vram_mask] & (0x80 >> (gd54xx->blt.x_count >> 2));
if ((gd54xx->blt.dst_addr & 3) == 3)
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = (gd54xx->blt.dst_addr & 3);
break;
}
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
break;
case CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND:
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL)
{
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) {
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
src = gd54xx->blt.fg_col;
shift = 0;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
if (gd54xx->blt.dst_addr & 1)
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
shift = (gd54xx->blt.dst_addr & 1);
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
if ((gd54xx->blt.dst_addr % 3) == 2)
src = (gd54xx->blt.fg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
shift = (gd54xx->blt.dst_addr % 3);
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
if ((gd54xx->blt.dst_addr & 3) == 3)
src = (gd54xx->blt.fg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = (gd54xx->blt.fg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = (gd54xx->blt.fg_col >> 8);
else
src = gd54xx->blt.fg_col;
shift = (gd54xx->blt.dst_addr & 3);
break;
}
}
else
{
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
src = (gd54xx->blt.fg_col >> (shift << 3));
} else {
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> gd54xx->blt.x_count);
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = 0;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 1));
if (gd54xx->blt.dst_addr & 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = (gd54xx->blt.dst_addr & 1);
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5436)
{
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count / 3));
if ((gd54xx->blt.dst_addr % 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr % 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
}
shift = (gd54xx->blt.dst_addr % 3);
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
mask = svga->vram[(gd54xx->blt.src_addr & svga->vram_mask & ~7) | gd54xx->blt.y_count] & (0x80 >> (gd54xx->blt.x_count >> 2));
if ((gd54xx->blt.dst_addr & 3) == 3)
src = mask ? (gd54xx->blt.fg_col >> 24) : (gd54xx->blt.bg_col >> 24);
else if ((gd54xx->blt.dst_addr & 3) == 2)
src = mask ? (gd54xx->blt.fg_col >> 16) : (gd54xx->blt.bg_col >> 16);
else if ((gd54xx->blt.dst_addr & 3) == 1)
src = mask ? (gd54xx->blt.fg_col >> 8) : (gd54xx->blt.bg_col >> 8);
else
src = mask ? gd54xx->blt.fg_col : gd54xx->blt.bg_col;
shift = (gd54xx->blt.dst_addr & 3);
break;
}
src = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
}
break;
}
@@ -2168,14 +2088,11 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
case 0xda: dst = ~(src & dst); break;
}
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
{
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask &&
!((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && mask))
svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst;
}
else
{
} else {
if ((gd54xx->blt.width_backup - gd54xx->blt.width) >= blt_mask &&
!((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && !mask))
svga->vram[gd54xx->blt.dst_addr & svga->vram_mask] = dst;
@@ -2185,8 +2102,7 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.x_count++;
if (gd54xx->blt.x_count == x_max)
{
if (gd54xx->blt.x_count == x_max) {
gd54xx->blt.x_count = 0;
if ((gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY|CIRRUS_BLTMODE_COLOREXPAND)) == CIRRUS_BLTMODE_COLOREXPAND)
gd54xx->blt.src_addr++;
@@ -2217,15 +2133,11 @@ gd54xx_start_blit(uint32_t cpu_dat, int count, gd54xx_t *gd54xx, svga_t *svga)
gd54xx->blt.height_internal--;
if (gd54xx->blt.height_internal == 0xffff) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC)
{
if (!(svga->seqregs[7] & 0xf0))
{
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC) {
if (!(svga->seqregs[7] & 0xf0)) {
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_set_p(&svga->mapping, gd54xx);
}
else
{
} else {
mem_mapping_set_handler(&gd54xx->linear_mapping, svga_readb_linear, svga_readw_linear, svga_readl_linear, gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear);
mem_mapping_set_p(&gd54xx->linear_mapping, svga);
}

128
src/video/vid_s3_virge.c
View File

@@ -8,7 +8,7 @@
*
* S3 ViRGE emulation.
*
* Version: @(#)vid_s3_virge.c 1.0.5 2018/03/15
* Version: @(#)vid_s3_virge.c 1.0.6 2018/03/22
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -58,7 +58,7 @@ static uint64_t virge_time = 0;
static uint64_t status_time = 0;
static int reg_writes = 0, reg_reads = 0;
static int dither[4][4] =
static const int8_t dither[4][4] =
{
{0, 4, 1, 5},
{6, 2, 7, 3},
@@ -151,8 +151,6 @@ typedef struct virge_t
uint8_t bank;
uint8_t ma_ext;
int width;
int bpp;
uint8_t virge_id, virge_id_high, virge_id_low, virge_rev;
@@ -175,8 +173,8 @@ typedef struct virge_t
event_t *wake_main_thread;
event_t *not_full_event;
uint32_t hwcursor_col[2];
int hwcursor_col_pos;
uint32_t hwc_fg_col, hwc_bg_col;
int hwc_col_stack_pos;
struct
{
@@ -399,23 +397,9 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
virge->ma_ext = (virge->ma_ext & 0x1c) | ((val & 0x30) >> 4);
break;
case 0x32:
if ((svga->crtc[0x67] & 0xc) != 0xc)
svga->vram_display_mask = (val & 0x40) ? 0x3ffff : ((virge->memory_size << 20) - 1);
s3_virge_update_irqs(virge);
break;
case 0x50:
switch (svga->crtc[0x50] & 0xc1)
{
case 0x00: virge->width = (svga->crtc[0x31] & 2) ? 2048 : 1024; break;
case 0x01: virge->width = 1152; break;
case 0x40: virge->width = 640; break;
case 0x80: virge->width = 800; break;
case 0x81: virge->width = 1600; break;
case 0xc0: virge->width = 1280; break;
}
virge->bpp = (svga->crtc[0x50] >> 4) & 3;
break;
case 0x69:
virge->ma_ext = val & 0x1f;
break;
@@ -454,16 +438,34 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
break;
case 0x4a:
virge->hwcursor_col[1] = (virge->hwcursor_col[1] & ~(0xff << (virge->hwcursor_col_pos * 8))) |
(val << (virge->hwcursor_col_pos * 8));
virge->hwcursor_col_pos++;
virge->hwcursor_col_pos &= 3;
switch (virge->hwc_col_stack_pos)
{
case 0:
virge->hwc_fg_col = (virge->hwc_fg_col & 0xffff00) | val;
break;
case 1:
virge->hwc_fg_col = (virge->hwc_fg_col & 0xff00ff) | (val << 8);
break;
case 2:
virge->hwc_fg_col = (virge->hwc_fg_col & 0x00ffff) | (val << 16);
break;
}
virge->hwc_col_stack_pos = (virge->hwc_col_stack_pos + 1) & 3;
break;
case 0x4b:
virge->hwcursor_col[0] = (virge->hwcursor_col[0] & ~(0xff << (virge->hwcursor_col_pos * 8))) |
(val << (virge->hwcursor_col_pos * 8));
virge->hwcursor_col_pos++;
virge->hwcursor_col_pos &= 3;
switch (virge->hwc_col_stack_pos)
{
case 0:
virge->hwc_bg_col = (virge->hwc_bg_col & 0xffff00) | val;
break;
case 1:
virge->hwc_bg_col = (virge->hwc_bg_col & 0xff00ff) | (val << 8);
break;
case 2:
virge->hwc_bg_col = (virge->hwc_bg_col & 0x00ffff) | (val << 16);
break;
}
virge->hwc_col_stack_pos = (virge->hwc_col_stack_pos + 1) & 3;
break;
case 0x53:
@@ -535,7 +537,7 @@ static uint8_t s3_virge_in(uint16_t addr, void *p)
case 0x31: ret = (svga->crtc[0x31] & 0xcf) | ((virge->ma_ext & 3) << 4); break;
case 0x35: ret = (svga->crtc[0x35] & 0xf0) | (virge->bank & 0xf); break;
case 0x36: ret = (svga->crtc[0x36] & 0xfc) | 2; break; /*PCI bus*/
case 0x45: virge->hwcursor_col_pos = 0; ret = svga->crtc[0x45]; break;
case 0x45: virge->hwc_col_stack_pos = 0; ret = svga->crtc[0x45]; break;
case 0x51: ret = (svga->crtc[0x51] & 0xf0) | ((virge->bank >> 2) & 0xc) | ((virge->ma_ext >> 2) & 3); break;
case 0x69: ret = virge->ma_ext; break;
case 0x6a: ret = virge->bank; break;
@@ -604,7 +606,7 @@ static void s3_virge_recalctimings(svga_t *svga)
svga->rowoffset = (svga->rowoffset * 3) / 4; /*Hack*/
}
}
svga->vram_display_mask = (svga->crtc[0x32] & 0x40) ? 0x3ffff : ((virge->memory_size << 20) - 1);
svga->vram_display_mask = (!(svga->crtc[0x31] & 0x08) && (svga->crtc[0x32] & 0x40)) ? 0x3ffff : ((virge->memory_size << 20) - 1);
}
else /*Streams mode*/
{
@@ -1830,20 +1832,20 @@ static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
switch (bpp) \
{ \
case 0: /*8 bpp*/ \
val = vram[addr & 0x3fffff]; \
val = vram[addr & svga->vram_mask]; \
break; \
case 1: /*16 bpp*/ \
val = *(uint16_t *)&vram[addr & 0x3fffff]; \
val = *(uint16_t *)&vram[addr & svga->vram_mask]; \
break; \
case 2: /*24 bpp*/ \
val = (*(uint32_t *)&vram[addr & 0x3fffff]) & 0xffffff; \
val = (*(uint32_t *)&vram[addr & svga->vram_mask]) & 0xffffff; \
break; \
} \
} while (0)
#define Z_READ(addr) *(uint16_t *)&vram[addr & 0x3fffff]
#define Z_READ(addr) *(uint16_t *)&vram[addr & svga->vram_mask]
#define Z_WRITE(addr, val) if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) *(uint16_t *)&vram[addr & 0x3fffff] = val
#define Z_WRITE(addr, val) if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) *(uint16_t *)&vram[addr & svga->vram_mask] = val
#define CLIP(x, y) \
do \
@@ -1903,23 +1905,24 @@ static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *p)
switch (bpp) \
{ \
case 0: /*8 bpp*/ \
vram[addr & 0x3fffff] = val; \
virge->svga.changedvram[(addr & 0x3fffff) >> 12] = changeframecount; \
vram[addr & svga->vram_mask] = val; \
virge->svga.changedvram[(addr & svga->vram_mask) >> 12] = changeframecount; \
break; \
case 1: /*16 bpp*/ \
*(uint16_t *)&vram[addr & 0x3fffff] = val; \
virge->svga.changedvram[(addr & 0x3fffff) >> 12] = changeframecount; \
*(uint16_t *)&vram[addr & svga->vram_mask] = val; \
virge->svga.changedvram[(addr & svga->vram_mask) >> 12] = changeframecount; \
break; \
case 2: /*24 bpp*/ \
*(uint32_t *)&vram[addr & 0x3fffff] = (val & 0xffffff) | \
(vram[(addr + 3) & 0x3fffff] << 24); \
virge->svga.changedvram[(addr & 0x3fffff) >> 12] = changeframecount; \
*(uint32_t *)&vram[addr & svga->vram_mask] = (val & 0xffffff) | \
(vram[(addr + 3) & svga->vram_mask] << 24); \
virge->svga.changedvram[(addr & svga->vram_mask) >> 12] = changeframecount; \
break; \
} \
} while (0)
static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat)
{
svga_t *svga = &virge->svga;
uint8_t *vram = virge->svga.vram;
uint32_t mono_pattern[64];
int count_mask;
@@ -2936,6 +2939,7 @@ static void dest_pixel_lit_texture_modulate(s3d_state_t *state)
static void tri(virge_t *virge, s3d_t *s3d_tri, s3d_state_t *state, int yc, int32_t dx1, int32_t dx2)
{
svga_t *svga = &virge->svga;
uint8_t *vram = virge->svga.vram;
int x_dir = s3d_tri->tlr ? 1 : -1;
@@ -3079,7 +3083,7 @@ static void tri(virge_t *virge, s3d_t *s3d_tri, s3d_state_t *state, int yc, int3
}
}
virge->svga.changedvram[(dest_offset & 0x3fffff) >> 12] = changeframecount;
virge->svga.changedvram[(dest_offset & svga->vram_mask) >> 12] = changeframecount;
dest_addr = dest_offset + (x * (bpp + 1));
z_addr = z_offset + (x << 1);
@@ -3109,11 +3113,11 @@ static void tri(virge_t *virge, s3d_t *s3d_tri, s3d_state_t *state, int yc, int3
/*Not implemented yet*/
break;
case 1: /*16 bpp*/
src_col = *(uint16_t *)&vram[dest_addr & 0x3fffff];
src_col = *(uint16_t *)&vram[dest_addr & svga->vram_mask];
RGB15_TO_24(src_col, src_r, src_g, src_b);
break;
case 2: /*24 bpp*/
src_col = (*(uint32_t *)&vram[dest_addr & 0x3fffff]) & 0xffffff;
src_col = (*(uint32_t *)&vram[dest_addr & svga->vram_mask]) & 0xffffff;
RGB24_TO_24(src_col, src_r, src_g, src_b);
break;
}
@@ -3372,12 +3376,36 @@ static void s3_virge_hwcursor_draw(svga_t *svga, int displine)
uint16_t dat[2];
int xx;
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
uint32_t fg, bg;
int y_add = (enable_overscan && !suppress_overscan) ? 16 : 0;
int x_add = (enable_overscan && !suppress_overscan) ? 8 : 0;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
switch (svga->bpp)
{
case 15:
fg = video_15to32[virge->hwc_fg_col & 0xffff];
bg = video_15to32[virge->hwc_bg_col & 0xffff];
break;
case 16:
fg = video_16to32[virge->hwc_fg_col & 0xffff];
bg = video_16to32[virge->hwc_bg_col & 0xffff];
break;
case 24: case 32:
fg = virge->hwc_fg_col;
bg = virge->hwc_bg_col;
break;
default:
fg = svga->pallook[virge->hwc_fg_col & 0xff];
bg = svga->pallook[virge->hwc_bg_col & 0xff];
break;
}
for (x = 0; x < 64; x += 16)
{
dat[0] = (svga->vram[svga->hwcursor_latch.addr] << 8) | svga->vram[svga->hwcursor_latch.addr + 1];
@@ -3390,7 +3418,7 @@ static void s3_virge_hwcursor_draw(svga_t *svga, int displine)
if (offset >= svga->hwcursor_latch.x)
{
if (dat[0] & 0x8000)
((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] = virge->hwcursor_col[dat[1] >> 15];
((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] = (dat[1] & 0x8000) ? fg : bg;
}
offset++;
@@ -3406,7 +3434,7 @@ static void s3_virge_hwcursor_draw(svga_t *svga, int displine)
if (offset >= svga->hwcursor_latch.x)
{
if (!(dat[0] & 0x8000))
((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] = virge->hwcursor_col[dat[1] >> 15];
((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] = (dat[1] & 0x8000) ? fg : bg;
else if (dat[1] & 0x8000)
((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] ^= 0xffffff;
}
@@ -3735,7 +3763,6 @@ static uint8_t s3_virge_pci_read(int func, int addr, void *p)
case 0x3e: ret = 0x04; break;
case 0x3f: ret = 0xff; break;
}
return ret;
}
@@ -4105,11 +4132,6 @@ static void *s3_virge_375_4_init(const device_t *info)
static void s3_virge_close(void *p)
{
virge_t *virge = (virge_t *)p;
#if 0
FILE *f = fopen("vram.dmp", "wb");
fwrite(virge->svga.vram, 4 << 20, 1, f);
fclose(f);
#endif
thread_kill(virge->render_thread);
thread_destroy_event(virge->not_full_event);