diff --git a/src/devices/disk/hdc_esdi_mca.c b/src/devices/disk/hdc_esdi_mca.c index c10c394..f6c9780 100644 --- a/src/devices/disk/hdc_esdi_mca.c +++ b/src/devices/disk/hdc_esdi_mca.c @@ -52,7 +52,7 @@ * however, are auto-configured by the system software as * shown above. * - * Version: @(#)hdc_esdi_mca.c 1.0.12 2018/09/22 + * Version: @(#)hdc_esdi_mca.c 1.0.13 2018/10/08 * * Authors: Fred N. van Kempen, * Sarah Walker, @@ -121,6 +121,8 @@ typedef struct { } drive_t; typedef struct { + uint16_t base; + int8_t irq; int8_t dma; uint32_t bios; @@ -216,14 +218,14 @@ static __inline void set_irq(hdc_t *dev) { if (dev->basic_ctrl & CTRL_IRQ_ENA) - picint(1 << ESDI_IRQCHAN); + picint(1 << dev->irq); } static __inline void clear_irq(hdc_t *dev) { - picintc(1 << ESDI_IRQCHAN); + picintc(1 << dev->irq); } @@ -301,36 +303,34 @@ complete_command_status(hdc_t *dev) dev->status_data[0] = CMD_READ | STATUS_LEN(7) | STATUS_DEVICE(0); else dev->status_data[0] = CMD_READ | STATUS_LEN(7) | STATUS_DEVICE(1); - dev->status_data[1] = 0x0000; /*Error bits*/ - dev->status_data[2] = 0x1900; /*Device status*/ - dev->status_data[3] = 0; /*Number of blocks left to do*/ - dev->status_data[4] = (dev->rba-1) & 0xffff; /*Last RBA processed*/ + dev->status_data[1] = 0x0000; /* error bits */ + dev->status_data[2] = 0x1900; /* device status */ + dev->status_data[3] = 0; /* #blocks left to do */ + dev->status_data[4] = (dev->rba-1) & 0xffff; /* last RBA processed */ dev->status_data[5] = (dev->rba-1) >> 8; - dev->status_data[6] = 0; /*Number of blocks requiring error recovery*/ + dev->status_data[6] = 0; /* #blocks requiring error recovery */ } #define ESDI_ADAPTER_ONLY() do \ - { \ - if (dev->cmd_dev != ATTN_HOST_ADAPTER) \ - { \ - cmd_unsupported(dev); \ - return; \ - } \ - } while (0) +{ \ + if (dev->cmd_dev != ATTN_HOST_ADAPTER) { \ + cmd_unsupported(dev); \ + return; \ + } \ +} while (0) #define ESDI_DRIVE_ONLY() do \ - { \ - if (dev->cmd_dev != ATTN_DEVICE_0 && dev->cmd_dev != ATTN_DEVICE_1) \ - { \ - cmd_unsupported(dev); \ - return; \ - } \ - if (dev->cmd_dev == ATTN_DEVICE_0) \ - drive = &dev->drives[0]; \ - else \ - drive = &dev->drives[1]; \ - } while (0) +{ \ + if (dev->cmd_dev != ATTN_DEVICE_0 && dev->cmd_dev != ATTN_DEVICE_1) { \ + cmd_unsupported(dev); \ + return; \ + } \ + if (dev->cmd_dev == ATTN_DEVICE_0) \ + drive = &dev->drives[0]; \ + else \ + drive = &dev->drives[1]; \ +} while (0) static void @@ -391,7 +391,7 @@ hdc_callback(void *priv) while (dev->sector_pos < dev->sector_count) { if (! dev->data_pos) { if (dev->rba >= drive->sectors) - fatal("Read past end of drive\n"); + fatal("ESDI: read past end of drive\n"); hdd_active(drive->hdd_num, 1); hdd_image_read(drive->hdd_num, dev->rba, 1, (uint8_t *)dev->data); @@ -477,7 +477,7 @@ hdc_callback(void *priv) } if (dev->rba >= drive->sectors) - fatal("Write past end of drive\n"); + fatal("ESDI: write past end of drive\n"); hdd_active(drive->hdd_num, dev->cmd_dev == ATTN_DEVICE_0 ? 0 : 1); @@ -549,14 +549,15 @@ hdc_callback(void *priv) } if ((dev->status & STATUS_IRQ) || dev->irq_in_progress) - fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress); + fatal("ESDI: IRQ in progress %02x %i\n", + dev->status, dev->irq_in_progress); dev->status_len = 9; dev->status_data[0] = CMD_GET_DEV_STATUS | STATUS_LEN(9) | STATUS_DEVICE_HOST_ADAPTER; - dev->status_data[1] = 0x0000; /*Error bits*/ - dev->status_data[2] = 0x1900; /*Device status*/ - dev->status_data[3] = 0; /*ESDI Standard Status*/ - dev->status_data[4] = 0; /*ESDI Vendor Unique Status*/ + dev->status_data[1] = 0x0000; /* Error bits */ + dev->status_data[2] = 0x1900; /* Device status */ + dev->status_data[3] = 0; /* ESDI Standard Status */ + dev->status_data[4] = 0; /* ESDI Vendor Unique Status */ dev->status_data[5] = 0; dev->status_data[6] = 0; dev->status_data[7] = 0; @@ -577,7 +578,8 @@ hdc_callback(void *priv) } if ((dev->status & STATUS_IRQ) || dev->irq_in_progress) - fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress); + fatal("ESDI: IRQ in progress %02x %i\n", + dev->status, dev->irq_in_progress); dev->status_len = 6; dev->status_data[0] = CMD_GET_DEV_CONFIG | STATUS_LEN(6) | STATUS_DEVICE_HOST_ADAPTER; @@ -602,7 +604,8 @@ hdc_callback(void *priv) ESDI_ADAPTER_ONLY(); if ((dev->status & STATUS_IRQ) || dev->irq_in_progress) - fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress); + fatal("ESDI: IRQ in progress %02x %i\n", + dev->status, dev->irq_in_progress); dev->status_len = 5; dev->status_data[0] = CMD_GET_POS_INFO | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER; @@ -625,7 +628,7 @@ hdc_callback(void *priv) dev->sector_pos = 0; dev->sector_count = dev->cmd_data[1]; if (dev->sector_count > 256) - fatal("Write sector buffer count %04x\n", dev->cmd_data[1]); + fatal("ESDI: write sector buffer count %04x\n", dev->cmd_data[1]); dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ; dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY; @@ -679,7 +682,7 @@ hdc_callback(void *priv) dev->sector_pos = 0; dev->sector_count = dev->cmd_data[1]; if (dev->sector_count > 256) - fatal("Read sector buffer count %04x\n", dev->cmd_data[1]); + fatal("ESDI: read sector buffer count %04x\n", dev->cmd_data[1]); dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ; dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY; @@ -731,7 +734,8 @@ hdc_callback(void *priv) case 0x12: ESDI_ADAPTER_ONLY(); if ((dev->status & STATUS_IRQ) || dev->irq_in_progress) - fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress); + fatal("ESDI: IRQ in progress %02x %i\n", + dev->status, dev->irq_in_progress); dev->status_len = 2; dev->status_data[0] = 0x12 | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER; @@ -744,7 +748,8 @@ hdc_callback(void *priv) break; default: - DEBUG("BAD COMMAND %02x %i\n", dev->command, dev->cmd_dev); + DEBUG("ESDI: BAD COMMAND %02x %i\n", + dev->command, dev->cmd_dev); } } @@ -755,7 +760,7 @@ hdc_read(uint16_t port, void *priv) hdc_t *dev = (hdc_t *)priv; uint8_t ret = 0xff; - switch (port & 7) { + switch (port - dev->base) { case 2: /*Basic status register*/ ret = dev->status; break; @@ -766,7 +771,7 @@ hdc_read(uint16_t port, void *priv) break; default: - DEBUG("esdi_read port=%04x\n", port); + DEBUG("ESDI: read invalid port %04x\n", port); } DBGLOG(2, "ESDI: rd(%04x) = %02x\n", port & 7, ret); @@ -782,8 +787,8 @@ hdc_write(uint16_t port, uint8_t val, void *priv) DBGLOG(2, "ESDI: wr(%04x, %02x)\n", port & 7, val); - switch (port & 7) { - case 2: /*Basic control register*/ + switch (port - dev->base) { + case 2: /*Basic control register*/ if ((dev->basic_ctrl & CTRL_RESET) && !(val & CTRL_RESET)) { dev->in_reset = 1; dev->callback = ESDI_TIME * 50LL; @@ -792,16 +797,16 @@ hdc_write(uint16_t port, uint8_t val, void *priv) dev->basic_ctrl = val; if (! (dev->basic_ctrl & CTRL_IRQ_ENA)) - picintc(1 << 14); + picintc(1 << dev->irq); break; - case 3: /*Attention register*/ + case 3: /*Attention register*/ switch (val & ATTN_DEVICE_SEL) { case ATTN_HOST_ADAPTER: switch (val & ATTN_REQ_MASK) { case ATTN_CMD_REQ: if (dev->cmd_req_in_progress) - fatal("Try to start command on in_progress adapter\n"); + fatal("ESDI: try to start command on in_progress adapter\n"); dev->cmd_req_in_progress = 1; dev->cmd_dev = ATTN_HOST_ADAPTER; dev->status |= STATUS_BUSY; @@ -822,7 +827,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv) break; default: - DEBUG("Bad attention request %02x\n", val); + DEBUG("ESDI: bad attention request %02x\n", val); } break; @@ -830,7 +835,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv) switch (val & ATTN_REQ_MASK) { case ATTN_CMD_REQ: if (dev->cmd_req_in_progress) - fatal("Try to start command on in_progress device0\n"); + fatal("ESDI: try to start command on in_progress device0\n"); dev->cmd_req_in_progress = 1; dev->cmd_dev = ATTN_DEVICE_0; dev->status |= STATUS_BUSY; @@ -845,7 +850,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv) break; default: - DEBUG("Bad attention request %02x\n", val); + DEBUG("ESDI: bad attention request %02x\n", val); } break; @@ -853,7 +858,7 @@ hdc_write(uint16_t port, uint8_t val, void *priv) switch (val & ATTN_REQ_MASK) { case ATTN_CMD_REQ: if (dev->cmd_req_in_progress) - fatal("Try to start command on in_progress device0\n"); + fatal("ESDI: try to start command on in_progress device0\n"); dev->cmd_req_in_progress = 1; dev->cmd_dev = ATTN_DEVICE_1; dev->status |= STATUS_BUSY; @@ -867,17 +872,17 @@ hdc_write(uint16_t port, uint8_t val, void *priv) break; default: - DEBUG("Bad attention request %02x\n", val); + DEBUG("ESDI: bad attention request %02x\n", val); } break; default: - DEBUG("Attention to unknown device %02x\n", val); + DEBUG("ESDI: attention to unknown device %02x\n", val); } break; default: - DEBUG("esdi_write port=%04x val=%02x\n", port, val); + DEBUG("ESDI: write to invalid port %04x (val=%02x)\n", port, val); } } @@ -888,7 +893,7 @@ hdc_readw(uint16_t port, void *priv) hdc_t *dev = (hdc_t *)priv; uint16_t ret = 0xffff; - switch (port & 7) { + switch (port - dev->base) { case 0: /*Status Interface Register*/ if (dev->status_pos >= dev->status_len) return(0); @@ -900,7 +905,7 @@ hdc_readw(uint16_t port, void *priv) break; default: - DEBUG("esdi_readw port=%04x\n", port); + DEBUG("ESDI: readw from invalid port %04x\n", port); } return(ret); @@ -914,7 +919,7 @@ hdc_writew(uint16_t port, uint16_t val, void *priv) DBGLOG(2, "ESDI: wrw(%04x, %04x)\n", port & 7, val); - switch (port & 7) { + switch (port - dev->base) { case 0: /*Command Interface Register*/ if (dev->cmd_pos >= 4) fatal("CIR pos 4\n"); @@ -935,7 +940,7 @@ hdc_writew(uint16_t port, uint16_t val, void *priv) break; default: - DEBUG("esdi_writew port=%04x val=%04x\n", port, val); + DEBUG("ESDI: writew to invalid port %04x (val=%04x)\n", port, val); } } @@ -946,7 +951,7 @@ hdc_mca_read(int port, void *priv) hdc_t *dev = (hdc_t *)priv; uint8_t ret = dev->pos_regs[port & 7]; - DBGLOG(1, "ESDI: mcard(%04x) = %02x\n", port, ret); + DBGLOG(1, "ESDI: mca_read(%04x) = %02x\n", port, ret); return(ret); } @@ -957,7 +962,7 @@ hdc_mca_write(int port, uint8_t val, void *priv) { hdc_t *dev = (hdc_t *)priv; - DBGLOG(1, "ESDI: mcawr(%04x, %02x) pos[2]=%02x pos[3]=%02x\n", + DBGLOG(1, "ESDI: mca_write(%04x, %02x) pos[2]=%02x pos[3]=%02x\n", port, val, dev->pos_regs[2], dev->pos_regs[3]); if (port < 0x102) return; @@ -965,10 +970,22 @@ hdc_mca_write(int port, uint8_t val, void *priv) /* Save the new value. */ dev->pos_regs[port & 7] = val; - io_removehandler(ESDI_IOADDR_PRI, 8, + io_removehandler(dev->base, 8, hdc_read,hdc_readw,NULL, hdc_write,hdc_writew,NULL, dev); + mem_map_disable(&dev->bios_rom.mapping); + /* Extract the new I/O base. */ + switch(dev->pos_regs[2] & 0x02) { + case 0x00: /* PRIMARY [0]=XXxx xx0X 0x3510 */ + dev->base = ESDI_IOADDR_PRI; + break; + + case 0x02: /* SECONDARY [0]=XXxx xx1X 0x3518 */ + dev->base = ESDI_IOADDR_SEC; + break; + } + switch(dev->pos_regs[2] & 0x3c) { case 0x14: /* DMA 5 [0]=XX01 01XX */ dev->dma = 5; @@ -999,22 +1016,59 @@ hdc_mca_write(int port, uint8_t val, void *priv) break; } + /* Extract the new BIOS address. */ + if (! (dev->pos_regs[3] & 0x08)) switch(dev->pos_regs[3] & 0x0f) { + case 0: /* ROM C000 [1]=XXXX 0000 */ + dev->bios = 0xC0000; + break; + + case 1: /* ROM C400 [1]=XXXX 0001 */ + dev->bios = 0xC4000; + break; + + case 2: /* ROM C800 [1]=XXXX 0010 */ + dev->bios = 0xC8000; + break; + + case 3: /* ROM CC00 [1]=XXXX 0011 */ + dev->bios = 0xCC000; + break; + + case 4: /* ROM D000 [1]=XXXX 0100 */ + dev->bios = 0xD0000; + break; + + case 5: /* ROM D400 [1]=XXXX 0101 */ + dev->bios = 0xD4000; + break; + + case 6: /* ROM D800 [1]=XXXX 0110 */ + dev->bios = 0xD8000; + break; + + case 7: /* ROM DC00 [1]=XXXX 0111 */ + dev->bios = 0xDC000; + break; + } else { + /* BIOS ROM disabled. */ + dev->bios = 0x000000; + } + if (dev->pos_regs[2] & 0x01) { /* Card enabled; register (new) I/O handler. */ - io_sethandler(ESDI_IOADDR_PRI, 8, + io_sethandler(dev->base, 8, hdc_read, hdc_readw, NULL, hdc_write, hdc_writew, NULL, dev); /* Enable or disable the BIOS ROM. */ - if (!(dev->pos_regs[3] & 0x08)) { - dev->bios = ((dev->pos_regs[3] & 7) * 0x4000) + 0xc0000; + if (!(dev->pos_regs[3] & 0x08) && dev->bios != 0x000000) { mem_map_enable(&dev->bios_rom.mapping); mem_map_set_addr(&dev->bios_rom.mapping, dev->bios, 0x4000); } /* Say hello. */ - INFO("ESDI: I/O=%04x, IRQ=%d, DMA=%d, BIOS @%05X\n", - ESDI_IOADDR_PRI, 14, dev->dma, dev->bios); + INFO("ESDI: I/O=%04x, IRQ=%i, DMA=%i, BIOS @%05X\n", + dev->base, dev->irq, dev->dma, dev->bios); } } @@ -1029,6 +1083,9 @@ esdi_init(const device_t *info) dev = (hdc_t *)mem_alloc(sizeof(hdc_t)); memset(dev, 0x00, sizeof(hdc_t)); + /* This is hardwired. */ + dev->irq = ESDI_IRQCHAN; + /* Mark as unconfigured. */ dev->irq_status = 0xff; @@ -1041,7 +1098,8 @@ esdi_init(const device_t *info) c = 0; for (i = 0; i < HDD_NUM; i++) { - if ((hdd[i].bus == HDD_BUS_ESDI) && (hdd[i].id.esdi_channel < ESDI_NUM)) { + if ((hdd[i].bus == HDD_BUS_ESDI) && + (hdd[i].id.esdi_channel < ESDI_NUM)) { /* This is an ESDI drive. */ drive = &dev->drives[hdd[i].id.esdi_channel]; @@ -1068,11 +1126,9 @@ esdi_init(const device_t *info) if (++c >= ESDI_NUM) break; } - /* Set the MCA ID for this controller, 0xFFDD. */ + /* Set the MCA ID for this controller and enable MCA. */ dev->pos_regs[0] = 0xff; dev->pos_regs[1] = 0xdd; - - /* Enable the device. */ mca_add(hdc_mca_read, hdc_mca_write, dev); /* Mark for a reset. */ diff --git a/src/devices/video/vid_ati_mach64.c b/src/devices/video/vid_ati_mach64.c index a6fd09d..e9e45d0 100644 --- a/src/devices/video/vid_ati_mach64.c +++ b/src/devices/video/vid_ati_mach64.c @@ -8,7 +8,7 @@ * * ATi Mach64 graphics card emulation. * - * Version: @(#)vid_ati_mach64.c 1.0.13 2018/10/05 + * Version: @(#)vid_ati_mach64.c 1.0.14 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -3496,7 +3496,7 @@ static const device_config_t mach64vt2_config[] = static const video_timings_t mach64gx_isa_timing = {VID_ISA,3,3,6,5,5,10}; const device_t mach64gx_isa_device = { - "ATI Mach64GX ISA", + "ATI Mach64GX", DEVICE_AT | DEVICE_ISA, 0, mach64gx_init, mach64_close, NULL, @@ -3509,7 +3509,7 @@ const device_t mach64gx_isa_device = { static const video_timings_t mach64gx_vlb_timing = {VID_BUS,2,2,1,20,20,21}; const device_t mach64gx_vlb_device = { - "ATI Mach64GX VLB", + "ATI Mach64GX", DEVICE_VLB, 0, mach64gx_init, mach64_close, NULL, @@ -3522,7 +3522,7 @@ const device_t mach64gx_vlb_device = { static const video_timings_t mach64gx_pci_timing = {VID_BUS,2,2,1,20,20,21}; const device_t mach64gx_pci_device = { - "ATI Mach64GX PCI", + "ATI Mach64GX", DEVICE_PCI, 0, mach64gx_init, mach64_close, NULL, diff --git a/src/devices/video/vid_cl54xx.c b/src/devices/video/vid_cl54xx.c index 34946fc..1e239c1 100644 --- a/src/devices/video/vid_cl54xx.c +++ b/src/devices/video/vid_cl54xx.c @@ -9,7 +9,7 @@ * Emulation of select Cirrus Logic cards (CL-GD 5428, * CL-GD 5429, 5430, 5434 and 5436 are supported). * - * Version: @(#)vid_cl54xx.c 1.0.19 2018/10/05 + * Version: @(#)vid_cl54xx.c 1.0.20 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -2298,7 +2298,10 @@ gd54xx_init(const device_t *info) gd54xx->pci_regs[0x33] = 0x00; svga->crtc[0x27] = id; - + + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return gd54xx; } @@ -2466,9 +2469,13 @@ static const device_config_t gd5434_config[] = } }; -const device_t gd5426_vlb_device = -{ - "Cirrus Logic CL-GD 5426 (VLB)", +static const video_timings_t cl_gd_isa_timing = {VID_ISA,3,3,6,8,8,12}; +static const video_timings_t cl_gd_vlb_timing = {VID_BUS,4,4,8,10,10,20}; +static const video_timings_t cl_gd_pci_timing = {VID_BUS,4,4,8,10,10,20}; + + +const device_t gd5426_vlb_device = { + "Cirrus Logic GD-5426", DEVICE_VLB, CIRRUS_ID_CLGD5426, gd54xx_init, @@ -2477,13 +2484,12 @@ const device_t gd5426_vlb_device = gd5426_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_vlb_timing, gd5428_config }; -const device_t gd5428_isa_device = -{ - "Cirrus Logic CL-GD 5428 (ISA)", +const device_t gd5428_isa_device = { + "Cirrus Logic GD-5428", DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5428, gd54xx_init, @@ -2492,13 +2498,12 @@ const device_t gd5428_isa_device = gd5428_isa_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_isa_timing, gd5428_config }; -const device_t gd5428_vlb_device = -{ - "Cirrus Logic CL-GD 5428 (VLB)", +const device_t gd5428_vlb_device = { + "Cirrus Logic GD-5428", DEVICE_VLB, CIRRUS_ID_CLGD5428, gd54xx_init, @@ -2507,13 +2512,12 @@ const device_t gd5428_vlb_device = gd5428_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_vlb_timing, gd5428_config }; -const device_t gd5429_isa_device = -{ - "Cirrus Logic CL-GD 5429 (ISA)", +const device_t gd5429_isa_device = { + "Cirrus Logic GD-5429", DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5429, gd54xx_init, @@ -2522,13 +2526,12 @@ const device_t gd5429_isa_device = gd5429_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_isa_timing, gd5428_config }; -const device_t gd5429_vlb_device = -{ - "Cirrus Logic CL-GD 5429 (VLB)", +const device_t gd5429_vlb_device = { + "Cirrus Logic GD-5429", DEVICE_VLB, CIRRUS_ID_CLGD5429, gd54xx_init, @@ -2537,13 +2540,12 @@ const device_t gd5429_vlb_device = gd5429_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_vlb_timing, gd5428_config }; -const device_t gd5430_vlb_device = -{ - "Cirrus Logic CL-GD 5430 (VLB)", +const device_t gd5430_vlb_device = { + "Cirrus Logic GD-5430", DEVICE_VLB, CIRRUS_ID_CLGD5430, gd54xx_init, @@ -2552,13 +2554,12 @@ const device_t gd5430_vlb_device = gd5430_vlb_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_vlb_timing, gd5428_config }; -const device_t gd5430_pci_device = -{ - "Cirrus Logic CL-GD 5430 (PCI)", +const device_t gd5430_pci_device = { + "Cirrus Logic GD-5430", DEVICE_PCI, CIRRUS_ID_CLGD5430, gd54xx_init, @@ -2567,13 +2568,12 @@ const device_t gd5430_pci_device = gd5430_pci_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5428_config }; -const device_t gd5434_isa_device = -{ - "Cirrus Logic CL-GD 5434 (ISA)", +const device_t gd5434_isa_device = { + "Cirrus Logic GD-5434", DEVICE_AT | DEVICE_ISA, CIRRUS_ID_CLGD5434, gd54xx_init, @@ -2582,13 +2582,12 @@ const device_t gd5434_isa_device = gd5434_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_isa_timing, gd5434_config }; -const device_t gd5434_vlb_device = -{ - "Cirrus Logic CL-GD 5434 (VLB)", +const device_t gd5434_vlb_device = { + "Cirrus Logic GD-5434", DEVICE_VLB, CIRRUS_ID_CLGD5434, gd54xx_init, @@ -2597,13 +2596,12 @@ const device_t gd5434_vlb_device = gd5434_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_vlb_timing, gd5434_config }; -const device_t gd5434_pci_device = -{ - "Cirrus Logic CL-GD 5434 (PCI)", +const device_t gd5434_pci_device = { + "Cirrus Logic GD-5434", DEVICE_PCI, CIRRUS_ID_CLGD5434, gd54xx_init, @@ -2612,13 +2610,12 @@ const device_t gd5434_pci_device = gd5434_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5434_config }; -const device_t gd5436_pci_device = -{ - "Cirrus Logic CL-GD 5436 (PCI)", +const device_t gd5436_pci_device = { + "Cirrus Logic GD-5436", DEVICE_PCI, CIRRUS_ID_CLGD5436, gd54xx_init, @@ -2627,13 +2624,12 @@ const device_t gd5436_pci_device = gd5436_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5434_config }; -const device_t gd5440_onboard_pci_device = -{ - "Cirrus Logic CL-GD 5440 (On-Board PCI)", +const device_t gd5440_onboard_pci_device = { + "Onboard Cirrus Logic GD-5440", DEVICE_PCI, CIRRUS_ID_CLGD5440 | 0x600, gd54xx_init, @@ -2642,13 +2638,12 @@ const device_t gd5440_onboard_pci_device = NULL, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5440_onboard_config }; -const device_t gd5440_pci_device = -{ - "Cirrus Logic CL-GD 5440 (PCI)", +const device_t gd5440_pci_device = { + "Cirrus Logic GD-5440", DEVICE_PCI, CIRRUS_ID_CLGD5440 | 0x400, gd54xx_init, @@ -2657,13 +2652,12 @@ const device_t gd5440_pci_device = gd5440_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5428_config }; -const device_t gd5446_pci_device = -{ - "Cirrus Logic CL-GD 5446 (PCI)", +const device_t gd5446_pci_device = { + "Cirrus Logic GD-5446", DEVICE_PCI, CIRRUS_ID_CLGD5446, gd54xx_init, @@ -2672,13 +2666,12 @@ const device_t gd5446_pci_device = gd5446_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5434_config }; -const device_t gd5446_stb_pci_device = -{ - "STB Nitro 64V (PCI)", +const device_t gd5446_stb_pci_device = { + "STB Nitro 64V", DEVICE_PCI, CIRRUS_ID_CLGD5446 | 0x100, gd54xx_init, @@ -2687,13 +2680,12 @@ const device_t gd5446_stb_pci_device = gd5446_stb_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5434_config }; -const device_t gd5480_pci_device = -{ - "Cirrus Logic CL-GD 5480 (PCI)", +const device_t gd5480_pci_device = { + "Cirrus Logic GD-5480", DEVICE_PCI, CIRRUS_ID_CLGD5480, gd54xx_init, @@ -2702,6 +2694,6 @@ const device_t gd5480_pci_device = gd5480_available, gd54xx_speed_changed, gd54xx_force_redraw, - NULL, + &cl_gd_pci_timing, gd5434_config }; diff --git a/src/devices/video/vid_et4000.c b/src/devices/video/vid_et4000.c index f7cfeb9..e6182ba 100644 --- a/src/devices/video/vid_et4000.c +++ b/src/devices/video/vid_et4000.c @@ -8,7 +8,7 @@ * * Emulation of the Tseng Labs ET4000. * - * Version: @(#)vid_et4000.c 1.0.12 2018/10/05 + * Version: @(#)vid_et4000.c 1.0.13 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -538,6 +538,9 @@ et4000_init(const device_t *info) DEBUG("VIDEO: %s (vram=%dKB)\n", dev->name, dev->vram_size>>10); + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return(dev); } @@ -610,39 +613,43 @@ static const device_config_t et4000_config[] = } }; +static const video_timings_t et4000ax_isa_timing = {VID_ISA,3,3,6,5,5,10}; +static const video_timings_t et4000ax_mca_timing = {VID_MCA,4,5,10,5,5,10}; + + const device_t et4000_isa_device = { - "Tseng Labs ET4000AX (ISA)", + "Tseng Labs ET4000AX", DEVICE_ISA, 0, et4000_init, et4000_close, NULL, et4000_available, et4000_speed_changed, et4000_force_redraw, - NULL, + &et4000ax_isa_timing, et4000_config }; const device_t et4000_mca_device = { - "Tseng Labs ET4000AX (MCA)", + "Tseng Labs ET4000AX", DEVICE_MCA, 1, et4000_init, et4000_close, NULL, et4000_available, et4000_speed_changed, et4000_force_redraw, - NULL, + &et4000ax_mca_timing, et4000_config }; const device_t et4000k_isa_device = { - "Trigem Korean VGA (Tseng Labs ET4000AX Korean)", + "Tseng Labs ET4000AX (Korean)", DEVICE_ISA, 2, et4000_init, et4000_close, NULL, et4000k_available, et4000_speed_changed, et4000_force_redraw, - NULL, + &et4000ax_isa_timing, et4000_config }; @@ -654,6 +661,6 @@ const device_t et4000k_tg286_isa_device = { et4000k_available, et4000_speed_changed, et4000_force_redraw, - NULL, + &et4000ax_isa_timing, et4000_config }; diff --git a/src/devices/video/vid_et4000w32.c b/src/devices/video/vid_et4000w32.c index 37cd550..61c9efc 100644 --- a/src/devices/video/vid_et4000w32.c +++ b/src/devices/video/vid_et4000w32.c @@ -12,7 +12,7 @@ * * FIXME: Note the madness on line 1163, fix that somehow? --FvK * - * Version: @(#)vid_et4000w32.c 1.0.14 2018/10/05 + * Version: @(#)vid_et4000w32.c 1.0.15 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -1224,115 +1224,133 @@ static void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p) } } -static void *et4000w32p_init(const device_t *info) + +static void * +et4000w32p_init(const device_t *info) { - int vram_size; - et4000w32p_t *et4000 = (et4000w32p_t *)mem_alloc(sizeof(et4000w32p_t)); - memset(et4000, 0, sizeof(et4000w32p_t)); + int vram_size; + et4000w32p_t *et4000 = (et4000w32p_t *)mem_alloc(sizeof(et4000w32p_t)); + memset(et4000, 0, sizeof(et4000w32p_t)); + et4000->type = info->local; + et4000->pci = !!(info->flags & DEVICE_PCI); - vram_size = device_get_config_int("memory"); + vram_size = device_get_config_int("memory"); - et4000->interleaved = (vram_size == 2) ? 1 : 0; + et4000->interleaved = (vram_size == 2) ? 1 : 0; - svga_init(&et4000->svga, et4000, vram_size << 20, - et4000w32p_recalctimings, - et4000w32p_in, et4000w32p_out, - et4000w32p_hwcursor_draw, - NULL); + svga_init(&et4000->svga, et4000, vram_size << 20, + et4000w32p_recalctimings, + et4000w32p_in, et4000w32p_out, + et4000w32p_hwcursor_draw, + NULL); - et4000->svga.ramdac = device_add(&stg_ramdac_device); + et4000->svga.ramdac = device_add(&stg_ramdac_device); - et4000->vram_mask = (vram_size << 20) - 1; + et4000->vram_mask = (vram_size << 20) - 1; - et4000->type = info->local; + switch(et4000->type) { + case ET4000W32_CARDEX: + rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, + 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + et4000->svga.clock_gen = et4000->svga.ramdac; + et4000->svga.getclock = stg_getclock; + break; - switch(et4000->type) { - case ET4000W32_CARDEX: - rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, 0xc0000, 0x8000, 0x7fff, 0, - MEM_MAPPING_EXTERNAL); + case ET4000W32_DIAMOND: + rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, + 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); + et4000->svga.clock_gen = device_add(&icd2061_device); + et4000->svga.getclock = icd2061_getclock; + break; + } - et4000->svga.clock_gen = et4000->svga.ramdac; - et4000->svga.getclock = stg_getclock; - break; + if (info->flags & DEVICE_PCI) + mem_map_disable(&et4000->bios_rom.mapping); - case ET4000W32_DIAMOND: - rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, 0xc0000, 0x8000, 0x7fff, 0, - MEM_MAPPING_EXTERNAL); + mem_map_add(&et4000->linear_mapping, 0, 0, + svga_read_linear, svga_readw_linear, svga_readl_linear, + svga_write_linear, svga_writew_linear, svga_writel_linear, + NULL, 0, &et4000->svga); + mem_map_add(&et4000->mmu_mapping, 0, 0, + et4000w32p_mmu_read, NULL, NULL, + et4000w32p_mmu_write, NULL, NULL, NULL, 0, et4000); - et4000->svga.clock_gen = device_add(&icd2061_device); - et4000->svga.getclock = icd2061_getclock; - break; - } - et4000->pci = !!(info->flags & DEVICE_PCI); - if (info->flags & DEVICE_PCI) - mem_map_disable(&et4000->bios_rom.mapping); - - mem_map_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, 0, &et4000->svga); - mem_map_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL, 0, et4000); - - et4000w32p_io_set(et4000); + et4000w32p_io_set(et4000); - if (info->flags & DEVICE_PCI) - pci_add_card(PCI_ADD_VIDEO, et4000w32p_pci_read, et4000w32p_pci_write, et4000); + if (info->flags & DEVICE_PCI) + pci_add_card(PCI_ADD_VIDEO, + et4000w32p_pci_read, et4000w32p_pci_write, et4000); - /* Hardwired bits: 00000000 1xx0x0xx */ - /* R/W bits: xx xxxx */ - /* PCem bits: 111 */ - et4000->pci_regs[0x04] = 0x83; + /* Hardwired bits: 00000000 1xx0x0xx */ + /* R/W bits: xx xxxx */ + /* PCem bits: 111 */ + et4000->pci_regs[0x04] = 0x83; - et4000->pci_regs[0x10] = 0x00; - et4000->pci_regs[0x11] = 0x00; - et4000->pci_regs[0x12] = 0xff; - et4000->pci_regs[0x13] = 0xff; + et4000->pci_regs[0x10] = 0x00; + et4000->pci_regs[0x11] = 0x00; + et4000->pci_regs[0x12] = 0xff; + et4000->pci_regs[0x13] = 0xff; - et4000->pci_regs[0x30] = 0x00; - et4000->pci_regs[0x31] = 0x00; - et4000->pci_regs[0x32] = 0x00; - et4000->pci_regs[0x33] = 0xf0; + et4000->pci_regs[0x30] = 0x00; + et4000->pci_regs[0x31] = 0x00; + et4000->pci_regs[0x32] = 0x00; + et4000->pci_regs[0x33] = 0xf0; - et4000->wake_fifo_thread = thread_create_event(); - et4000->fifo_not_full_event = thread_create_event(); - et4000->fifo_thread = thread_create(fifo_thread, et4000); + et4000->wake_fifo_thread = thread_create_event(); + et4000->fifo_not_full_event = thread_create_event(); + et4000->fifo_thread = thread_create(fifo_thread, et4000); - return et4000; + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + + return et4000; } -static int et4000w32p_available(void) -{ - return rom_present(BIOS_ROM_PATH_DIAMOND); -} -static int et4000w32p_cardex_available(void) +static void +et4000w32p_close(void *p) { - return rom_present(BIOS_ROM_PATH_CARDEX); -} + et4000w32p_t *et4000 = (et4000w32p_t *)p; -static void et4000w32p_close(void *p) -{ - et4000w32p_t *et4000 = (et4000w32p_t *)p; - - svga_close(&et4000->svga); + svga_close(&et4000->svga); - thread_kill(et4000->fifo_thread); - thread_destroy_event(et4000->wake_fifo_thread); - thread_destroy_event(et4000->fifo_not_full_event); + thread_kill(et4000->fifo_thread); + thread_destroy_event(et4000->wake_fifo_thread); + thread_destroy_event(et4000->fifo_not_full_event); - free(et4000); + free(et4000); } -static void et4000w32p_speed_changed(void *p) + +static void +et4000w32p_speed_changed(void *p) { - et4000w32p_t *et4000 = (et4000w32p_t *)p; + et4000w32p_t *et4000 = (et4000w32p_t *)p; - svga_recalctimings(&et4000->svga); + svga_recalctimings(&et4000->svga); } -static void et4000w32p_force_redraw(void *p) -{ - et4000w32p_t *et4000w32p = (et4000w32p_t *)p; - et4000w32p->svga.fullchange = changeframecount; +static void +et4000w32p_force_redraw(void *p) +{ + et4000w32p_t *et4000w32p = (et4000w32p_t *)p; + + et4000w32p->svga.fullchange = changeframecount; +} + + +static int +et4000w32p_available(void) +{ + return rom_present(BIOS_ROM_PATH_DIAMOND); +} + +static int +et4000w32p_cardex_available(void) +{ + return rom_present(BIOS_ROM_PATH_CARDEX); } @@ -1357,6 +1375,10 @@ static const device_config_t et4000w32p_config[] = } }; +static const video_timings_t et4000w32p_pci_timing = {VID_BUS,4,4,4,10,10,10}; +static const video_timings_t et4000w32p_vlb_timing = {VID_BUS,4,4,4,10,10,10}; + + const device_t et4000w32p_cardex_vlb_device = { "Tseng Labs ET4000/w32p (Cardex)", DEVICE_VLB, @@ -1365,7 +1387,7 @@ const device_t et4000w32p_cardex_vlb_device = { et4000w32p_cardex_available, et4000w32p_speed_changed, et4000w32p_force_redraw, - NULL, + &et4000w32p_vlb_timing, et4000w32p_config }; @@ -1377,7 +1399,7 @@ const device_t et4000w32p_cardex_pci_device = { et4000w32p_cardex_available, et4000w32p_speed_changed, et4000w32p_force_redraw, - NULL, + &et4000w32p_pci_timing, et4000w32p_config }; @@ -1389,7 +1411,7 @@ const device_t et4000w32p_vlb_device = { et4000w32p_available, et4000w32p_speed_changed, et4000w32p_force_redraw, - NULL, + &et4000w32p_vlb_timing, et4000w32p_config }; @@ -1401,6 +1423,6 @@ const device_t et4000w32p_pci_device = { et4000w32p_available, et4000w32p_speed_changed, et4000w32p_force_redraw, - NULL, + &et4000w32p_pci_timing, et4000w32p_config }; diff --git a/src/devices/video/vid_paradise.c b/src/devices/video/vid_paradise.c index 8592009..325197f 100644 --- a/src/devices/video/vid_paradise.c +++ b/src/devices/video/vid_paradise.c @@ -13,7 +13,7 @@ * NOTE: The MegaPC video device should be moved to the MegaPC * machine file. * - * Version: @(#)vid_paradise.c 1.0.7 2018/09/22 + * Version: @(#)vid_paradise.c 1.0.8 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -56,23 +56,21 @@ #include "vid_svga_render.h" -enum type -{ - PVGA1A = 0, - WD90C11, - WD90C30 +enum type { + PVGA1A = 0, + WD90C11, + WD90C30 }; -typedef struct paradise_t -{ - svga_t svga; - - rom_t bios_rom; +typedef struct { + enum type type; - enum type type; + svga_t svga; - uint32_t read_bank[4], write_bank[4]; + rom_t bios_rom; + + uint32_t read_bank[4], write_bank[4]; } paradise_t; @@ -334,6 +332,9 @@ static void *paradise_pvga1a_init(const device_t *info, uint32_t memsize) paradise->type = PVGA1A; + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return paradise; } @@ -367,6 +368,9 @@ static void *paradise_wd90c11_init(const device_t *info) paradise->type = WD90C11; + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return paradise; } @@ -400,6 +404,9 @@ static void *paradise_wd90c30_init(const device_t *info, uint32_t memsize) paradise->type = WD90C11; + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return paradise; } @@ -516,31 +523,6 @@ static void paradise_force_redraw(void *p) } -const device_t paradise_pvga1a_pc2086_device = -{ - "Paradise PVGA1A (Amstrad PC2086)", - 0, - 0, - paradise_pvga1a_pc2086_init, paradise_close, NULL, - NULL, - paradise_speed_changed, - paradise_force_redraw, - NULL, - NULL -}; -const device_t paradise_pvga1a_pc3086_device = -{ - "Paradise PVGA1A (Amstrad PC3086)", - 0, - 0, - paradise_pvga1a_pc3086_init, paradise_close, NULL, - NULL, - paradise_speed_changed, - paradise_force_redraw, - NULL, - NULL -}; - static const device_config_t paradise_pvga1a_config[] = { { @@ -565,43 +547,74 @@ static const device_config_t paradise_pvga1a_config[] = } }; -const device_t paradise_pvga1a_device = -{ - "Paradise PVGA1A", - DEVICE_ISA, - 0, - paradise_pvga1a_standalone_init, paradise_close, NULL, - paradise_pvga1a_standalone_available, - paradise_speed_changed, - paradise_force_redraw, - NULL, - paradise_pvga1a_config +static const video_timings_t pvga1a_timing = {VID_ISA,8,16,32,8,16,32}; + + +const device_t paradise_pvga1a_device = { + "Paradise PVGA1A", + DEVICE_ISA, + 0, + paradise_pvga1a_standalone_init, paradise_close, NULL, + paradise_pvga1a_standalone_available, + paradise_speed_changed, + paradise_force_redraw, + &pvga1a_timing, + paradise_pvga1a_config }; -const device_t paradise_wd90c11_megapc_device = -{ - "Paradise WD90C11 (Amstrad MegaPC)", - 0, - 0, - paradise_wd90c11_megapc_init, paradise_close, NULL, - NULL, - paradise_speed_changed, - paradise_force_redraw, - NULL, - NULL + +const device_t paradise_pvga1a_pc2086_device = { + "Paradise PVGA1A (Amstrad PC2086)", + 0, + 0, + paradise_pvga1a_pc2086_init, paradise_close, NULL, + NULL, + paradise_speed_changed, + paradise_force_redraw, + &pvga1a_timing, + NULL }; -const device_t paradise_wd90c11_device = -{ - "Paradise WD90C11-LR", - DEVICE_ISA, - 0, - paradise_wd90c11_standalone_init, paradise_close, NULL, - paradise_wd90c11_standalone_available, - paradise_speed_changed, - paradise_force_redraw, - NULL, - NULL + +const device_t paradise_pvga1a_pc3086_device = { + "Paradise PVGA1A (Amstrad PC3086)", + 0, + 0, + paradise_pvga1a_pc3086_init, paradise_close, NULL, + NULL, + paradise_speed_changed, + paradise_force_redraw, + &pvga1a_timing, + NULL }; + +static const video_timings_t wd90c11_timing = {VID_ISA,8,16,32,8,16,32}; + + +const device_t paradise_wd90c11_device = { + "Paradise WD90C11-LR", + DEVICE_ISA, + 0, + paradise_wd90c11_standalone_init, paradise_close, NULL, + paradise_wd90c11_standalone_available, + paradise_speed_changed, + paradise_force_redraw, + &wd90c11_timing, + NULL +}; + +const device_t paradise_wd90c11_megapc_device = { + "Paradise WD90C11 (Amstrad MegaPC)", + 0, + 0, + paradise_wd90c11_megapc_init, paradise_close, NULL, + NULL, + paradise_speed_changed, + paradise_force_redraw, + &wd90c11_timing, + NULL +}; + + static const device_config_t paradise_wd90c30_config[] = { { @@ -623,15 +636,17 @@ static const device_config_t paradise_wd90c30_config[] = } }; -const device_t paradise_wd90c30_device = -{ - "Paradise WD90C30-LR", - DEVICE_ISA, - 0, - paradise_wd90c30_standalone_init, paradise_close, NULL, - paradise_wd90c30_standalone_available, - paradise_speed_changed, - paradise_force_redraw, - NULL, - paradise_wd90c30_config +static const video_timings_t wd90c30_timing = {VID_ISA,6,8,16,6,8,16}; + + +const device_t paradise_wd90c30_device = { + "Paradise WD90C30-LR", + DEVICE_ISA, + 0, + paradise_wd90c30_standalone_init, paradise_close, NULL, + paradise_wd90c30_standalone_available, + paradise_speed_changed, + paradise_force_redraw, + &wd90c30_timing, + paradise_wd90c30_config }; diff --git a/src/devices/video/vid_s3.c b/src/devices/video/vid_s3.c index 5a2d1c7..4d1a095 100644 --- a/src/devices/video/vid_s3.c +++ b/src/devices/video/vid_s3.c @@ -10,7 +10,7 @@ * * NOTE: ROM images need more/better organization per chipset. * - * Version: @(#)vid_s3.c 1.0.12 2018/10/05 + * Version: @(#)vid_s3.c 1.0.13 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -3247,7 +3247,7 @@ const device_t s3_9fx_vlb_device = { }; const device_t s3_9fx_pci_device = { - "Number 9 9FX (S3 Trio64) PCI", + "Number 9 9FX (S3 Trio64)", DEVICE_PCI, S3_NUMBER9_9FX, s3_init, s3_close, NULL, @@ -3295,7 +3295,7 @@ const device_t s3_phoenix_trio64_vlb_device = { }; const device_t s3_phoenix_trio64_pci_device = { - "Phoenix S3 Trio64 PCI", + "Phoenix S3 Trio64", DEVICE_PCI, S3_PHOENIX_TRIO64, s3_init, s3_close, NULL, @@ -3307,7 +3307,7 @@ const device_t s3_phoenix_trio64_pci_device = { }; const device_t s3_phoenix_trio64_onboard_pci_device = { - "Phoenix S3 Trio64 On-Board", + "Onboard Phoenix S3 Trio64", DEVICE_PCI, S3_PHOENIX_TRIO64_ONBOARD, s3_init, s3_close, NULL, @@ -3354,7 +3354,7 @@ const device_t s3_diamond_stealth64_vlb_device = { }; const device_t s3_diamond_stealth64_pci_device = { - "S3 Trio64 (Diamond Stealth64 DRAM) PCI", + "S3 Trio64 (Diamond Stealth64 DRAM)", DEVICE_PCI, S3_DIAMOND_STEALTH64_764, s3_init, s3_close, NULL, diff --git a/src/devices/video/vid_s3_virge.c b/src/devices/video/vid_s3_virge.c index 4ebdc34..711d74e 100644 --- a/src/devices/video/vid_s3_virge.c +++ b/src/devices/video/vid_s3_virge.c @@ -8,7 +8,7 @@ * * S3 ViRGE emulation. * - * Version: @(#)vid_s3_virge.c 1.0.12 2018/09/22 + * Version: @(#)vid_s3_virge.c 1.0.13 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -3997,6 +3997,9 @@ s3_virge_init(const device_t *info) virge->fifo_not_full_event = thread_create_event(); virge->fifo_thread = thread_create(fifo_thread, virge); + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return virge; } @@ -4021,35 +4024,17 @@ s3_virge_close(void *p) } -static int s3_virge_available(void) -{ - return rom_present(ROM_DIAMOND_STEALTH3D_2000); -} - -static int s3_virge_988_available(void) -{ - return rom_present(ROM_DIAMOND_STEALTH3D_3000); -} - -static int s3_virge_375_1_available(void) -{ - return rom_present(ROM_VIRGE_DX); -} - -static int s3_virge_375_4_available(void) -{ - return rom_present(ROM_VIRGE_DX_VBE20); -} - - -static void s3_virge_speed_changed(void *p) +static void +s3_virge_speed_changed(void *p) { virge_t *virge = (virge_t *)p; svga_recalctimings(&virge->svga); } -static void s3_virge_force_redraw(void *p) + +static void +s3_virge_force_redraw(void *p) { virge_t *virge = (virge_t *)p; @@ -4057,6 +4042,31 @@ static void s3_virge_force_redraw(void *p) } +static int +s3_virge_available(void) +{ + return rom_present(ROM_DIAMOND_STEALTH3D_2000); +} + +static int +s3_virge_988_available(void) +{ + return rom_present(ROM_DIAMOND_STEALTH3D_3000); +} + +static int +s3_virge_375_1_available(void) +{ + return rom_present(ROM_VIRGE_DX); +} + +static int +s3_virge_375_4_available(void) +{ + return rom_present(ROM_VIRGE_DX_VBE20); +} + + static const device_config_t s3_virge_config[] = { { @@ -4084,6 +4094,9 @@ static const device_config_t s3_virge_config[] = } }; +static const video_timings_t virge375_vlb_timing = {VID_BUS,2,2,3,28,28,45}; +static const video_timings_t virge375_pci_timing = {VID_BUS,2,2,3,28,28,45}; + const device_t s3_virge_vlb_device = { "Diamond Stealth 3D 2000 (S3 ViRGE)", @@ -4093,7 +4106,7 @@ const device_t s3_virge_vlb_device = { s3_virge_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_vlb_timing, s3_virge_config }; @@ -4105,7 +4118,7 @@ const device_t s3_virge_pci_device = { s3_virge_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_pci_timing, s3_virge_config }; @@ -4117,7 +4130,7 @@ const device_t s3_virge_988_vlb_device = { s3_virge_988_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_vlb_timing, s3_virge_config }; @@ -4129,7 +4142,7 @@ const device_t s3_virge_988_pci_device = { s3_virge_988_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_pci_timing, s3_virge_config }; @@ -4141,7 +4154,7 @@ const device_t s3_virge_375_vlb_device = { s3_virge_375_1_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_vlb_timing, s3_virge_config }; @@ -4153,7 +4166,7 @@ const device_t s3_virge_375_pci_device = { s3_virge_375_1_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_pci_timing, s3_virge_config }; @@ -4165,7 +4178,7 @@ const device_t s3_virge_375_4_vlb_device = { s3_virge_375_4_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_vlb_timing, s3_virge_config }; @@ -4177,6 +4190,6 @@ const device_t s3_virge_375_4_pci_device = { s3_virge_375_4_available, s3_virge_speed_changed, s3_virge_force_redraw, - NULL, + &virge375_pci_timing, s3_virge_config }; diff --git a/src/devices/video/vid_tgui9440.c b/src/devices/video/vid_tgui9440.c index 5bc1719..8a87024 100644 --- a/src/devices/video/vid_tgui9440.c +++ b/src/devices/video/vid_tgui9440.c @@ -47,7 +47,7 @@ * access size or host data has any affect, but the Windows 3.1 * driver always reads bytes and write words of 0xffff. * - * Version: @(#)vid_tgui9440.c 1.0.9 2018/10/05 + * Version: @(#)vid_tgui9440.c 1.0.10 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -1807,7 +1807,7 @@ const device_t tgui9400cxi_device = { }; const device_t tgui9440_vlb_device = { - "Trident TGUI 9440 VLB", + "Trident TGUI 9440", DEVICE_VLB, TGUI_9440, tgui_init, tgui_close, NULL, @@ -1819,7 +1819,7 @@ const device_t tgui9440_vlb_device = { }; const device_t tgui9440_pci_device = { - "Trident TGUI 9440 PCI", + "Trident TGUI 9440", DEVICE_PCI, TGUI_9440, tgui_init, tgui_close, NULL, diff --git a/src/devices/video/vid_ti_cf62011.c b/src/devices/video/vid_ti_cf62011.c index 4167bb0..42a59bb 100644 --- a/src/devices/video/vid_ti_cf62011.c +++ b/src/devices/video/vid_ti_cf62011.c @@ -42,7 +42,7 @@ * which are the same as the XGA. It supports up to 1MB of VRAM, * but we lock it down to 512K. The PS/1 2122 had 256K. * - * Version: @(#)vid_ti_cf62011.c 1.0.6 2018/10/05 + * Version: @(#)vid_ti_cf62011.c 1.0.7 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -99,6 +99,9 @@ typedef struct { } tivga_t; +static const video_timings_t ti_cf62011_timing = {VID_ISA,8,16,32,8,16,32}; + + static void vid_out(uint16_t addr, uint8_t val, void *priv) { @@ -274,6 +277,9 @@ vid_init(const device_t *info) ti->svga.bpp = 8; ti->svga.miscout = 1; + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + return(ti); } @@ -312,7 +318,7 @@ const device_t ti_cf62011_device = { NULL, vid_speed_changed, vid_force_redraw, - NULL, + &ti_cf62011_timing, vid_config }; #endif @@ -326,6 +332,6 @@ const device_t ibm_ps1_2121_device = { NULL, vid_speed_changed, vid_force_redraw, - NULL, + &ti_cf62011_timing, NULL }; diff --git a/src/devices/video/vid_tvga.c b/src/devices/video/vid_tvga.c index 9df207c..c94f4cc 100644 --- a/src/devices/video/vid_tvga.c +++ b/src/devices/video/vid_tvga.c @@ -8,7 +8,7 @@ * * Trident TVGA (8900D) emulation. * - * Version: @(#)vid_tvga.c 1.0.8 2018/10/05 + * Version: @(#)vid_tvga.c 1.0.9 2018/10/08 * * Authors: Fred N. van Kempen, * Miran Grca, @@ -91,322 +91,342 @@ static void tvga_recalcbanking(tvga_t *tvga); static void tvga_out(uint16_t addr, uint8_t val, void *priv) { - tvga_t *tvga = (tvga_t *)priv; - svga_t *svga = &tvga->svga; + tvga_t *tvga = (tvga_t *)priv; + svga_t *svga = &tvga->svga; + uint8_t old; - uint8_t old; + if (((addr&0xfff0) == 0x3d0 || (addr&0xfff0) == 0x3b0) && + !(svga->miscout & 1)) addr ^= 0x60; - if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1)) addr ^= 0x60; + switch (addr) { + case 0x3c5: + switch (svga->seqaddr & 0x0f) { + case 0x0b: + tvga->oldmode = 1; + break; - switch (addr) - { - case 0x3C5: - switch (svga->seqaddr & 0xf) - { - case 0xB: - tvga->oldmode=1; - break; - case 0xC: - if (svga->seqregs[0xe] & 0x80) - svga->seqregs[0xc] = val; - break; - case 0xd: - if (tvga->oldmode) - tvga->oldctrl2 = val; - else - { - tvga->newctrl2 = val; - svga_recalctimings(svga); - } - break; - case 0xE: - if (tvga->oldmode) - tvga->oldctrl1 = val; - else - { - svga->seqregs[0xe] = val ^ 2; - tvga->tvga_3d8 = svga->seqregs[0xe] & 0xf; - tvga_recalcbanking(tvga); - } - return; - } - break; + case 0x0c: + if (svga->seqregs[0xe] & 0x80) + svga->seqregs[0xc] = val; + break; - case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - tkd8001_ramdac_out(addr, val, svga->ramdac, svga); - return; + case 0x0d: + if (tvga->oldmode) + tvga->oldctrl2 = val; + else { + tvga->newctrl2 = val; + svga_recalctimings(svga); + } + break; - case 0x3CF: - switch (svga->gdcaddr & 15) - { - case 0xE: - svga->gdcreg[0xe] = val ^ 2; - tvga->tvga_3d9 = svga->gdcreg[0xe] & 0xf; - tvga_recalcbanking(tvga); - break; - case 0xF: - svga->gdcreg[0xf] = val; - tvga_recalcbanking(tvga); - break; - } - break; - case 0x3D4: + case 0x0e: + if (tvga->oldmode) + tvga->oldctrl1 = val; + else { + svga->seqregs[0xe] = val ^ 2; + tvga->tvga_3d8 = svga->seqregs[0xe] & 0xf; + tvga_recalcbanking(tvga); + } + return; + } + break; + + case 0x3c6: + case 0x3c7: + case 0x3c8: + case 0x3c9: + tkd8001_ramdac_out(addr, val, svga->ramdac, svga); + return; + + case 0x3cf: + switch (svga->gdcaddr & 15) { + case 0x0e: + svga->gdcreg[0xe] = val ^ 2; + tvga->tvga_3d9 = svga->gdcreg[0xe] & 0xf; + tvga_recalcbanking(tvga); + break; + + case 0x0f: + svga->gdcreg[0xf] = val; + tvga_recalcbanking(tvga); + break; + } + break; + + case 0x3d4: svga->crtcreg = val & 0x3f; - return; - case 0x3D5: - if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80)) - return; - if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80)) - val = (svga->crtc[7] & ~0x10) | (val & 0x10); - old = svga->crtc[svga->crtcreg]; - val &= crtc_mask[svga->crtcreg]; - svga->crtc[svga->crtcreg] = val; - if (old != val) - { - if (svga->crtcreg < 0xE || svga->crtcreg > 0x10) - { - svga->fullchange = changeframecount; - svga_recalctimings(svga); - } - } - switch (svga->crtcreg) - { - case 0x1e: - svga->vram_display_mask = (val & 0x80) ? tvga->vram_mask : 0x3ffff; - break; - } - return; - case 0x3D8: - if (svga->gdcreg[0xf] & 4) - { - tvga->tvga_3d8 = val; - tvga_recalcbanking(tvga); - } - return; - case 0x3D9: - if (svga->gdcreg[0xf] & 4) - { - tvga->tvga_3d9 = val; - tvga_recalcbanking(tvga); - } - return; - } - svga_out(addr, val, svga); + return; + + case 0x3d5: + if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80)) + return; + if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80)) + val = (svga->crtc[7] & ~0x10) | (val & 0x10); + old = svga->crtc[svga->crtcreg]; + val &= crtc_mask[svga->crtcreg]; + svga->crtc[svga->crtcreg] = val; + if (old != val) { + if (svga->crtcreg < 0xE || svga->crtcreg > 0x10) { + svga->fullchange = changeframecount; + svga_recalctimings(svga); + } + } + switch (svga->crtcreg) { + case 0x1e: + svga->vram_display_mask = (val & 0x80) ? tvga->vram_mask : 0x3ffff; + break; + + default: + break; + } + return; + + case 0x3d8: + if (svga->gdcreg[0xf] & 4) { + tvga->tvga_3d8 = val; + tvga_recalcbanking(tvga); + } + return; + + case 0x3d9: + if (svga->gdcreg[0xf] & 4) { + tvga->tvga_3d9 = val; + tvga_recalcbanking(tvga); + } + return; + } + + svga_out(addr, val, svga); } -static uint8_t tvga_in(uint16_t addr, void *priv) -{ - tvga_t *tvga = (tvga_t *)priv; - svga_t *svga = &tvga->svga; - if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1)) addr ^= 0x60; - - switch (addr) - { - case 0x3C5: - if ((svga->seqaddr & 0xf) == 0xb) - { - tvga->oldmode = 0; - return 0x33; /*TVGA8900D*/ - } - if ((svga->seqaddr & 0xf) == 0xd) - { - if (tvga->oldmode) return tvga->oldctrl2; - return tvga->newctrl2; - } - if ((svga->seqaddr & 0xf) == 0xe) - { - if (tvga->oldmode) - return tvga->oldctrl1; - } - break; - case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - return tkd8001_ramdac_in(addr, svga->ramdac, svga); - case 0x3D4: - return svga->crtcreg; - case 0x3D5: - if (svga->crtcreg > 0x18 && svga->crtcreg < 0x1e) - return 0xff; - return svga->crtc[svga->crtcreg]; - case 0x3d8: +static uint8_t +tvga_in(uint16_t addr, void *priv) +{ + tvga_t *tvga = (tvga_t *)priv; + svga_t *svga = &tvga->svga; + + if (((addr&0xfff0) == 0x3d0 || (addr&0xfff0) == 0x3b0) && + !(svga->miscout & 1)) addr ^= 0x60; + + switch (addr) { + case 0x3c5: + if ((svga->seqaddr & 0x0f) == 0x0b) { + tvga->oldmode = 0; + return 0x33; /*TVGA8900D*/ + } + if ((svga->seqaddr & 0x0f) == 0x0d) { + if (tvga->oldmode) + return tvga->oldctrl2; + return tvga->newctrl2; + } + if ((svga->seqaddr & 0x0f) == 0x0e) { + if (tvga->oldmode) + return tvga->oldctrl1; + } + break; + + case 0x3c6: + case 0x3c7: + case 0x3c8: + case 0x3c9: + return tkd8001_ramdac_in(addr, svga->ramdac, svga); + + case 0x3d4: + return svga->crtcreg; + + case 0x3d5: + if (svga->crtcreg > 0x18 && svga->crtcreg < 0x1e) + return 0xff; + return svga->crtc[svga->crtcreg]; + + case 0x3d8: return tvga->tvga_3d8; - case 0x3d9: + + case 0x3d9: return tvga->tvga_3d9; - } - return svga_in(addr, svga); + } + + return svga_in(addr, svga); } static void tvga_recalcbanking(tvga_t *tvga) { - svga_t *svga = &tvga->svga; - - svga->write_bank = (tvga->tvga_3d8 & 0x1f) * 65536; + svga_t *svga = &tvga->svga; - if (svga->gdcreg[0xf] & 1) - svga->read_bank = (tvga->tvga_3d9 & 0x1f) * 65536; - else - svga->read_bank = svga->write_bank; + svga->write_bank = (tvga->tvga_3d8 & 0x1f) * 65536; + + if (svga->gdcreg[0xf] & 1) + svga->read_bank = (tvga->tvga_3d9 & 0x1f) * 65536; + else + svga->read_bank = svga->write_bank; } static void tvga_recalctimings(svga_t *svga) { - tvga_t *tvga = (tvga_t *)svga->p; - if (!svga->rowoffset) svga->rowoffset = 0x100; /*This is the only sensible way I can see this being handled, - given that TVGA8900D has no overflow bits. - Some sort of overflow is required for 320x200x24 and 1024x768x16*/ - if (svga->crtc[0x29] & 0x10) - svga->rowoffset += 0x100; + tvga_t *tvga = (tvga_t *)svga->p; - if (svga->bpp == 24) - svga->hdisp = (svga->crtc[1] + 1) * 8; - - if ((svga->crtc[0x1e] & 0xA0) == 0xA0) svga->ma_latch |= 0x10000; - if ((svga->crtc[0x27] & 0x01) == 0x01) svga->ma_latch |= 0x20000; - if ((svga->crtc[0x27] & 0x02) == 0x02) svga->ma_latch |= 0x40000; - - if (tvga->oldctrl2 & 0x10) - { - svga->rowoffset <<= 1; - svga->ma_latch <<= 1; - } - if (svga->gdcreg[0xf] & 0x08) - { - svga->htotal *= 2; - svga->hdisp *= 2; - svga->hdisp_time *= 2; - } + /* + * This is the only sensible way I can see this being handled, + * given that TVGA8900D has no overflow bits. + * Some sort of overflow is required for 320x200x24 and 1024x768x16 + */ + if (!svga->rowoffset) svga->rowoffset = 0x100; - svga->interlace = (svga->crtc[0x1e] & 4); + if (svga->crtc[0x29] & 0x10) + svga->rowoffset += 0x100; - if (svga->interlace) - svga->rowoffset >>= 1; + if (svga->bpp == 24) + svga->hdisp = (svga->crtc[1] + 1) * 8; - switch (((svga->miscout >> 2) & 3) | ((tvga->newctrl2 << 2) & 4)) - { - case 2: svga->clock = cpuclock/44900000.0; break; - case 3: svga->clock = cpuclock/36000000.0; break; - case 4: svga->clock = cpuclock/57272000.0; break; - case 5: svga->clock = cpuclock/65000000.0; break; - case 6: svga->clock = cpuclock/50350000.0; break; - case 7: svga->clock = cpuclock/40000000.0; break; - } + if ((svga->crtc[0x1e] & 0xA0) == 0xA0) svga->ma_latch |= 0x10000; + if ((svga->crtc[0x27] & 0x01) == 0x01) svga->ma_latch |= 0x20000; + if ((svga->crtc[0x27] & 0x02) == 0x02) svga->ma_latch |= 0x40000; + + if (tvga->oldctrl2 & 0x10) { + svga->rowoffset <<= 1; + svga->ma_latch <<= 1; + } + if (svga->gdcreg[0xf] & 0x08) { + svga->htotal *= 2; + svga->hdisp *= 2; + svga->hdisp_time *= 2; + } - if (tvga->oldctrl2 & 0x10) - { - switch (svga->bpp) - { - case 8: - svga->render = svga_render_8bpp_highres; - break; - case 15: - svga->render = svga_render_15bpp_highres; - svga->hdisp /= 2; - break; - case 16: - svga->render = svga_render_16bpp_highres; - svga->hdisp /= 2; - break; - case 24: - svga->render = svga_render_24bpp_highres; - svga->hdisp /= 3; - break; - } - svga->lowres = 0; - } + svga->interlace = (svga->crtc[0x1e] & 4); + + if (svga->interlace) + svga->rowoffset >>= 1; + + switch (((svga->miscout >> 2) & 3) | ((tvga->newctrl2 << 2) & 4)) { + case 2: svga->clock = cpuclock/44900000.0; break; + case 3: svga->clock = cpuclock/36000000.0; break; + case 4: svga->clock = cpuclock/57272000.0; break; + case 5: svga->clock = cpuclock/65000000.0; break; + case 6: svga->clock = cpuclock/50350000.0; break; + case 7: svga->clock = cpuclock/40000000.0; break; + } + + if (tvga->oldctrl2 & 0x10) { + switch (svga->bpp) { + case 8: + svga->render = svga_render_8bpp_highres; + break; + + case 15: + svga->render = svga_render_15bpp_highres; + svga->hdisp /= 2; + break; + + case 16: + svga->render = svga_render_16bpp_highres; + svga->hdisp /= 2; + break; + + case 24: + svga->render = svga_render_24bpp_highres; + svga->hdisp /= 3; + break; + } + svga->lowres = 0; + } } static void * tvga_init(const device_t *info) { - tvga_t *tvga = (tvga_t *)mem_alloc(sizeof(tvga_t)); - memset(tvga, 0x00, sizeof(tvga_t)); - - tvga->vram_size = device_get_config_int("memory") << 10; - tvga->vram_mask = tvga->vram_size - 1; - - rom_init(&tvga->bios_rom, ROM_TVGA_BIOS, - 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - - svga_init(&tvga->svga, tvga, tvga->vram_size, - tvga_recalctimings, - tvga_in, tvga_out, - NULL, - NULL); + tvga_t *tvga = (tvga_t *)mem_alloc(sizeof(tvga_t)); + memset(tvga, 0x00, sizeof(tvga_t)); - tvga->svga.ramdac = device_add(&tkd8001_ramdac_device); + tvga->vram_size = device_get_config_int("memory") << 10; + tvga->vram_mask = tvga->vram_size - 1; - io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga); + rom_init(&tvga->bios_rom, ROM_TVGA_BIOS, + 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - return tvga; + svga_init(&tvga->svga, tvga, tvga->vram_size, + tvga_recalctimings, tvga_in, tvga_out, NULL, NULL); + + tvga->svga.ramdac = device_add(&tkd8001_ramdac_device); + + io_sethandler(0x03c0, 32, + tvga_in,NULL,NULL, tvga_out,NULL,NULL, tvga); + + video_inform(VID_TYPE_SPEC, + (const video_timings_t *)info->vid_timing); + + return tvga; } static void tvga_close(void *priv) { - tvga_t *tvga = (tvga_t *)priv; + tvga_t *tvga = (tvga_t *)priv; - svga_close(&tvga->svga); + svga_close(&tvga->svga); - free(tvga); + free(tvga); } static void tvga_speed_changed(void *p) { - tvga_t *tvga = (tvga_t *)p; - - svga_recalctimings(&tvga->svga); + tvga_t *tvga = (tvga_t *)p; + + svga_recalctimings(&tvga->svga); } static void tvga_force_redraw(void *p) { - tvga_t *tvga = (tvga_t *)p; + tvga_t *tvga = (tvga_t *)p; - tvga->svga.fullchange = changeframecount; + tvga->svga.fullchange = changeframecount; } static int tvga8900d_available(void) { - return rom_present(ROM_TVGA_BIOS); + return rom_present(ROM_TVGA_BIOS); } static const device_config_t tvga_config[] = { - { - "memory", "Memory size", CONFIG_SELECTION, "", 1024, - { - { - "256 KB", 256 - }, - { - "512 KB", 512 - }, - { - "1 MB", 1024 - }, - /*Chip supports 2MB, but drivers are buggy*/ - { - "" - } - } - }, - { - "", "", -1 - } + { + "memory", "Memory size", CONFIG_SELECTION, "", 1024, + { + { + "256 KB", 256 + }, + { + "512 KB", 512 + }, + { + "1 MB", 1024 + }, + /*Chip supports 2MB, but drivers are buggy*/ + { + "" + } + } + }, + { + "", "", -1 + } }; +static const video_timings_t tvga8900d_timing = {VID_ISA,3,3,6,8,8,12}; + const device_t tvga8900d_device = { "Trident TVGA 8900D", @@ -416,6 +436,6 @@ const device_t tvga8900d_device = { tvga8900d_available, tvga_speed_changed, tvga_force_redraw, - NULL, + &tvga8900d_timing, tvga_config };