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Small fixes here and there.

Browse Source 
First phase of cleaning up the PIC code block.
This commit is contained in:
waltje
2019-03-01 03:00:39 -05:00
parent dbf1c30c22
commit b59bd2881f
43 changed files with 2989 additions and 6173 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/386.c
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@@ -8,7 +8,7 @@
*
* Implementation of 80286+ CPU interpreter.
*
* Version: @(#)386.c 1.0.6 2019/02/10
* Version: @(#)386.c 1.0.7 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -250,8 +250,8 @@ exec386(int cycs)
nmi_auto_clear = 0;
nmi = 0;
}
} else if ((flags & I_FLAG) && pic_intpending) {
temp = picinterrupt();
} else if (flags & I_FLAG) {
temp = pic_interrupt();
if (temp != 0xFF) {
flags_rebuild();

6
src/cpu/386_dynarec.c
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@@ -8,7 +8,7 @@
*
* Implementation of the CPU's dynamic recompiler.
*
* Version: @(#)386_dynarec.c 1.0.6 2019/02/10
* Version: @(#)386_dynarec.c 1.0.7 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -910,9 +910,9 @@ inrecomp=0;
nmi = 0;
}
}
else if ((flags&I_FLAG) && pic_intpending)
else if (flags&I_FLAG)
{
temp=picinterrupt();
temp=pic_interrupt();
if (temp!=0xFF)
{
CPU_BLOCK_END();

10
src/cpu/808x.c
View File

@@ -8,7 +8,7 @@
*
* 808x CPU emulation.
*
* Version: @(#)808x.c 1.0.11 2019/02/15
* Version: @(#)808x.c 1.0.14 2019/02/28
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Andrew Jenner, <https://www.reenigne.org>
@@ -143,14 +143,14 @@ dumpregs(int force)
cpu_state.pc, CS, DS, ES, SS, flags);
INFO("Old CS:EIP: %04X:%08X; %i ins\n", oldcs, cpu_state.oldpc, ins);
for (c = 0; c < 4; c++) {
INFO("%s : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
INFO("%s : base=%06X limit=%08X access=%02X low=%08X high=%08X\n",
seg_names[c], _opseg[c]->base, _opseg[c]->limit,
_opseg[c]->access, _opseg[c]->limit_low, _opseg[c]->limit_high);
}
if (is386) {
INFO("FS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
INFO("FS : base=%06X limit=%08X access=%02X low=%08X limit_high=%08X\n",
seg_fs, _fs.limit, _fs.access, _fs.limit_low, _fs.limit_high);
INFO("GS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
INFO("GS : base=%06X limit=%08X access=%02X low=%08X limit_high=%08X\n",
gs, _gs.limit, _gs.access, _gs.limit_low, _gs.limit_high);
INFO("GDT : base=%06X limit=%04X\n", gdt.base, gdt.limit);
INFO("LDT : base=%06X limit=%04X\n", ldt.base, ldt.limit);
@@ -2824,7 +2824,7 @@ on_halt:
do_intr(2, 1);
nmi_enable = 0;
} else if (takeint && !noint) {
temp = picinterrupt();
temp = pic_interrupt();
if (temp != 0xFF) {
halt = 0;
do_intr(temp, 1);

3273
src/cpu/808x.c.orig
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File diff suppressed because it is too large Load Diff

3583
src/cpu/cpu.c
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File diff suppressed because it is too large Load Diff

22
src/cpu/cpu.h
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@@ -8,7 +8,7 @@
*
* CPU type handler.
*
* Version: @(#)cpu.h 1.0.8 2019/02/11
* Version: @(#)cpu.h 1.0.9 2019/02/17
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* leilei,
@@ -159,9 +159,7 @@ extern CPU cpus_Pentium2D[];
#define CR4_PSE (1 << 4)
#define CPL ((_cs.access>>5)&3)
#define IOPL ((flags>>12)&3)
#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
@@ -323,15 +321,14 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128)
/* Global variables. */
extern int cpu_iscyrix;
extern int xt_cpu_multi;
extern int cpu_16bitbus;
extern int cpu_busspeed;
extern int cpu_multi;
extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is186, is286, is386, is486;
extern int is_nec, is_rapidcad, is_pentium;
extern int is_nec, is_rapidcad, is_cyrix, is_pentium;
extern int hasfpu;
extern int cpu_hasrdtsc;
extern int cpu_hasMSR;
@@ -348,11 +345,9 @@ extern int cycles_lost;
extern uint8_t opcode;
extern int fpucount;
extern float mips,flops;
extern int clockrate;
extern int cgate16;
extern int cpl_override;
extern int CPUID;
extern int xt_cpu_multi;
extern int isa_cycles;
extern int cpu_effective;
@@ -363,7 +358,8 @@ extern int cycdiff;
extern uint32_t pccache;
extern uint8_t *pccache2;
extern float isa_timing, bus_timing;
extern float isa_timing,
bus_timing;
extern uint64_t pmc[2];
extern uint16_t temp_seg_data[4];
extern uint16_t cs_msr;
@@ -406,10 +402,12 @@ extern x86seg _oldds;
#define ISA_CYCLES_SHIFT 6
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
extern int cpu_waitstates;
extern int cpu_cycles_read, cpu_cycles_read_l,
cpu_cycles_write, cpu_cycles_write_l;
extern int cpu_prefetch_cycles, cpu_prefetch_width,
cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
extern int cpu_waitstates;
extern int cpu_pci_speed;
extern int timing_rr;

36
src/cpu/x86_ops_misc.h
View File

@@ -8,7 +8,7 @@
*
* Miscellaneous x86 CPU Instructions.
*
* Version: @(#)x86_ops_misc.h 1.0.2 2018/10/05
* Version: @(#)x86_ops_misc.h 1.0.4 2019/02/28
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -147,7 +147,7 @@ static int opF6_a16(uint32_t fetchdat)
{
AH = src16 % dst;
AL = (src16 / dst) &0xff;
if (!cpu_iscyrix)
if (!is_cyrix)
{
flags_rebuild();
flags |= 0x8D5; /*Not a Cyrix*/
@@ -160,8 +160,8 @@ static int opF6_a16(uint32_t fetchdat)
x86_int(0);
return 1;
}
CLOCK_CYCLES((is486 && !cpu_iscyrix) ? 24 : 22);
PREFETCH_RUN((is486 && !cpu_iscyrix) ? 24 : 22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
CLOCK_CYCLES((is486 && !is_cyrix) ? 24 : 22);
PREFETCH_RUN((is486 && !is_cyrix) ? 24 : 22, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x38: /*IDIV AL,b*/
tempws = (int)(int16_t)AX;
@@ -171,7 +171,7 @@ static int opF6_a16(uint32_t fetchdat)
{
AH = (tempws % (int)((int8_t)dst)) & 0xff;
AL = tempws2 & 0xff;
if (!cpu_iscyrix)
if (!is_cyrix)
{
flags_rebuild();
flags|=0x8D5; /*Not a Cyrix*/
@@ -249,7 +249,7 @@ static int opF6_a32(uint32_t fetchdat)
{
AH = src16 % dst;
AL = (src16 / dst) &0xff;
if (!cpu_iscyrix)
if (!is_cyrix)
{
flags_rebuild();
flags |= 0x8D5; /*Not a Cyrix*/
@@ -261,8 +261,8 @@ static int opF6_a32(uint32_t fetchdat)
x86_int(0);
return 1;
}
CLOCK_CYCLES((is486 && !cpu_iscyrix) ? 16 : 14);
PREFETCH_RUN((is486 && !cpu_iscyrix) ? 16 : 14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
CLOCK_CYCLES((is486 && !is_cyrix) ? 16 : 14);
PREFETCH_RUN((is486 && !is_cyrix) ? 16 : 14, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x38: /*IDIV AL,b*/
tempws = (int)(int16_t)AX;
@@ -272,7 +272,7 @@ static int opF6_a32(uint32_t fetchdat)
{
AH = (tempws % (int)((int8_t)dst)) & 0xff;
AL = tempws2 & 0xff;
if (!cpu_iscyrix)
if (!is_cyrix)
{
flags_rebuild();
flags|=0x8D5; /*Not a Cyrix*/
@@ -353,7 +353,7 @@ static int opF7_w_a16(uint32_t fetchdat)
{
DX = templ % dst;
AX = (templ / dst) & 0xffff;
if (!cpu_iscyrix) setznp16(AX); /*Not a Cyrix*/
if (!is_cyrix) setznp16(AX); /*Not a Cyrix*/
}
else
{
@@ -371,7 +371,7 @@ static int opF7_w_a16(uint32_t fetchdat)
{
DX = tempws % (int)((int16_t)dst);
AX = tempws2 & 0xffff;
if (!cpu_iscyrix) setznp16(AX); /*Not a Cyrix*/
if (!is_cyrix) setznp16(AX); /*Not a Cyrix*/
}
else
{
@@ -445,7 +445,7 @@ static int opF7_w_a32(uint32_t fetchdat)
{
DX = templ % dst;
AX = (templ / dst) & 0xffff;
if (!cpu_iscyrix) setznp16(AX); /*Not a Cyrix*/
if (!is_cyrix) setznp16(AX); /*Not a Cyrix*/
}
else
{
@@ -463,7 +463,7 @@ static int opF7_w_a32(uint32_t fetchdat)
{
DX = tempws % (int)((int16_t)dst);
AX = tempws2 & 0xffff;
if (!cpu_iscyrix) setznp16(AX); /*Not a Cyrix*/
if (!is_cyrix) setznp16(AX); /*Not a Cyrix*/
}
else
{
@@ -533,14 +533,14 @@ static int opF7_l_a16(uint32_t fetchdat)
case 0x30: /*DIV EAX,l*/
if (divl(dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
if (!is_cyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES((is486) ? 40 : 38);
PREFETCH_RUN(is486 ? 40:38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x38: /*IDIV EAX,l*/
if (idivl((int32_t)dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
if (!is_cyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES(43);
PREFETCH_RUN(43, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
@@ -603,14 +603,14 @@ static int opF7_l_a32(uint32_t fetchdat)
case 0x30: /*DIV EAX,l*/
if (divl(dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
if (!is_cyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES((is486) ? 40 : 38);
PREFETCH_RUN(is486 ? 40 : 38, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x38: /*IDIV EAX,l*/
if (idivl((int32_t)dst))
return 1;
if (!cpu_iscyrix) setznp32(EAX); /*Not a Cyrix*/
if (!is_cyrix) setznp32(EAX); /*Not a Cyrix*/
CLOCK_CYCLES(43);
PREFETCH_RUN(43, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
@@ -630,7 +630,7 @@ static int opHLT(uint32_t fetchdat)
x86gpf(NULL,0);
return 1;
}
if (!((flags&I_FLAG) && pic_intpending))
if (!((flags&I_FLAG) && pic_pending))
{
CLOCK_CYCLES_ALWAYS(100);
cpu_state.pc--;

35
src/devices/system/dma.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Intel DMA controllers.
*
* Version: @(#)dma.c 1.0.8 2019/02/11
* Version: @(#)dma.c 1.0.9 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -427,6 +427,7 @@ dma_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
dma_m |= (1 << (val & 3));
else
dma_m &= ~(1 << (val & 3));
if ((val & 3) == 3) INFO("DMA: mask=%02x\n", dma_m);
return;
case 0xb: /*Mode*/
@@ -736,17 +737,25 @@ dma_channel_read(int channel)
int tc = 0;
if (channel < 4) {
if (dma_command & 0x04)
if (dma_command & 0x04) {
DEBUG("DMA: chan_read(%i) & 04\n", channel);
return(DMA_NODATA);
}
} else {
if (dma16_command & 0x04)
if (dma16_command & 0x04) {
DEBUG("DMA: chan_read(%i) & 04\n", channel);
return(DMA_NODATA);
}
}
if (dma_m & (1 << channel))
if (dma_m & (1 << channel)) {
DEBUG("DMA: chan_write(%i) mask %02x\n", channel, dma_m);
return(DMA_NODATA);
if ((dma_c->mode & 0xC) != 8)
}
if ((dma_c->mode & 0xC) != 8) {
DEBUG("DMA: chan_write(%i) mode %02x\n", channel, dma_c->mode);
return(DMA_NODATA);
}
if (! AT)
refreshread();
@@ -807,17 +816,25 @@ dma_channel_write(int channel, uint16_t val)
dma_t *dma_c = &dma[channel];
if (channel < 4) {
if (dma_command & 0x04)
if (dma_command & 0x04) {
DEBUG("DMA: chan_write(%i) & 04\n", channel);
return(DMA_NODATA);
}
} else {
if (dma16_command & 0x04)
if (dma16_command & 0x04) {
DEBUG("DMA: chan_write(%i) & 04\n", channel);
return(DMA_NODATA);
}
}
if (dma_m & (1 << channel))
if (dma_m & (1 << channel)) {
DEBUG("DMA: chan_write(%i) mask %02x\n", channel, dma_m);
return(DMA_NODATA);
if ((dma_c->mode & 0xC) != 4)
}
if ((dma_c->mode & 0xC) != 4) {
DEBUG("DMA: chan_write(%i) mode %02x\n", channel, dma_c->mode);
return(DMA_NODATA);
}
if (! AT)
refreshread();

752
src/devices/system/pic.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of Intel 8259 interrupt controller.
*
* Version: @(#)pic.c 1.0.4 2019/02/10
* Version: @(#)pic.c 1.0.5 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -48,69 +48,34 @@
#include "pit.h"
int intclear;
int keywaiting = 0;
int pic_intpending;
PIC pic, pic2;
uint16_t pic_current;
PIC pic,
pic2;
int pic_pending;
void
pic_updatepending(void)
static uint16_t pic_current;
static int
is_level(uint16_t irq)
{
uint16_t temp_pending = 0;
if (AT) {
if ((pic2.pend & ~pic2.mask) & ~pic2.mask2)
pic.pend |= pic.icw3;
if (PCI)
return pci_irq_is_level(irq);
else {
if (irq < 8)
return (pic.icw1 & 0x08) ? 1 : 0;
else
pic.pend &= ~pic.icw3;
return (pic2.icw1 & 0x08) ? 1 : 0;
}
pic_intpending = (pic.pend & ~pic.mask) & ~pic.mask2;
if (AT) {
if (!((pic.mask | pic.mask2) & pic.icw3)) {
temp_pending = ((pic2.pend&~pic2.mask)&~pic2.mask2);
temp_pending <<= 8;
pic_intpending |= temp_pending;
}
}
#if 0
DBGLOG(1, "pic_intpending = %i %02X %02X %02X %02X\n",
pic_intpending, pic.ins, pic.pend, pic.mask, pic.mask2);
DBGLOG(1, " %02X %02X %02X %02X %i %i\n",
pic2.ins, pic2.pend, pic2.mask, pic2.mask2,
((pic.mask | pic.mask2) & (1 << 2)),
((pic2.pend&~pic2.mask)&~pic2.mask2));
#endif
}
void
pic_reset(void)
{
pic.icw = 0;
pic.mask = 0xff;
pic.mask2 = 0;
pic.pend = pic.ins = 0;
pic.vector = 8;
pic.read = 1;
pic2.icw = 0;
pic2.mask = 0xff;
pic.mask2 = 0;
pic2.pend = pic2.ins = 0;
pic_intpending = 0;
}
void
pic_update_mask(uint8_t *mask, uint8_t ins)
static void
update_mask(uint8_t *mask, uint8_t ins)
{
int c;
*mask = 0;
*mask = 0x00;
for (c = 0; c < 8; c++) {
if (ins & (1 << c)) {
*mask = 0xff << c;
@@ -120,306 +85,374 @@ pic_update_mask(uint8_t *mask, uint8_t ins)
}
static int
picint_is_level(uint16_t irq)
static void
update_pending(void)
{
if (PCI)
return pci_irq_is_level(irq);
else {
if (irq < 8)
return (pic.icw1 & 8) ? 1 : 0;
uint16_t temp = 0;
if (AT) {
if ((pic2.pend & ~pic2.mask) & ~pic2.mask2)
pic.pend |= pic.icw3;
else
return (pic2.icw1 & 8) ? 1 : 0;
pic.pend &= ~pic.icw3;
}
pic_pending = (pic.pend & ~pic.mask) & ~pic.mask2;
if (AT) {
if (! ((pic.mask | pic.mask2) & pic.icw3)) {
temp = ((pic2.pend & ~pic2.mask) & ~pic2.mask2);
temp <<= 8;
pic_pending |= temp;
}
}
#if 0
DBGLOG(2, "pic_intpending = %i %02X %02X %02X %02X\n",
pic_pending, pic.ins, pic.pend, pic.mask, pic.mask2);
DBGLOG(2, " %02X %02X %02X %02X %i %i\n",
pic2.ins, pic2.pend, pic2.mask, pic2.mask2,
((pic.mask | pic.mask2) & (1 << 2)),
((pic2.pend & ~pic2.mask) & ~pic2.mask2));
#endif
}
static void
pic_write(uint16_t addr, uint8_t val, void *priv)
{
PIC *dev = (PIC *)priv;
int c;
if (addr & 1) {
switch (dev->icw) {
case 0: /* OCW1 */
dev->mask = val;
update_pending();
break;
case 1: /* ICW2 */
dev->vector = val & 0xf8;
DEBUG("PIC: vector now: %02X\n", dev->vector);
if (dev->icw1 & 0x02)
dev->icw = 3;
else
dev->icw = 2;
break;
case 2: /* ICW3 */
dev->icw3 = val;
DEBUG("PIC: ICW3 now %02x\n", val);
if (dev->icw1 & 0x01)
dev->icw = 3;
else
dev->icw = 0;
break;
case 3: /* ICW4 */
dev->icw4 = val;
dev->icw = 0;
break;
}
return;
}
if (val & 0x10) {
/* ICW1 */
dev->mask = 0x00;
dev->mask2 = 0x00;
dev->icw = 1;
dev->icw1 = val;
dev->ins = 0;
update_pending();
return;
}
if (! (val & 0x08)) {
/* OCW2 */
if ((val & 0xe0) == 0x60) {
dev->ins &= ~(1 << (val & 0x07));
update_mask(&dev->mask2, dev->ins);
if (AT) {
if (((val & 0x07) == pic2.icw3) &&
(pic2.pend & ~pic2.mask) & ~pic2.mask2)
dev->pend |= dev->icw3;
}
if ((pic_current & (1 << (val & 0x07))) && is_level(val & 0x07)) {
if ((((1 << (val & 0x07)) != dev->icw3) || !AT))
dev->pend |= 1 << (val & 0x07);
}
update_pending();
} else {
for (c = 0; c < 8; c++) {
if (dev->ins & (1 << c)) {
dev->ins &= ~(1 << c);
update_mask(&dev->mask2, dev->ins);
if (AT) {
if (((1 << c) == dev->icw3) &&
(pic2.pend & ~pic2.mask) & ~pic2.mask2)
dev->pend |= dev->icw3;
}
if ((pic_current & (1 << c)) &&
is_level(c)) {
if ((((1 << c) != dev->icw3) || !AT))
dev->pend |= 1 << c;
}
update_pending();
return;
}
}
}
return;
}
/* OCW3 */
if (val & 0x02)
dev->read = (val & 0x01);
}
static uint8_t
pic_read(uint16_t addr, void *priv)
{
PIC *dev = (PIC *)priv;
if (addr & 1) {
DEBUG("PIC1: read mask %02X\n", dev->mask);
return(pic.mask);
}
if (dev->read) {
DEBUG("PIC1: read ins %02X\n", dev->ins);
if (AT)
return(dev->ins | (pic2.ins ? 4 : 0));
else
return(dev->ins);
}
return(dev->pend);
}
static void
pic_autoeoi(void)
{
PIC *dev = &pic;
int c;
for (c = 0; c < 8; c++) {
if (pic.ins & ( 1 << c)) {
pic.ins &= ~(1 << c);
pic_update_mask(&pic.mask2, pic.ins);
if (dev->ins & ( 1 << c)) {
dev->ins &= ~(1 << c);
update_mask(&dev->mask2, dev->ins);
if (AT) {
if (((1 << c) == pic.icw3) && (pic2.pend & ~pic2.mask) & ~pic2.mask2)
pic.pend |= pic.icw3;
if (((1 << c) == dev->icw3) &&
(pic2.pend & ~pic2.mask) & ~pic2.mask2)
dev->pend |= dev->icw3;
}
if ((pic_current & (1 << c)) && picint_is_level(c)) {
if (((1 << c) != pic.icw3) || !AT)
pic.pend |= 1 << c;
if ((pic_current & (1 << c)) && is_level(c)) {
if (((1 << c) != dev->icw3) || !AT)
dev->pend |= (1 << c);
}
pic_updatepending();
update_pending();
return;
}
}
}
void
pic_write(uint16_t addr, uint8_t val, void *priv)
static void
pic2_write(uint16_t addr, uint8_t val, void *priv)
{
PIC *dev = (PIC *)priv;
int c;
if (addr&1) {
switch (pic.icw) {
case 0: /*OCW1*/
pic.mask = val;
pic_updatepending();
if (addr & 1) {
switch (dev->icw) {
case 0: /* OCW1 */
dev->mask = val;
update_pending();
break;
case 1: /*ICW2*/
pic.vector = val & 0xF8;
if (pic.icw1 & 2) pic.icw = 3;
else pic.icw = 2;
case 1: /* ICW2 */
dev->vector = val & 0xf8;
DEBUG("PIC2: vector now: %02X\n", dev->vector);
if (dev->icw1 & 0x02)
dev->icw = 3;
else
dev->icw = 2;
break;
case 2: /*ICW3*/
pic.icw3 = val;
DBGLOG(1, "PIC1 ICW3 now %02X\n", val);
if (pic.icw1 & 1) pic.icw = 3;
else pic.icw = 0;
case 2: /* ICW3 */
dev->icw3 = val;
DEBUG("PIC2: ICW3 now %02X\n", val);
if (dev->icw1 & 1)
dev->icw = 3;
else
dev->icw = 0;
break;
case 3: /*ICW4*/
pic.icw4 = val;
pic.icw = 0;
case 3: /* ICW4 */
dev->icw4 = val;
dev->icw = 0;
break;
}
} else {
if (val & 16) { /*ICW1*/
pic.mask = 0;
pic.mask2 = 0;
pic.icw = 1;
pic.icw1 = val;
pic.ins = 0;
pic_updatepending();
}
else if (!(val & 8)) { /*OCW2*/
if ((val & 0xE0) == 0x60) {
pic.ins &= ~(1 << (val & 7));
pic_update_mask(&pic.mask2, pic.ins);
if (AT) {
if (((val&7) == pic2.icw3) && (pic2.pend & ~pic2.mask) & ~pic2.mask2)
pic.pend |= pic.icw3;
}
if ((pic_current & (1 << (val & 7))) && picint_is_level(val & 7)) {
if ((((1 << (val & 7)) != pic.icw3) || !AT))
pic.pend |= 1 << (val & 7);
}
return;
}
pic_updatepending();
} else {
for (c = 0; c < 8; c++) {
if (pic.ins & (1 << c)) {
pic.ins &= ~(1 << c);
pic_update_mask(&pic.mask2, pic.ins);
if (val & 0x10) {
/* ICW1 */
dev->mask = 0x00;
dev->mask2 = 0x00;
dev->icw = 1;
dev->icw1 = val;
dev->ins = 0;
update_pending();
if (AT) {
if (((1 << c) == pic.icw3) && (pic2.pend & ~pic2.mask) & ~pic2.mask2)
pic.pend |= pic.icw3;
}
return;
}
if ((pic_current & (1 << c)) && picint_is_level(c)) {
if ((((1 << c) != pic.icw3) || !AT))
pic.pend |= 1 << c;
}
if (! (val & 0x08)) {
/* OCW2 */
if ((val & 0xe0) == 0x60) {
dev->ins &= ~(1 << (val & 0x07));
update_mask(&dev->mask2, dev->ins);
if (c == 1 && keywaiting)
intclear &= ~1;
pic_updatepending();
return;
if (pic_current & (0x100 << (val & 0x07)) &&
is_level((val & 0x07) + 8)) {
dev->pend |= (1 << (val & 0x07));
pic.pend |= (1 << dev->icw3);
}
update_pending();
} else {
for (c = 0; c < 8; c++) {
if (dev->ins & (1 << c)) {
dev->ins &= ~(1 << c);
update_mask(&dev->mask2, dev->ins);
if (pic_current & (0x100 << c) && is_level(c + 8)) {
dev->pend |= (1 << c);
pic.pend |= (1 << dev->icw3);
}
update_pending();
return;
}
}
} else { /*OCW3*/
if (val & 2)
pic.read = (val & 1);
}
return;
}
/* OCW3 */
if (val & 0x02)
dev->read = (val & 0x01);
}
uint8_t
pic_read(uint16_t addr, void *priv)
static uint8_t
pic2_read(uint16_t addr, void *priv)
{
PIC *dev = (PIC *)priv;
if (addr & 1) {
DBGLOG(1, "Read PIC mask %02X\n", pic.mask);
return pic.mask;
DBGLOG(1, "PIC2: read mask %02x\n", dev->mask);
return(dev->mask);
}
if (pic.read) {
DBGLOG(1, "Read PIC ins %02X\n", pic.ins);
if (AT)
return pic.ins | (pic2.ins ? 4 : 0);
else
return pic.ins;
if (dev->read) {
DBGLOG(1, "PIC2: read ins %02x\n", dev->ins);
return(dev->ins);
}
return pic.pend;
}
void
pic_init(void)
{
io_sethandler(0x0020, 2,
pic_read,NULL,NULL, pic_write,NULL,NULL, NULL);
DBGLOG(1, "PIC2: read pend %02x\n", dev->pend);
return(dev->pend);
}
static void
pic2_autoeoi(void)
{
PIC *dev = &pic2;
int c;
for (c = 0; c < 8; c++) {
if (pic2.ins & (1 << c)) {
pic2.ins &= ~(1 << c);
pic_update_mask(&pic2.mask2, pic2.ins);
if (dev->ins & (1 << c)) {
dev->ins &= ~(1 << c);
update_mask(&dev->mask2, dev->ins);
if (pic_current & (0x100 << c) && picint_is_level(c + 8)) {
pic2.pend |= (1 << c);
pic.pend |= (1 << pic2.icw3);
if (pic_current & (0x100 << c) && is_level(c + 8)) {
dev->pend |= (1 << c);
pic.pend |= (1 << dev->icw3);
}
pic_updatepending();
update_pending();
return;
}
}
}
void
pic2_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t
pic_process(PIC *dev, int c)
{
int c;
uint8_t pending = dev->pend & ~dev->mask;
int pic_int = c & 7;
int pic_int_num = 1 << pic_int;
int in_service = 0;
if (addr & 1) {
switch (pic2.icw) {
case 0: /*OCW1*/
pic2.mask = val;
pic_updatepending();
break;
in_service = (dev->ins & (pic_int_num - 1));
case 1: /*ICW2*/
pic2.vector = val & 0xF8;
DBGLOG(1, "PIC2 vector now: %02X\n", pic2.vector);
if (pic2.icw1 & 2) pic2.icw = 3;
else pic2.icw = 2;
break;
if (AT && (c >= 8))
in_service |= (pic.ins & 0x03);
case 2: /*ICW3*/
pic2.icw3 = val;
DBGLOG(1, "PIC2 ICW3 now %02X\n", val);
if (pic2.icw1 & 1) pic2.icw = 3;
else pic2.icw = 0;
break;
if ((pending & pic_int_num) && !in_service) {
dev->pend &= ~pic_int_num;
dev->ins |= pic_int_num;
update_mask(&dev->mask2, dev->ins);
case 3: /*ICW4*/
pic2.icw4 = val;
pic2.icw = 0;
break;
if (AT && (c >= 8)) {
pic.ins |= (1 << pic2.icw3); /*Cascade IRQ*/
update_mask(&pic.mask2, pic.ins);
}
} else {
if (val & 16) { /*ICW1*/
pic2.mask = 0;
pic2.mask2 = 0;
pic2.icw = 1;
pic2.icw1 = val;
pic2.ins = 0;
pic_updatepending();
} else if (!(val & 8)) { /*OCW2*/
if ((val & 0xE0) == 0x60) {
pic2.ins &= ~(1 << (val & 7));
pic_update_mask(&pic2.mask2, pic2.ins);
if (pic_current & (0x100 << (val & 7)) && picint_is_level((val & 7) + 8)) {
pic2.pend |= (1 << (val & 7));
pic.pend |= (1 << pic2.icw3);
}
update_pending();
pic_updatepending();
} else {
for (c = 0; c < 8; c++) {
if (pic2.ins & (1 << c)) {
pic2.ins &= ~(1<<c);
pic_update_mask(&pic2.mask2, pic2.ins);
if (dev->icw4 & 0x02)
(AT && (c >= 8)) ? pic2_autoeoi() : pic_autoeoi();
if (pic_current & (0x100 << c) && picint_is_level(c + 8)) {
pic2.pend |= (1 << c);
pic.pend |= (1 << pic2.icw3);
}
if (! c)
pit_set_gate(&pit2, 0, 0);
pic_updatepending();
return;
}
}
}
} else { /*OCW3*/
if (val & 2)
pic2.read = (val & 1);
}
}
}
uint8_t
pic2_read(uint16_t addr, void *priv)
{
if (addr&1) {
#if 0
DBGLOG(1, "Read PIC2 mask %02X %04X:%08X\n", pic2.mask, CS, cpu_state.pc);
#endif
return pic2.mask;
return(pic_int + dev->vector);
}
if (pic2.read) {
#if 0
DBGLOG(1, "Read PIC2 ins %02X %04X:%08X\n", pic2.ins, CS, cpu_state.pc);
#endif
return pic2.ins;
}
#if 0
DBGLOG(1, "Read PIC2 pend %02X %04X:%08X\n", pic2.pend, CS, cpu_state.pc);
#endif
return pic2.pend;
return(0xff);
}
void
pic2_init(void)
{
io_sethandler(0x00a0, 2,
pic2_read,NULL,NULL, pic2_write,NULL,NULL, NULL);
}
void
clearpic(void)
{
pic.pend = pic.ins = 0;
pic_current = 0;
pic_updatepending();
}
void
/* Try to raise an interrupt. */
static void
picint_common(uint16_t num, int level)
{
int c = 0;
if (! num) {
ERRLOG("PIC: Attempting to raise null IRQ\n");
if (num == 0) {
ERRLOG("PIC: attempting to raise IRQ0 !\n");
return;
}
@@ -430,12 +463,12 @@ picint_common(uint16_t num, int level)
c++;
if (AT && (num == pic.icw3) && (pic.icw3 != 4)) {
ERRLOG("PIC: Attempting to raise cascaded IRQ %i\n");
ERRLOG("PIC: attempting to raise cascaded IRQ%i !\n", c);
return;
}
if (!(pic_current & num) || !level) {
DBGLOG(1, "PIC: Raising IRQ %i\n", c);
DBGLOG(2, "PIC: raising IRQ%i\n", c);
if (level)
pic_current |= num;
@@ -450,11 +483,102 @@ picint_common(uint16_t num, int level)
} else
pic.pend |= num;
pic_updatepending();
update_pending();
}
}
void
pic_init(void)
{
memset(&pic, 0x00, sizeof(PIC));
io_sethandler(0x0020, 2,
pic_read,NULL,NULL, pic_write,NULL,NULL, &pic);
}
void
pic2_init(void)
{
memset(&pic2, 0x00, sizeof(PIC));
io_sethandler(0x00a0, 2,
pic2_read,NULL,NULL, pic2_write,NULL,NULL, &pic2);
}
void
pic_reset(void)
{
pic.icw = 0;
pic.mask = 0xff;
pic.mask2 = 0x00;
pic.pend = pic.ins = 0;
pic.vector = 8;
pic.read = 1;
pic2.icw = 0;
pic2.mask = 0xff;
pic.mask2 = 0x00;
pic2.pend = pic2.ins = 0;
pic_pending = 0;
}
#if 0 /*NOT USED */
void
pic_clear(void)
{
pic.pend = pic.ins = 0;
pic_current = 0;
update_pending();
}
#endif
void
picintc(uint16_t num)
{
int c = 0;
if (num == 0) {
ERRLOG("PIC: attempting to lower IRQ0 !\n");
return;
}
if (AT && (num == pic.icw3) && (pic.icw3 == 4))
num = 1 << 9;
while (! (num & (1 << c)))
c++;
if (AT && (num == pic.icw3) && (pic.icw3 != 4)) {
ERRLOG("PIC: attempting to lower cascaded IRQ%i !\n", c);
return;
}
if (pic_current & num)
pic_current &= ~num;
DBGLOG(2, "PIC: lowering IRQ%i\n", c);
if (num > 0xff) {
if (! AT)
return;
pic2.pend &= ~(num >> 8);
if (! ((pic2.pend & ~pic2.mask) & ~pic2.mask2))
pic.pend &= ~(1 << pic2.icw3);
} else
pic.pend &= ~num;
update_pending();
}
void
picint(uint16_t num)
{
@@ -469,108 +593,34 @@ picintlevel(uint16_t num)
}
void
picintc(uint16_t num)
{
int c = 0;
if (!num) {
ERRLOG("PIC: Attempting to lower null IRQ\n");
return;
}
if (AT && (num == pic.icw3) && (pic.icw3 == 4))
num = 1 << 9;
while (!(num & (1 << c)))
c++;
if (AT && (num == pic.icw3) && (pic.icw3 != 4)) {
ERRLOG("PIC: Attempting to lower cascaded IRQ %i\n");
return;
}
if (pic_current & num)
pic_current &= ~num;
DBGLOG(1, "PIC: Lowering IRQ %i\n", c);
if (num > 0xff) {
if (! AT)
return;
pic2.pend &= ~(num >> 8);
if (! ((pic2.pend & ~pic2.mask) & ~pic2.mask2))
pic.pend &= ~(1 << pic2.icw3);
} else
pic.pend &= ~num;
pic_updatepending();
}
static uint8_t
pic_process_interrupt(PIC* target_pic, int c)
{
uint8_t pending = target_pic->pend & ~target_pic->mask;
int pic_int = c & 7;
int pic_int_num = 1 << pic_int;
int in_service = 0;
in_service = (target_pic->ins & (pic_int_num - 1));
if (AT && (c >= 8))
in_service |= (pic.ins & 0x03);
if ((pending & pic_int_num) && !in_service) {
target_pic->pend &= ~pic_int_num;
target_pic->ins |= pic_int_num;
pic_update_mask(&target_pic->mask2, target_pic->ins);
if (AT && (c >= 8)) {
pic.ins |= (1 << pic2.icw3); /*Cascade IRQ*/
pic_update_mask(&pic.mask2, pic.ins);
}
pic_updatepending();
if (target_pic->icw4 & 0x02)
(AT && (c >= 8)) ? pic2_autoeoi() : pic_autoeoi();
if (! c)
pit_set_gate(&pit2, 0, 0);
return pic_int + target_pic->vector;
} else
return 0xFF;
}
uint8_t
picinterrupt(void)
pic_interrupt(void)
{
uint8_t ret = 0xff;
int c, d;
uint8_t ret;
if (! pic_pending) return(ret);
for (c = 0; c <= 7; c++) {
if (AT && ((1 << c) == pic.icw3)) {
for (d = 8; d <= 15; d++) {
ret = pic_process_interrupt(&pic2, d);
if (ret != 0xFF) return ret;
ret = pic_process(&pic2, d);
if (ret != 0xff)
return(ret);
}
} else {
ret = pic_process_interrupt(&pic, c);
if (ret != 0xFF) return ret;
ret = pic_process(&pic, c);
if (ret != 0xff)
return(ret);
}
}
return 0xFF;
return(ret);
}
void
dumppic(void)
pic_dump(void)
{
DEBUG("PIC1 : MASK %02X PEND %02X INS %02X LEVEL %02X VECTOR %02X CASCADE %02X\n", pic.mask, pic.pend, pic.ins, (pic.icw1 & 8) ? 1 : 0, pic.vector, pic.icw3);
if (AT)

14
src/devices/system/pic.h
View File

@@ -8,13 +8,13 @@
*
* Definitions for the Intel 8259 module.
*
* Version: @(#)pic.h 1.0.2 2018/09/05
* Version: @(#)pic.h 1.0.3 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -40,7 +40,7 @@
# define EMU_PIC_H
typedef struct PIC {
typedef struct {
uint8_t icw1,
icw3,
icw4,
@@ -56,19 +56,19 @@ typedef struct PIC {
extern PIC pic,
pic2;
extern int pic_intpending;
extern int pic_pending; /*FIXME: used by x86_ops_misc.h */
extern void pic_init(void);
extern void pic2_init(void);
extern void pic_reset(void);
extern uint8_t pic_interrupt(void);
extern void pic_clear(int num);
extern void pic_dump(void);
extern void picint(uint16_t num);
extern void picintlevel(uint16_t num);
extern void picintc(uint16_t num);
extern uint8_t picinterrupt(void);
extern void picclear(int num);
extern void dumppic(void);
#endif /*EMU_PIC_H*/

8
src/devices/system/pit.c
View File

@@ -13,7 +13,7 @@
* B4 to 40, two writes to 43, then two reads
* - value _does_ change!
*
* Version: @(#)pit.c 1.0.11 2019/02/15
* Version: @(#)pit.c 1.0.12 2019/02/17
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -663,7 +663,7 @@ pit_setclock(uint32_t freq)
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286) {
/* For 286 and up, this is easy. */
cpuclock = (double)freq;
cpuclock = (float)freq;
PITCONST = cpuclock / 1193182.0;
CGACONST = (float) (cpuclock / (19687503.0 / 11.0));
xt_cpu_multi = 1;
@@ -675,7 +675,7 @@ pit_setclock(uint32_t freq)
xt_cpu_multi = 3;
/* Get selected CPU's (max) clock rate. */
speed = machine_speed();
speed = machine_speed(1); //FIXME:
switch (speed) {
case 7159092: /* 7.16 MHz */
@@ -691,7 +691,7 @@ pit_setclock(uint32_t freq)
case 10000000: /* 10 MHz */
case 12000000: /* 12 MHz */
case 16000000: /* 16 MHz */
cpuclock = ((double)speed * xt_cpu_multi);
cpuclock = ((float)speed * xt_cpu_multi);
break;
default:

14
src/machines/m_amstrad.c
View File

@@ -32,7 +32,7 @@
* BIOSES: I need to re-do the bios.txt format so we can load non-BIOS
* ROM files for a given machine, such as font roms here..
*
* Version: @(#)m_amstrad.c 1.0.20 2019/02/12
* Version: @(#)m_amstrad.c 1.0.21 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -1311,42 +1311,42 @@ amstrad_common_init(const machine_t *model, void *arg, int type)
}
void
void
m_amstrad_1512_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 0);
}
void
void
m_amstrad_1640_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 1);
}
void
void
m_amstrad_200_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 2);
}
void
void
m_amstrad_2086_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 3);
}
void
void
m_amstrad_3086_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 4);
}
void
void
m_amstrad_mega_init(const machine_t *model, void *arg)
{
amstrad_common_init(model, arg, 5);

30
src/machines/m_at.c
View File

@@ -8,13 +8,13 @@
*
* Standard PC/AT implementation.
*
* Version: @(#)m_at.c 1.0.10 2018/08/20
* Version: @(#)m_at.c 1.0.11 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -55,7 +55,7 @@
void
machine_at_common_init(const machine_t *model, void *arg)
m_at_common_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);
@@ -68,18 +68,18 @@ machine_at_common_init(const machine_t *model, void *arg)
void
machine_at_init(const machine_t *model, void *arg)
m_at_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_at_device);
}
void
machine_at_ibm_init(const machine_t *model, void *arg)
m_at_ibm_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
mem_remap_top(384);
@@ -88,36 +88,36 @@ machine_at_ibm_init(const machine_t *model, void *arg)
void
machine_at_ps2_init(const machine_t *model, void *arg)
m_at_ps2_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_device);
}
void
machine_at_common_ide_init(const machine_t *model, void *arg)
m_at_common_ide_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&ide_isa_2ch_opt_device);
}
void
machine_at_ide_init(const machine_t *model, void *arg)
m_at_ide_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
device_add(&ide_isa_2ch_opt_device);
}
void
machine_at_ps2_ide_init(const machine_t *model, void *arg)
m_at_ps2_ide_init(const machine_t *model, void *arg)
{
machine_at_ps2_init(model, arg);
m_at_ps2_init(model, arg);
device_add(&ide_isa_2ch_opt_device);
}

88
src/machines/m_at_4x0.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of the Intel 430xx 440xx PCISet chips.
*
* Version: @(#)m_at_4x0.c 1.0.3 2018/11/08
* Version: @(#)m_at_4x0.c 1.0.4 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -431,9 +431,9 @@ static const device_t i440fx_device = {
static void
machine_at_premiere_common_init(const machine_t *model, void *arg)
m_at_premiere_common_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -458,9 +458,9 @@ machine_at_premiere_common_init(const machine_t *model, void *arg)
/* Revenge: Intel Premiere/PCI I/430LX/AMI/SMC FDC37C665 */
void
machine_at_batman_init(const machine_t *model, void *arg)
m_at_batman_init(const machine_t *model, void *arg)
{
machine_at_premiere_common_init(model, arg);
m_at_premiere_common_init(model, arg);
device_add(&i430lx_device);
}
@@ -468,9 +468,9 @@ machine_at_batman_init(const machine_t *model, void *arg)
/* Plato: Intel Premiere/PCI II/430NX/AMI/SMC FDC37C665 */
void
machine_at_plato_init(const machine_t *model, void *arg)
m_at_plato_init(const machine_t *model, void *arg)
{
machine_at_premiere_common_init(model, arg);
m_at_premiere_common_init(model, arg);
device_add(&i430nx_device);
}
@@ -478,9 +478,9 @@ machine_at_plato_init(const machine_t *model, void *arg)
/* P54TP4XE: ASUS P/I-P55TP4XE/430FX/Award/SMC FDC37C665 */
void
machine_at_p54tp4xe_init(const machine_t *model, void *arg)
m_at_p54tp4xe_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -503,11 +503,11 @@ machine_at_p54tp4xe_init(const machine_t *model, void *arg)
/* Endeavor: Intel Advanced_EV/430FX/AMI/NS PC87306 */
void
machine_at_endeavor_init(const machine_t *model, void *arg)
m_at_endeavor_init(const machine_t *model, void *arg)
{
static video_timings_t endeavor_timing = {VID_BUS,3,2,4,25,25,40};
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -536,9 +536,9 @@ machine_at_endeavor_init(const machine_t *model, void *arg)
/* Zappa: Intel Advanced_ZP/430FX/AMI/NS PC87306 */
void
machine_at_zappa_init(const machine_t *model, void *arg)
m_at_zappa_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -560,9 +560,9 @@ machine_at_zappa_init(const machine_t *model, void *arg)
/* MB500N: PC Partner MB500N/430FX/Award/SMC FDC37C665 */
void
machine_at_mb500n_init(const machine_t *model, void *arg)
m_at_mb500n_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -583,9 +583,9 @@ machine_at_mb500n_init(const machine_t *model, void *arg)
/* President: President Award 430FX PCI/430FX/Award/Unknown SIO */
void
machine_at_president_init(const machine_t *model, void *arg)
m_at_president_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -609,9 +609,9 @@ machine_at_president_init(const machine_t *model, void *arg)
/* Thor: Intel Advanced_ATX/430FX/AMI/NS PC87306 */
/* MRthor: Intel Advanced_ATX/430FX/MR.BIOS/NS PC87306 */
void
machine_at_thor_init(const machine_t *model, void *arg)
m_at_thor_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -635,9 +635,9 @@ machine_at_thor_init(const machine_t *model, void *arg)
/* PB640: Packard Bell PB640/430FX/AMI/NS PC87306 */
void
machine_at_pb640_init(const machine_t *model, void *arg)
m_at_pb640_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -665,9 +665,9 @@ machine_at_pb640_init(const machine_t *model, void *arg)
/* AP53: AOpen AP53/430HX/AMI/SMC FDC37C665/669 */
void
machine_at_ap53_init(const machine_t *model, void *arg)
m_at_ap53_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -693,9 +693,9 @@ machine_at_ap53_init(const machine_t *model, void *arg)
/* P55T2P4: ASUS P/I-P55T2P4/430HX/Award/Winbond W8387F*/
void
machine_at_p55t2p4_init(const machine_t *model, void *arg)
m_at_p55t2p4_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -718,9 +718,9 @@ machine_at_p55t2p4_init(const machine_t *model, void *arg)
/* P55T2S: ASUS P/I-P55T2S/430HX/AMI/NS PC87306 */
void
machine_at_p55t2s_init(const machine_t *model, void *arg)
m_at_p55t2s_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -745,9 +745,9 @@ machine_at_p55t2s_init(const machine_t *model, void *arg)
/* P55TVP4: ASUS P/I-P55TVP4/430VX/Award/Winbond W8387F*/
void
machine_at_p55tvp4_init(const machine_t *model, void *arg)
m_at_p55tvp4_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -770,9 +770,9 @@ machine_at_p55tvp4_init(const machine_t *model, void *arg)
/* 430VX: Award 430VX PCI/430VX/Award/UMC UM8669F*/
void
machine_at_i430vx_init(const machine_t *model, void *arg)
m_at_i430vx_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -795,9 +795,9 @@ machine_at_i430vx_init(const machine_t *model, void *arg)
/* P55VA: Epox P55-VA/430VX/Award/SMC FDC37C932FR*/
void
machine_at_p55va_init(const machine_t *model, void *arg)
m_at_p55va_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -818,9 +818,9 @@ machine_at_p55va_init(const machine_t *model, void *arg)
/* J656VXD: Jetway J656VXD/430VX/Award/SMC FDC37C669*/
void
machine_at_j656vxd_init(const machine_t *model, void *arg)
m_at_j656vxd_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -841,9 +841,9 @@ machine_at_j656vxd_init(const machine_t *model, void *arg)
#if defined(DEV_BRANCH) && defined(USE_I686)
/* 440FX: Tyan Titan-Pro AT/440FX/Award BIOS/SMC FDC37C665 */
void
machine_at_i440fx_init(const machine_t *model, void *arg)
m_at_i440fx_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -867,9 +867,9 @@ machine_at_i440fx_init(const machine_t *model, void *arg)
/* S1668: Tyan Titan-Pro ATX/440FX/AMI/SMC FDC37C669 */
void
machine_at_s1668_init(const machine_t *model, void *arg)
m_at_s1668_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_ami_pci_device);
@@ -952,9 +952,9 @@ static const device_t acerm3a_device = {
/* ACERM3A: Acer M3A/430HX/Acer/SMC FDC37C932FR */
void
machine_at_acerm3a_init(const machine_t *model, void *arg)
m_at_acerm3a_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
@@ -979,9 +979,9 @@ machine_at_acerm3a_init(const machine_t *model, void *arg)
/* ACERV35N: Acer V35N/430HX/Acer/SMC FDC37C932FR */
void
machine_at_acerv35n_init(const machine_t *model, void *arg)
m_at_acerv35n_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);

10
src/machines/m_at_ali1429.c
View File

@@ -8,13 +8,13 @@
*
* Implementation the ALI M1429 mainboard.
*
* Version: @(#)m_at_ali1429.c 1.0.6 2018/11/11
* Version: @(#)m_at_ali1429.c 1.0.7 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -127,7 +127,7 @@ ali1429_read(uint16_t port, void *priv)
if (! (port & 1))
return(ali1429_index);
if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && cpu_iscyrix)
if ((ali1429_index >= 0xc0 || ali1429_index == 0x20) && is_cyrix)
return(0xff); /*Don't conflict with Cyrix config registers*/
return(ali1429_regs[ali1429_index]);
@@ -150,11 +150,11 @@ ali1429_init(void)
void
machine_at_ali1429_init(const machine_t *model, void *arg)
m_at_ali1429_init(const machine_t *model, void *arg)
{
ali1429_reset();
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_ami_device);

6
src/machines/m_at_commodore.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Commodore PC3 system.
*
* Version: @(#)m_at_commodore.c 1.0.11 2019/02/10
* Version: @(#)m_at_commodore.c 1.0.12 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -89,9 +89,9 @@ pc3_init(void)
void
machine_at_cmdpc_init(const machine_t *model, void *arg)
m_at_cmdpc_init(const machine_t *model, void *arg)
{
machine_at_ide_init(model, arg);
m_at_ide_init(model, arg);
mem_remap_top(384);

18
src/machines/m_at_compaq.c
View File

@@ -8,14 +8,14 @@
*
* Emulation of various Compaq PC's.
*
* Version: @(#)m_at_compaq.c 1.0.8 2018/09/15
* Version: @(#)m_at_compaq.c 1.0.9 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
* TheCollector1995, <mariogplayer@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -120,7 +120,7 @@ write_raml(uint32_t addr, uint32_t val, void *priv)
static void
compaq_common_init(const machine_t *model, void *arg, int type)
{
machine_at_init(model, arg);
m_at_init(model, arg);
mem_remap_top(384);
@@ -140,11 +140,11 @@ compaq_common_init(const machine_t *model, void *arg, int type)
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
case 3: /* Portable III */
machine_olim24_video_init();
m_olim24_video_init();
break;
case 3+386: /* Portable III/386 */
machine_olim24_video_init();
m_olim24_video_init();
if (hdc_type == 1)
device_add(&ide_isa_device);
break;
@@ -161,28 +161,28 @@ compaq_common_init(const machine_t *model, void *arg, int type)
void
machine_at_compaq_p1_init(const machine_t *model, void *arg)
m_at_compaq_p1_init(const machine_t *model, void *arg)
{
compaq_common_init(model, arg, 0);
}
void
machine_at_compaq_p2_init(const machine_t *model, void *arg)
m_at_compaq_p2_init(const machine_t *model, void *arg)
{
compaq_common_init(model, arg, 2);
}
void
machine_at_compaq_p3_init(const machine_t *model, void *arg)
m_at_compaq_p3_init(const machine_t *model, void *arg)
{
compaq_common_init(model, arg, 3);
}
void
machine_at_compaq_p3_386_init(const machine_t *model, void *arg)
m_at_compaq_p3_386_init(const machine_t *model, void *arg)
{
compaq_common_init(model, arg, 3+386);
}

18
src/machines/m_at_headland.c
View File

@@ -10,13 +10,13 @@
*
* FIXME: fix the mem_map_t stuff in mem_read_b() et al!
*
* Version: @(#)m_at_headland.c 1.0.9 2018/11/02
* Version: @(#)m_at_headland.c 1.0.10 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Original by GreatPsycho for PCem.
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2017,2018 Miran Grca.
* Copyright 2017,2018 GreatPsycho.
*
@@ -387,7 +387,7 @@ hl_read(uint16_t addr, void *priv)
break;
case 0x0023:
if ((dev->indx >= 0xc0 || dev->indx == 0x20) && cpu_iscyrix)
if ((dev->indx >= 0xc0 || dev->indx == 0x20) && is_cyrix)
ret = 0xff; /*Don't conflict with Cyrix config registers*/
else
ret = dev->regs[dev->indx];
@@ -654,9 +654,9 @@ headland_common_init(int ht386)
void
machine_at_tg286m_init(const machine_t *model, void *arg)
m_at_tg286m_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&ide_isa_device);
@@ -666,9 +666,9 @@ machine_at_tg286m_init(const machine_t *model, void *arg)
/* Generic Headland 386SX machine. */
void
machine_at_headland_init(const machine_t *model, void *arg)
m_at_headland_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&ide_isa_device);
@@ -678,12 +678,12 @@ machine_at_headland_init(const machine_t *model, void *arg)
/* Arche Technologies AMA-932J-25 (Headland HT18 386SX-25.) */
void
machine_at_ama932j_init(const machine_t *model, void *arg)
m_at_ama932j_init(const machine_t *model, void *arg)
{
romdef_t *roms = (romdef_t *)arg;
headland_t *dev;
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&ide_isa_device);

14
src/machines/m_at_neat.c
View File

@@ -13,14 +13,14 @@
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
* Version: @(#)m_at_neat.c 1.0.2 2018/10/05
* Version: @(#)m_at_neat.c 1.0.3 2019/02/16
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2018 Fred N. van Kempen.
* Copyright 2018,2019 Fred N. van Kempen.
*
* Redistribution and use in source and binary forms, with
or without modification, are permitted provided that the
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
@@ -811,9 +811,9 @@ neat_init(void)
void
machine_at_neat_init(const machine_t *model, void *arg)
m_at_neat_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
neat_init();
@@ -822,9 +822,9 @@ machine_at_neat_init(const machine_t *model, void *arg)
void
machine_at_neat_ami_init(const machine_t *model, void *arg)
m_at_neat_ami_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
neat_init();

16
src/machines/m_at_opti495.c
View File

@@ -260,13 +260,13 @@ Note: the block address is forced to be a multiple of the block size by
ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187
*
* Version: @(#)m_at_opti495.c 1.0.8 2018/11/02
* Version: @(#)m_at_opti495.c 1.0.9 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -363,9 +363,9 @@ opti495_init(void)
void
machine_at_opti495_ami_init(const machine_t *model, void *arg)
m_at_opti495_ami_init(const machine_t *model, void *arg)
{
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
@@ -375,9 +375,9 @@ machine_at_opti495_ami_init(const machine_t *model, void *arg)
void
machine_at_opti495_award_init(const machine_t *model, void *arg)
m_at_opti495_award_init(const machine_t *model, void *arg)
{
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_device);
device_add(&fdc_at_device);
@@ -387,9 +387,9 @@ machine_at_opti495_award_init(const machine_t *model, void *arg)
void
machine_at_opti495_mr_init(const machine_t *model, void *arg)
m_at_opti495_mr_init(const machine_t *model, void *arg)
{
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);

21
src/machines/m_at_scat.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of Chips&Technology's SCAT (82C235) chipset.
*
* Version: @(#)m_at_scat.c 1.0.12 2018/09/15
* Version: @(#)m_at_scat.c 1.0.13 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Original by GreatPsycho for PCem.
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
*
* This program is free software; you can redistribute it and/or modify
@@ -1319,9 +1319,10 @@ scat_common_init(int type)
void
machine_at_scat_init(const machine_t *model, void *arg)
m_at_scat_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
device_add(&fdc_at_device);
scat_common_init(0);
@@ -1329,9 +1330,9 @@ machine_at_scat_init(const machine_t *model, void *arg)
void
machine_at_scat_gw286ct_init(const machine_t *model, void *arg)
m_at_scat_gw286ct_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
device_add(&fdc_at_device);
@@ -1340,9 +1341,9 @@ machine_at_scat_gw286ct_init(const machine_t *model, void *arg)
void
machine_at_scat_spc4216p_init(const machine_t *model, void *arg)
m_at_scat_spc4216p_init(const machine_t *model, void *arg)
{
machine_at_init(model, arg);
m_at_init(model, arg);
device_add(&fdc_at_device);
@@ -1426,9 +1427,9 @@ scatsx_common_init(void)
void
machine_at_scatsx_init(const machine_t *model, void *arg)
m_at_scatsx_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);

8
src/machines/m_at_sis471.c
View File

@@ -8,12 +8,12 @@
*
* Emulation of the SiS 85c471 Super I/O chip.
*
* Version: @(#)m_at_sis471.c 1.0.12 2018/11/11
* Version: @(#)m_at_sis471.c 1.0.13 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
*
* This program is free software; you can redistribute it and/or modify
@@ -286,9 +286,9 @@ const device_t sis_85c471_device = {
void
machine_at_dtk486_init(const machine_t *model, void *arg)
m_at_dtk486_init(const machine_t *model, void *arg)
{
machine_at_ide_init(model, arg);
m_at_ide_init(model, arg);
device_add(&fdc_at_device);

16
src/machines/m_at_sis496.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of the SiS 85C496/497 chipset.
*
* Version: @(#)m_at_sis49x.c 1.0.8 2018/11/10
* Version: @(#)m_at_sis49x.c 1.0.9 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -409,9 +409,9 @@ const device_t sis_85c496_device = {
static void
machine_at_sis_85c496_common_init(const machine_t *model, void *arg)
common_init(const machine_t *model, void *arg)
{
machine_at_common_init(model, arg);
m_at_common_init(model, arg);
device_add(&keyboard_ps2_pci_device);
device_add(&ide_pci_device);
@@ -435,9 +435,9 @@ machine_at_sis_85c496_common_init(const machine_t *model, void *arg)
void
machine_at_sis496_ami_init(const machine_t *model, void *arg)
m_at_sis496_ami_init(const machine_t *model, void *arg)
{
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
@@ -463,9 +463,9 @@ machine_at_sis496_ami_init(const machine_t *model, void *arg)
void
machine_at_r418_init(const machine_t *model, void *arg)
m_at_r418_init(const machine_t *model, void *arg)
{
machine_at_sis_85c496_common_init(model, arg);
common_init(model, arg);
device_add(&fdc37c665_device);
}

535
src/machines/m_at_sis50x.c
View File

@@ -8,12 +8,12 @@
*
* Emulation of the SiS 85C50x PCI chips.
*
* Version: @(#)m_at_sis50x.c 1.0.4 2018/09/13
* Version: @(#)m_at_sis50x.c 1.0.5 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
*
* This program is free software; you can redistribute it and/or modify
@@ -46,304 +46,313 @@
#include "machine.h"
typedef struct sis_85c501_t
typedef struct {
uint8_t pci_conf[256];
uint8_t turbo_reg;
} 85c501_t;
typedef struct {
uint8_t pci_conf[256];
} 85c503_t;
typedef struct {
uint8_t isa_conf[12];
uint8_t reg;
} 85c50x_isa_t;
static 85c501_t 85c501;
static 85c503_t 85c503;
static 85c50x_isa_t 85c50x_isa;
static void
85c501_recalcmapping(void)
{
uint8_t pci_conf[256];
uint8_t turbo_reg;
} sis_85c501_t;
uint32_t base;
int c, d;
sis_85c501_t sis_85c501;
for (c = 0; c < 1; c++) {
for (d = 0; d < 4; d++) {
base = 0xe0000 + (d << 14);
if (85c501.pci_conf[0x54 + c] & (1 << (d + 4))) {
switch (85c501.pci_conf[0x53] & 0x60) {
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
typedef struct sis_85c503_t
{
uint8_t pci_conf[256];
} sis_85c503_t;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
sis_85c503_t sis_85c503;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
typedef struct sis_85c50x_t
{
uint8_t isa_conf[12];
uint8_t reg;
} sis_85c50x_isa_t;
sis_85c50x_isa_t sis_85c50x_isa;
static void sis_85c501_recalcmapping(void)
{
int c, d;
for (c = 0; c < 1; c++)
{
for (d = 0; d < 4; d++)
{
uint32_t base = 0xe0000 + (d << 14);
if (sis_85c501.pci_conf[0x54 + c] & (1 << (d + 4)))
{
switch (sis_85c501.pci_conf[0x53] & 0x60)
{
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
}
else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
}
} else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
flushmmucache();
shadowbios = 1;
flushmmucache();
shadowbios = 1;
}
static void sis_85c501_write(int func, int addr, uint8_t val, void *p)
static void
85c501_write(int func, int addr, uint8_t val, void *p)
{
if (func)
return;
if (func)
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
break;
case 0x05:
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((sis_85c501.pci_conf[0x54] & val) ^ 0xf0)
{
sis_85c501.pci_conf[0x54] = val;
sis_85c501_recalcmapping();
}
break;
}
sis_85c501.pci_conf[addr] = val;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x42;
val |= 0x04;
break;
case 0x05:
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x54: /*Shadow configure*/
if ((85c501.pci_conf[0x54] & val) ^ 0xf0) {
85c501.pci_conf[0x54] = val;
85c501_recalcmapping();
}
break;
}
85c501.pci_conf[addr] = val;
}
static void sis_85c503_write(int func, int addr, uint8_t val, void *p)
static uint8_t
85c501_read(int func, int addr, void *p)
{
if (func > 0)
return;
if (func)
return 0xff;
if (addr >= 0x0f && addr < 0x41)
return;
return 85c501.pci_conf[addr];
}
switch(addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
static void
85c501_reset(void)
{
memset(&85c501, 0, sizeof(85c501_t));
85c501.pci_conf[0x00] = 0x39; /*SiS*/
85c501.pci_conf[0x01] = 0x10;
85c501.pci_conf[0x02] = 0x06; /*501/502*/
85c501.pci_conf[0x03] = 0x04;
85c501.pci_conf[0x04] = 7;
85c501.pci_conf[0x05] = 0;
85c501.pci_conf[0x06] = 0x80;
85c501.pci_conf[0x07] = 0x02;
85c501.pci_conf[0x08] = 0; /*Device revision*/
85c501.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
85c501.pci_conf[0x0a] = 0x00;
85c501.pci_conf[0x0b] = 0x06;
85c501.pci_conf[0x0e] = 0x00; /*Single function device*/
85c501.pci_conf[0x50] = 0xbc;
85c501.pci_conf[0x51] = 0xfb;
85c501.pci_conf[0x52] = 0xad;
85c501.pci_conf[0x53] = 0xfe;
shadowbios = 1;
}
static void
85c501_init(void)
{
pci_add_card(0, 85c501_read, 85c501_write, NULL);
85c501_reset();
pci_reset_handler.pci_master_reset = NULL;
}
static void
85c503_write(int func, int addr, uint8_t val, void *p)
{
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x41)
return;
switch(addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x04: /*Command register*/
val &= 0x08;
val |= 0x07;
break;
case 0x05:
val = 0;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x41:
DEBUG("Set IRQ routing: INT A -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x42:
DEBUG("Set IRQ routing: INT B -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x43:
DEBUG("Set IRQ routing: INT C -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x44:
DEBUG("Set IRQ routing: INT D -> %02X\n", val);
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
}
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
}
sis_85c503.pci_conf[addr] = val;
85c503.pci_conf[addr] = val;
}
static void sis_85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
static uint8_t
85c503_read(int func, int addr, void *p)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB) sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg] = val;
}
else
{
sis_85c50x_isa.reg = val;
}
}
if (func > 0)
return 0xff;
static uint8_t sis_85c501_read(int func, int addr, void *p)
{
if (func)
return 0xff;
return sis_85c501.pci_conf[addr];
}
static uint8_t sis_85c503_read(int func, int addr, void *p)
{
if (func > 0)
return 0xff;
return sis_85c503.pci_conf[addr];
return 85c503.pci_conf[addr];
}
static uint8_t sis_85c50x_isa_read(uint16_t port, void *priv)
static void
85c503_reset(void)
{
if (port & 1)
{
if (sis_85c50x_isa.reg <= 0xB)
return sis_85c50x_isa.isa_conf[sis_85c50x_isa.reg];
else
return 0xff;
}
memset(&85c503, 0, sizeof(85c503_t));
85c503.pci_conf[0x00] = 0x39; /*SiS*/
85c503.pci_conf[0x01] = 0x10;
85c503.pci_conf[0x02] = 0x08; /*503*/
85c503.pci_conf[0x03] = 0x00;
85c503.pci_conf[0x04] = 7;
85c503.pci_conf[0x05] = 0;
85c503.pci_conf[0x06] = 0x80;
85c503.pci_conf[0x07] = 0x02;
85c503.pci_conf[0x08] = 0; /*Device revision*/
85c503.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
85c503.pci_conf[0x0a] = 0x01;
85c503.pci_conf[0x0b] = 0x06;
85c503.pci_conf[0x0e] = 0x00; /*Single function device*/
85c503.pci_conf[0x41] = 85c503.pci_conf[0x42] = 85c503.pci_conf[0x43] = 85c503.pci_conf[0x44] = 0x80;
}
static void
85c503_init(int card)
{
pci_add_card(card, 85c503_read, 85c503_write, NULL);
85c503_reset();
trc_init();
port_92_reset();
port_92_add();
pci_reset_handler.pci_set_reset = 85c503_reset;
}
static void
85c50x_isa_write(uint16_t port, uint8_t val, void *priv)
{
if (port & 1) {
if (85c50x_isa.reg <= 0x0b)
85c50x_isa.isa_conf[85c50x_isa.reg] = val;
} else
85c50x_isa.reg = val;
}
static uint8_t
85c50x_isa_read(uint16_t port, void *priv)
{
if (port & 1) {
if (85c50x_isa.reg <= 0x0b)
return 85c50x_isa.isa_conf[85c50x_isa.reg];
else
{
return sis_85c50x_isa.reg;
}
return 0xff;
}
return 85c50x_isa.reg;
}
static void sis_85c501_reset(void)
static void
85c50x_isa_init(void)
{
memset(&sis_85c501, 0, sizeof(sis_85c501_t));
sis_85c501.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c501.pci_conf[0x01] = 0x10;
sis_85c501.pci_conf[0x02] = 0x06; /*501/502*/
sis_85c501.pci_conf[0x03] = 0x04;
memset(&85c50x_isa, 0, sizeof(85c50x_isa_t));
sis_85c501.pci_conf[0x04] = 7;
sis_85c501.pci_conf[0x05] = 0;
sis_85c501.pci_conf[0x06] = 0x80;
sis_85c501.pci_conf[0x07] = 0x02;
sis_85c501.pci_conf[0x08] = 0; /*Device revision*/
sis_85c501.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c501.pci_conf[0x0a] = 0x00;
sis_85c501.pci_conf[0x0b] = 0x06;
sis_85c501.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c501.pci_conf[0x50] = 0xbc;
sis_85c501.pci_conf[0x51] = 0xfb;
sis_85c501.pci_conf[0x52] = 0xad;
sis_85c501.pci_conf[0x53] = 0xfe;
shadowbios = 1;
}
static void sis_85c501_init(void)
{
pci_add_card(0, sis_85c501_read, sis_85c501_write, NULL);
sis_85c501_reset();
pci_reset_handler.pci_master_reset = NULL;
}
static void sis_85c503_reset(void)
{
memset(&sis_85c503, 0, sizeof(sis_85c503_t));
sis_85c503.pci_conf[0x00] = 0x39; /*SiS*/
sis_85c503.pci_conf[0x01] = 0x10;
sis_85c503.pci_conf[0x02] = 0x08; /*503*/
sis_85c503.pci_conf[0x03] = 0x00;
sis_85c503.pci_conf[0x04] = 7;
sis_85c503.pci_conf[0x05] = 0;
sis_85c503.pci_conf[0x06] = 0x80;
sis_85c503.pci_conf[0x07] = 0x02;
sis_85c503.pci_conf[0x08] = 0; /*Device revision*/
sis_85c503.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis_85c503.pci_conf[0x0a] = 0x01;
sis_85c503.pci_conf[0x0b] = 0x06;
sis_85c503.pci_conf[0x0e] = 0x00; /*Single function device*/
sis_85c503.pci_conf[0x41] = sis_85c503.pci_conf[0x42] = sis_85c503.pci_conf[0x43] = sis_85c503.pci_conf[0x44] = 0x80;
}
static void sis_85c503_init(int card)
{
pci_add_card(card, sis_85c503_read, sis_85c503_write, NULL);
sis_85c503_reset();
trc_init();
port_92_reset();
port_92_add();
pci_reset_handler.pci_set_reset = sis_85c503_reset;
}
static void sis_85c50x_isa_init(void)
{
memset(&sis_85c50x_isa, 0, sizeof(sis_85c50x_isa_t));
io_sethandler(0x22, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, NULL);
io_sethandler(0x22, 2,
85c50x_isa_read,NULL,NULL, 85c50x_isa_write,NULL,NULL, NULL);
}

8
src/machines/m_at_t3100e.c
View File

@@ -121,13 +121,13 @@
* bit 2 set for single-pixel LCD font
* bits 0,1 for display font
*
* Version: @(#)m_at_t3100e.c 1.0.9 2018/09/13
* Version: @(#)m_at_t3100e.c 1.0.10 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2017-2018 John Elliott.
*
@@ -603,13 +603,13 @@ upper_write_raml(uint32_t addr, uint32_t val, void *priv)
void
machine_at_t3100e_init(const machine_t *model, void *arg)
m_at_t3100e_init(const machine_t *model, void *arg)
{
int pg;
memset(&t3100e, 0x00, sizeof(t3100e_t));
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_at_toshiba_device);

8
src/machines/m_at_wd76c10.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of the WD76C10 system controller.
*
* Version: @(#)m_at_wd76c10.c 1.0.10 2018/11/10
* Version: @(#)m_at_wd76c10.c 1.0.11 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -218,11 +218,11 @@ wd76c10_init(void)
void
machine_at_wd76c10_init(const machine_t *model, void *arg)
m_at_wd76c10_init(const machine_t *model, void *arg)
{
wd76c10_t *dev;
machine_at_common_ide_init(model, arg);
m_at_common_ide_init(model, arg);
device_add(&keyboard_ps2_quadtel_device);

4
src/machines/m_europc.c
View File

@@ -69,7 +69,7 @@
* FIXME: Find a new way to handle the switching of color/mono on
* external cards. New video_get_type(int card) function?
*
* Version: @(#)m_europc.c 1.0.18 2019/02/11
* Version: @(#)m_europc.c 1.0.19 2019/02/16
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
@@ -776,7 +776,7 @@ const device_t europc_device = {
* user.
*/
void
machine_europc_init(const machine_t *model, void *arg)
m_europc_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);

6
src/machines/m_olivetti_m24.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of the Olivetti M24.
*
* Version: @(#)m_olivetti_m24.c 1.0.13 2019/02/12
* Version: @(#)m_olivetti_m24.c 1.0.14 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -801,7 +801,7 @@ const device_t m24_device = {
void
machine_olim24_init(const machine_t *model, void *arg)
m_olim24_init(const machine_t *model, void *arg)
{
olim24_t *dev;
@@ -859,7 +859,7 @@ machine_olim24_init(const machine_t *model, void *arg)
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
/* Compaq Portable III also seems to use this. */
void
machine_olim24_video_init(void)
m_olim24_video_init(void)
{
olim24_t *dev;

30
src/machines/m_pcjr.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of the IBM PCjr.
*
* Version: @(#)m_pcjr.c 1.0.12 2019/02/15
* Version: @(#)m_pcjr.c 1.0.13 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -751,16 +751,16 @@ const device_t m_pcjr_device = {
void
machine_pcjr_init(const machine_t *model, UNUSED(void *arg))
m_pcjr_init(const machine_t *model, UNUSED(void *arg))
{
int display_type;
pcjr_t *pcjr;
pcjr_t *dev;
pcjr = (pcjr_t *)mem_alloc(sizeof(pcjr_t));
memset(pcjr, 0x00, sizeof(pcjr_t));
pcjr->memctrl = -1;
dev = (pcjr_t *)mem_alloc(sizeof(pcjr_t));
memset(dev, 0x00, sizeof(pcjr_t));
dev->memctrl = -1;
display_type = machine_get_config_int("display_type");
pcjr->composite = (display_type != PCJR_RGB);
dev->composite = (display_type != PCJR_RGB);
pic_init();
pit_init();
@@ -776,13 +776,13 @@ machine_pcjr_init(const machine_t *model, UNUSED(void *arg))
}
/* Initialize the video controller. */
mem_map_add(&pcjr->mapping, 0xb8000, 0x08000,
mem_map_add(&dev->mapping, 0xb8000, 0x08000,
vid_read, NULL, NULL,
vid_write, NULL, NULL, NULL, 0, pcjr);
vid_write, NULL, NULL, NULL, 0, dev);
io_sethandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, pcjr);
timer_add(vid_poll, &pcjr->vidtime, TIMER_ALWAYS_ENABLED, pcjr);
device_add_ex(&m_pcjr_device, pcjr);
vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
timer_add(vid_poll, &dev->vidtime, TIMER_ALWAYS_ENABLED, dev);
device_add_ex(&m_pcjr_device, dev);
video_inform(VID_TYPE_CGA,
(const video_timings_t *)&m_pcjr_device.vid_timing);
@@ -790,10 +790,10 @@ machine_pcjr_init(const machine_t *model, UNUSED(void *arg))
keyboard_scan = 1;
key_queue_start = key_queue_end = 0;
io_sethandler(0x0060, 4,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
kbd_read, NULL, NULL, kbd_write, NULL, NULL, dev);
io_sethandler(0x00a0, 8,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, pcjr);
kbd_read, NULL, NULL, kbd_write, NULL, NULL, dev);
timer_add(kbd_poll, &keyboard_delay, TIMER_ALWAYS_ENABLED, dev);
keyboard_set_table(scancode_xt);
keyboard_send = kbd_adddata_ex;

10
src/machines/m_ps1.c
View File

@@ -22,13 +22,13 @@
* The reserved 384K is remapped to the top of extended memory.
* If this is not done then you get an error on startup.
*
* Version: @(#)m_ps1.c 1.0.22 2018/11/11
* Version: @(#)m_ps1.c 1.0.23 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -655,7 +655,7 @@ ps1_set_feedback(void *priv)
void
machine_ps1_m2011_init(const machine_t *model, void *arg)
m_ps1_m2011_init(const machine_t *model, void *arg)
{
ps1_common_init(model, arg);
@@ -664,7 +664,7 @@ machine_ps1_m2011_init(const machine_t *model, void *arg)
void
machine_ps1_m2121_init(const machine_t *model, void *arg)
m_ps1_m2121_init(const machine_t *model, void *arg)
{
ps1_common_init(model, arg);
@@ -673,7 +673,7 @@ machine_ps1_m2121_init(const machine_t *model, void *arg)
void
machine_ps1_m2133_init(const machine_t *model, void *arg)
m_ps1_m2133_init(const machine_t *model, void *arg)
{
ps1_common_init(model, arg);

10
src/machines/m_ps2_isa.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of ISA-based PS/2 machines.
*
* Version: @(#)m_ps2_isa.c 1.0.14 2018/11/11
* Version: @(#)m_ps2_isa.c 1.0.15 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -182,7 +182,7 @@ ps2_write(uint16_t port, uint8_t val, void *priv)
static void
ps2board_init(void)
ps2_common_init(void)
{
io_sethandler(0x0091, 1, ps2_read,NULL,NULL, ps2_write,NULL,NULL, NULL);
io_sethandler(0x0094, 1, ps2_read,NULL,NULL, ps2_write,NULL,NULL, NULL);
@@ -205,7 +205,7 @@ ps2board_init(void)
void
machine_ps2_m30_286_init(const machine_t *model, void *arg)
m_ps2_m30_286_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);
@@ -215,7 +215,7 @@ machine_ps2_m30_286_init(const machine_t *model, void *arg)
dma16_init();
pic2_init();
ps2board_init();
ps2_common_init();
device_add(&keyboard_ps2_device);
device_add(&ps_nvr_device);

32
src/machines/m_ps2_mca.c
View File

@@ -48,13 +48,13 @@
*
* This works around the timing loop mentioned above.
*
* Version: @(#)m_ps2_mca.c 1.0.19 2018/11/11
* Version: @(#)m_ps2_mca.c 1.0.20 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -698,7 +698,7 @@ model_50_write(uint16_t port, uint8_t val)
static void
board_model_50_init(void)
model_50_init(void)
{
board_common_init();
@@ -846,7 +846,7 @@ model_55sx_write(uint16_t port, uint8_t val)
static void
board_model_55sx_init(void)
model_55sx_init(void)
{
board_common_init();
@@ -1165,7 +1165,7 @@ model_70_type3_write(uint16_t port, uint8_t val)
static void
board_model_70_type34_init(int is_type4)
model_70_type34_init(int is_type4)
{
board_common_init();
@@ -1337,7 +1337,7 @@ model_80_write(uint16_t port, uint8_t val)
static void
board_model_80_type2_init(int is_486)
model_80_type2_init(int is_486)
{
board_common_init();
@@ -1420,45 +1420,45 @@ ps2_common_init(const machine_t *model, void *arg)
void
machine_ps2_model_50_init(const machine_t *model, void *arg)
m_ps2_model_50_init(const machine_t *model, void *arg)
{
ps2_common_init(model, arg);
board_model_50_init();
model_50_init();
}
void
machine_ps2_model_55sx_init(const machine_t *model, void *arg)
m_ps2_model_55sx_init(const machine_t *model, void *arg)
{
ps2_common_init(model, arg);
board_model_55sx_init();
model_55sx_init();
}
void
machine_ps2_model_70_type3_init(const machine_t *model, void *arg)
m_ps2_model_70_type3_init(const machine_t *model, void *arg)
{
ps2_common_init(model, arg);
board_model_70_type34_init(0);
model_70_type34_init(0);
}
void
machine_ps2_model_70_type4_init(const machine_t *model, void *arg)
m_ps2_model_70_type4_init(const machine_t *model, void *arg)
{
ps2_common_init(model, arg);
board_model_70_type34_init(1);
model_70_type34_init(1);
}
void
machine_ps2_model_80_init(const machine_t *model, void *arg)
m_ps2_model_80_init(const machine_t *model, void *arg)
{
ps2_common_init(model, arg);
board_model_80_type2_init(0);
model_80_type2_init(0);
}

10
src/machines/m_tandy.c
View File

@@ -11,13 +11,13 @@
* NOTE: It might be better (after all..) to split off the video
* driver from the main code, to keep it a little cleaner.
*
* Version: @(#)m_tandy.c 1.0.14 2018/10/24
* Version: @(#)m_tandy.c 1.0.15 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -1991,21 +1991,21 @@ tandy1k_common_init(const machine_t *model, void *arg, int type)
void
machine_tandy1k_init(const machine_t *model, void *arg)
m_tandy1k_init(const machine_t *model, void *arg)
{
tandy1k_common_init(model, arg, 0);
}
void
machine_tandy1k_hx_init(const machine_t *model, void *arg)
m_tandy1k_hx_init(const machine_t *model, void *arg)
{
tandy1k_common_init(model, arg, 1);
}
void
machine_tandy1k_sl2_init(const machine_t *model, void *arg)
m_tandy1k_sl2_init(const machine_t *model, void *arg)
{
tandy1k_common_init(model, arg, 2);
}

20
src/machines/m_xt.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of standard IBM PC/XT class machine.
*
* Version: @(#)m_xt.c 1.0.14 2019/02/13
* Version: @(#)m_xt.c 1.0.15 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -56,7 +56,7 @@
/* Generic PC/XT system board with just the basics. */
void
machine_pc_common_init(const machine_t *model, void *arg)
m_pc_common_init(const machine_t *model, void *arg)
{
int rom_basic;
@@ -80,9 +80,9 @@ machine_pc_common_init(const machine_t *model, void *arg)
/* The original IBM PC, 1981 model. */
void
machine_pc_init(const machine_t *model, void *arg)
m_pc_init(const machine_t *model, void *arg)
{
machine_pc_common_init(model, arg);
m_pc_common_init(model, arg);
device_add(&keyboard_pc_device);
@@ -94,9 +94,9 @@ machine_pc_init(const machine_t *model, void *arg)
/* The later IBM PC from 1982. */
void
machine_pc82_init(const machine_t *model, void *arg)
m_pc82_init(const machine_t *model, void *arg)
{
machine_pc_common_init(model, arg);
m_pc_common_init(model, arg);
device_add(&keyboard_pc82_device);
@@ -108,9 +108,9 @@ machine_pc82_init(const machine_t *model, void *arg)
/* The original IBM PC/XT, 1982 model. */
void
machine_xt_init(const machine_t *model, void *arg)
m_xt_init(const machine_t *model, void *arg)
{
machine_pc_common_init(model, arg);
m_pc_common_init(model, arg);
device_add(&keyboard_xt_device);
}
@@ -118,9 +118,9 @@ machine_xt_init(const machine_t *model, void *arg)
/* The later IBM PC/XT from 1986. */
void
machine_xt86_init(const machine_t *model, void *arg)
m_xt86_init(const machine_t *model, void *arg)
{
machine_pc_common_init(model, arg);
m_pc_common_init(model, arg);
device_add(&keyboard_xt86_device);
}

6
src/machines/m_xt_compaq.c
View File

@@ -8,13 +8,13 @@
*
* Emulation of the Compaq XT-class PC's.
*
* Version: @(#)m_xt_compaq.c 1.0.13 2018/11/11
* Version: @(#)m_xt_compaq.c 1.0.14 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -55,7 +55,7 @@
void
machine_xt_compaq_p1_init(const machine_t *model, void *arg)
m_xt_compaq_p1_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);

8
src/machines/m_xt_laserxt.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of the Laser XT series of machines.
*
* Version: @(#)m_xt_laserxt.c 1.0.8 2019/02/11
* Version: @(#)m_xt_laserxt.c 1.0.9 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -197,16 +197,16 @@ laserxt_init(int lxt3)
void
machine_xt_laserxt_init(const machine_t *model, void *arg)
m_xt_laserxt_init(const machine_t *model, void *arg)
{
machine_xt_init(model, arg);
m_xt_init(model, arg);
laserxt_init(0);
}
void
machine_xt_lxt3_init(const machine_t *model, void *arg)
m_xt_lxt3_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);

10
src/machines/m_xt_t1000.c
View File

@@ -96,13 +96,13 @@
*
* FIXME: The ROM drive should be re-done using the "option file".
*
* Version: @(#)m_xt_t1000.c 1.0.14 2018/09/22
* Version: @(#)m_xt_t1000.c 1.0.15 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
* Copyright 2018 Fred N. van Kempen.
* Copyright 2018,2019 Fred N. van Kempen.
* Copyright 2018 Miran Grca.
* Copyright 2017,2018 John Elliott.
*
@@ -936,7 +936,7 @@ const device_t m_xt_t1000_device = {
};
void
void
m_xt_t1000_init(const machine_t *model, void *arg)
{
FILE *f;
@@ -1036,7 +1036,7 @@ t1200_nvram_write(uint32_t addr, uint8_t val, void *priv)
}
void
void
m_xt_t1200_init(const machine_t *model, void *arg)
{
int pg;
@@ -1092,7 +1092,7 @@ machine_xt_t1200_init(const machine_t *model, void *arg)
}
void
void
m_xt_t1x00_close(void)
{
cfgsys_save(&t1000);

6
src/machines/m_xt_xi8088.c
View File

@@ -8,13 +8,13 @@
*
* Implementation of the Xi8088 open-source machine.
*
* Version: @(#)m_xt_xi8088.c 1.0.11 2018/09/19
* Version: @(#)m_xt_xi8088.c 1.0.12 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
@@ -142,7 +142,7 @@ const device_t m_xi8088_device = {
void
machine_xt_xi8088_init(const machine_t *model, void *arg)
m_xt_xi8088_init(const machine_t *model, void *arg)
{
/* Initialize local state. */
memset(&xi8088, 0x00, sizeof(xi8088_t));

4
src/machines/m_zenith.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Zenith SupersPORT.
*
* Version: @(#)m_zenith.c 1.0.2 2019/01/13
* Version: @(#)m_zenith.c 1.0.3 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Original patch for PCem by 'Tux'
@@ -131,7 +131,7 @@ static const device_t scratchpad_device = {
void
machine_zenith_supersport_init(const machine_t *model, void *arg)
m_zenith_supersport_init(const machine_t *model, void *arg)
{
machine_common_init(model, arg);

36
src/machines/machine.c
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.c 1.0.18 2019/02/15
* Version: @(#)machine.c 1.0.19 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -125,14 +125,44 @@ machine_close(void)
}
/* Return the (maximum) speed at which this machine will run. */
/* Return the machine type. */
int
machine_type(void)
{
return (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type);
}
/* Return this machine's default or slow speed. */
uint32_t
machine_speed(void)
machine_speed(int turbo)
{
uint32_t k;
int mhz;
/* Get the current CPU's maximum speed. */
k = machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed;
/*
* If not on turbo, use the speed the mainboard
* has set as its fallback ("slow") speed.
*/
if (! turbo) {
mhz = machines[machine].slow_mhz;
switch(mhz) {
case -1: /* machine has no slow/turbo switching */
break;
case 0: /* use half of current max speed */
k >>= 1;
break;
default: /* use specified speed */
k = (mhz << 20);
break;
}
}
return(k);
}

176
src/machines/machine.h
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.h 1.0.26 2019/02/11
* Version: @(#)machine.h 1.0.27 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -65,6 +65,7 @@ typedef struct _machine_ {
const char *name;
const char *internal_name;
const wchar_t *bios_path;
int slow_mhz;
struct {
const char *name;
#ifdef EMU_CPU_H
@@ -103,7 +104,8 @@ extern int machine_get_from_internal_name(const char *s);
extern int machine_available(int id);
extern void machine_reset(void);
extern void machine_close(void);
extern uint32_t machine_speed(void);
extern int machine_type(void);
extern uint32_t machine_speed(int turbo);
#ifdef EMU_DEVICE_H
extern const device_t *machine_getdevice(int machine);
#endif
@@ -114,82 +116,82 @@ extern const char *machine_get_config_string(const char *s);
/* Initialization functions for boards and systems. */
extern void machine_common_init(const machine_t *, void *);
extern void machine_at_common_init(const machine_t *, void *);
extern void machine_at_init(const machine_t *, void *);
extern void machine_at_ibm_init(const machine_t *, void *);
extern void machine_at_ps2_init(const machine_t *, void *);
extern void machine_at_common_ide_init(const machine_t *, void *);
extern void machine_at_ide_init(const machine_t *, void *);
extern void machine_at_ps2_ide_init(const machine_t *, void *);
extern void m_at_common_init(const machine_t *, void *);
extern void m_at_init(const machine_t *, void *);
extern void m_at_ibm_init(const machine_t *, void *);
extern void m_at_ps2_init(const machine_t *, void *);
extern void m_at_common_ide_init(const machine_t *, void *);
extern void m_at_ide_init(const machine_t *, void *);
extern void m_at_ps2_ide_init(const machine_t *, void *);
extern void machine_at_t3100e_init(const machine_t *, void *);
extern void m_at_t3100e_init(const machine_t *, void *);
extern void machine_at_p54tp4xe_init(const machine_t *, void *);
extern void machine_at_endeavor_init(const machine_t *, void *);
extern void machine_at_zappa_init(const machine_t *, void *);
extern void machine_at_mb500n_init(const machine_t *, void *);
extern void machine_at_president_init(const machine_t *, void *);
extern void machine_at_thor_init(const machine_t *, void *);
extern void machine_at_pb640_init(const machine_t *, void *);
extern void m_at_p54tp4xe_init(const machine_t *, void *);
extern void m_at_endeavor_init(const machine_t *, void *);
extern void m_at_zappa_init(const machine_t *, void *);
extern void m_at_mb500n_init(const machine_t *, void *);
extern void m_at_president_init(const machine_t *, void *);
extern void m_at_thor_init(const machine_t *, void *);
extern void m_at_pb640_init(const machine_t *, void *);
extern void machine_at_acerm3a_init(const machine_t *, void *);
extern void machine_at_acerv35n_init(const machine_t *, void *);
extern void machine_at_ap53_init(const machine_t *, void *);
extern void machine_at_p55t2p4_init(const machine_t *, void *);
extern void machine_at_p55t2s_init(const machine_t *, void *);
extern void m_at_acerm3a_init(const machine_t *, void *);
extern void m_at_acerv35n_init(const machine_t *, void *);
extern void m_at_ap53_init(const machine_t *, void *);
extern void m_at_p55t2p4_init(const machine_t *, void *);
extern void m_at_p55t2s_init(const machine_t *, void *);
extern void machine_at_batman_init(const machine_t *, void *);
extern void machine_at_plato_init(const machine_t *, void *);
extern void m_at_batman_init(const machine_t *, void *);
extern void m_at_plato_init(const machine_t *, void *);
extern void machine_at_p55tvp4_init(const machine_t *, void *);
extern void machine_at_i430vx_init(const machine_t *, void *);
extern void machine_at_p55va_init(const machine_t *, void *);
extern void machine_at_j656vxd_init(const machine_t *, void *);
extern void m_at_p55tvp4_init(const machine_t *, void *);
extern void m_at_i430vx_init(const machine_t *, void *);
extern void m_at_p55va_init(const machine_t *, void *);
extern void m_at_j656vxd_init(const machine_t *, void *);
#if defined(DEV_BRANCH) && defined(USE_I686)
extern void machine_at_i440fx_init(const machine_t *, void *);
extern void machine_at_s1668_init(const machine_t *, void *);
extern void m_at_i440fx_init(const machine_t *, void *);
extern void m_at_s1668_init(const machine_t *, void *);
#endif
extern void machine_at_ali1429_init(const machine_t *, void *);
extern void machine_at_cmdpc_init(const machine_t *, void *);
extern void m_at_ali1429_init(const machine_t *, void *);
extern void m_at_cmdpc_init(const machine_t *, void *);
extern void machine_at_tg286m_init(const machine_t *, void *);
extern void machine_at_headland_init(const machine_t *, void *);
extern void machine_at_ama932j_init(const machine_t *, void *);
extern void machine_at_neat_init(const machine_t *, void *);
extern void machine_at_neat_ami_init(const machine_t *, void *);
extern void m_at_tg286m_init(const machine_t *, void *);
extern void m_at_headland_init(const machine_t *, void *);
extern void m_at_ama932j_init(const machine_t *, void *);
extern void m_at_neat_init(const machine_t *, void *);
extern void m_at_neat_ami_init(const machine_t *, void *);
extern void machine_at_opti495_ami_init(const machine_t *, void *);
extern void machine_at_opti495_award_init(const machine_t *, void *);
extern void machine_at_opti495_mr_init(const machine_t *, void *);
extern void m_at_opti495_ami_init(const machine_t *, void *);
extern void m_at_opti495_award_init(const machine_t *, void *);
extern void m_at_opti495_mr_init(const machine_t *, void *);
extern void machine_at_sis471_ami_init(const machine_t *, void *);
extern void machine_at_dtk486_init(const machine_t *, void *);
extern void m_at_sis471_ami_init(const machine_t *, void *);
extern void m_at_dtk486_init(const machine_t *, void *);
extern void machine_at_sis496_ami_init(const machine_t *, void *);
extern void machine_at_r418_init(const machine_t *, void *);
extern void m_at_sis496_ami_init(const machine_t *, void *);
extern void m_at_r418_init(const machine_t *, void *);
extern void machine_at_scat_init(const machine_t*, void*);
extern void machine_at_scat_gw286ct_init(const machine_t*, void*);
extern void machine_at_scat_spc4216p_init(const machine_t*, void*);
extern void m_at_scat_init(const machine_t*, void*);
extern void m_at_scat_gw286ct_init(const machine_t*, void*);
extern void m_at_scat_spc4216p_init(const machine_t*, void*);
extern void machine_at_scatsx_init(const machine_t*, void*);
extern void m_at_scatsx_init(const machine_t*, void*);
extern void machine_at_compaq_p1_init(const machine_t*, void*);
extern void machine_at_compaq_p2_init(const machine_t*, void*);
extern void machine_at_compaq_p3_init(const machine_t*, void*);
extern void machine_at_compaq_p3_386_init(const machine_t*, void*);
extern void m_at_compaq_p1_init(const machine_t*, void*);
extern void m_at_compaq_p2_init(const machine_t*, void*);
extern void m_at_compaq_p3_init(const machine_t*, void*);
extern void m_at_compaq_p3_386_init(const machine_t*, void*);
extern void machine_at_wd76c10_init(const machine_t *, void *);
extern void m_at_wd76c10_init(const machine_t *, void *);
extern void machine_pcjr_init(const machine_t *, void *);
extern void m_pcjr_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_pcjr_device;
#endif
extern void machine_ps1_m2011_init(const machine_t *, void *);
extern void machine_ps1_m2121_init(const machine_t *, void *);
extern void machine_ps1_m2133_init(const machine_t *, void *);
extern void m_ps1_m2011_init(const machine_t *, void *);
extern void m_ps1_m2121_init(const machine_t *, void *);
extern void m_ps1_m2133_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern void ps1_hdc_inform(void *, void *);
extern void ps1_set_feedback(void *);
@@ -197,31 +199,31 @@ extern const device_t m_ps1_device;
extern const device_t ps1_hdc_device;
#endif
extern void machine_ps2_m30_286_init(const machine_t *, void *);
extern void machine_ps2_model_50_init(const machine_t *, void *);
extern void machine_ps2_model_55sx_init(const machine_t *, void *);
extern void machine_ps2_model_70_type3_init(const machine_t *, void *);
extern void machine_ps2_model_70_type4_init(const machine_t *, void *);
extern void machine_ps2_model_80_init(const machine_t *, void *);
extern void m_ps2_m30_286_init(const machine_t *, void *);
extern void m_ps2_model_50_init(const machine_t *, void *);
extern void m_ps2_model_55sx_init(const machine_t *, void *);
extern void m_ps2_model_70_type3_init(const machine_t *, void *);
extern void m_ps2_model_70_type4_init(const machine_t *, void *);
extern void m_ps2_model_80_init(const machine_t *, void *);
extern void machine_amstrad_1512_init(const machine_t *, void *);
extern void machine_amstrad_1640_init(const machine_t *, void *);
extern void machine_amstrad_200_init(const machine_t *, void *);
extern void machine_amstrad_2086_init(const machine_t *, void *);
extern void machine_amstrad_3086_init(const machine_t *, void *);
extern void machine_amstrad_mega_init(const machine_t *, void *);
extern void m_amstrad_1512_init(const machine_t *, void *);
extern void m_amstrad_1640_init(const machine_t *, void *);
extern void m_amstrad_200_init(const machine_t *, void *);
extern void m_amstrad_2086_init(const machine_t *, void *);
extern void m_amstrad_3086_init(const machine_t *, void *);
extern void m_amstrad_mega_init(const machine_t *, void *);
extern void machine_europc_init(const machine_t *, void *);
extern void m_europc_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_europc_device;
#endif
extern void machine_olim24_init(const machine_t *, void *);
extern void machine_olim24_video_init(void);
extern void m_olim24_init(const machine_t *, void *);
extern void m_olim24_video_init(void);
extern void machine_tandy1k_init(const machine_t *, void *);
extern void machine_tandy1k_hx_init(const machine_t *, void *);
extern void machine_tandy1k_sl2_init(const machine_t *, void *);
extern void m_tandy1k_init(const machine_t *, void *);
extern void m_tandy1k_hx_init(const machine_t *, void *);
extern void m_tandy1k_sl2_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_tandy1k_device;
extern const device_t m_tandy1k_hx_device;
@@ -229,32 +231,32 @@ extern const device_t m_tandy1k_sl2_device;
#endif
extern int tandy1k_eeprom_read(void);
extern void machine_zenith_supersport_init(const machine_t *, void *);
extern void m_zenith_supersport_init(const machine_t *, void *);
extern void machine_pc_init(const machine_t *, void *);
extern void machine_pc82_init(const machine_t *, void *);
extern void machine_xt_init(const machine_t *, void *);
extern void machine_xt86_init(const machine_t *, void *);
extern void m_pc_init(const machine_t *, void *);
extern void m_pc82_init(const machine_t *, void *);
extern void m_xt_init(const machine_t *, void *);
extern void m_xt86_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_pc_device;
extern const device_t m_xt_device;
#endif
extern void machine_xt_compaq_p1_init(const machine_t *, void *);
extern void m_xt_compaq_p1_init(const machine_t *, void *);
extern void machine_xt_laserxt_init(const machine_t *, void *);
extern void machine_xt_lxt3_init(const machine_t *, void *);
extern void m_xt_laserxt_init(const machine_t *, void *);
extern void m_xt_lxt3_init(const machine_t *, void *);
extern void machine_xt_t1000_init(const machine_t *, void *);
extern void m_xt_t1000_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_xt_t1000_device;
extern const device_t t1000_video_device;
extern const device_t t1200_video_device;
#endif
extern void machine_xt_t1200_init(const machine_t *, void *);
extern void machine_xt_t1x00_close(void);
extern void m_xt_t1200_init(const machine_t *, void *);
extern void m_xt_t1x00_close(void);
extern void machine_xt_xi8088_init(const machine_t *, void *);
extern void m_xt_xi8088_init(const machine_t *, void *);
#ifdef EMU_DEVICE_H
extern const device_t m_xi8088_device;
#endif

190
src/machines/machine_table.c
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine_table.c 1.0.33 2019/02/12
* Version: @(#)machine_table.c 1.0.34 2019/02/16
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -63,149 +63,149 @@
const machine_t machines[] = {
/* 8088 */
{ "[8088] IBM PC (1981)", "ibm_pc", L"ibm/pc", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 16, 256, 16, 0, machine_pc_init, &m_pc_device, NULL },
{ "[8088] IBM PC (1982)", "ibm_pc82", L"ibm/pc82", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 256, 32, 0, machine_pc82_init, &m_pc_device, NULL },
{ "[8088] IBM PCjr", "ibm_pcjr", L"ibm/pcjr", {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_pcjr_init, &m_pcjr_device, NULL },
{ "[8088] IBM XT (1982)", "ibm_xt", L"ibm/xt", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, &m_xt_device, NULL },
{ "[8088] IBM XT (1986)", "ibm_xt86", L"ibm/xt86", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt86_init, &m_xt_device, NULL },
{ "[8088] IBM PC (1981)", "ibm_pc", L"ibm/pc", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 16, 256, 16, 0, m_pc_init, &m_pc_device, NULL },
{ "[8088] IBM PC (1982)", "ibm_pc82", L"ibm/pc82", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 256, 32, 0, m_pc82_init, &m_pc_device, NULL },
{ "[8088] IBM PCjr", "ibm_pcjr", L"ibm/pcjr", -1, {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, m_pcjr_init, &m_pcjr_device, NULL },
{ "[8088] IBM XT (1982)", "ibm_xt", L"ibm/xt", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, &m_xt_device, NULL },
{ "[8088] IBM XT (1986)", "ibm_xt86", L"ibm/xt86", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt86_init, &m_xt_device, NULL },
{ "[8088] AMI XT (generic)", "ami_xt", L"generic/xt/ami", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, &m_xt_device, NULL },
{ "[8088] Award XT (generic)", "awd_xt", L"generic/xt/award", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, &m_xt_device, NULL },
{ "[8088] Phoenix XT (generic)", "phoenix_xt", L"generic/xt/phoenix", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL, NULL },
{ "[8088] AMI XT (generic)", "ami_xt", L"generic/xt/ami", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, &m_xt_device, NULL },
{ "[8088] Award XT (generic)", "awd_xt", L"generic/xt/award", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, &m_xt_device, NULL },
{ "[8088] Phoenix XT (generic)", "phoenix_xt", L"generic/xt/phoenix", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, NULL, NULL },
{ "[8088] OpenXT (generic)", "open_xt", L"generic/xt/open_xt", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"Intel", cpus_186}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, &m_xt_device, NULL },
{ "[8088] OpenXT (generic)", "open_xt", L"generic/xt/open_xt", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"Intel", cpus_186}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, &m_xt_device, NULL },
{ "[8088] Compaq Portable", "compaq_portable", L"compaq/portable", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_p1_init, NULL, NULL },
{ "[8088] DTK XT", "dtk_xt", L"dtk/xt", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, &m_xt_device, NULL },
{ "[8088] Juko XT", "juko_pc", L"juko/pc", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL, NULL },
{ "[8088] Schneider EuroPC", "schneider_europc", L"schneider/europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 16, machine_europc_init, NULL, NULL },
{ "[8088] Tandy 1000", "tandy_1000", L"tandy/t1000", {{"Intel", cpus_europc}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_tandy1k_init, &m_tandy1k_device, NULL },
{ "[8088] Tandy 1000 HX", "tandy_1000hx", L"tandy/t1000hx", {{"Intel", cpus_europc}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 256, 640, 128, 0, machine_tandy1k_hx_init, &m_tandy1k_hx_device, NULL },
{ "[8088] Toshiba T1000", "toshiba_t1000", L"toshiba/t1000", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 64, machine_xt_t1000_init, &m_xt_t1000_device, machine_xt_t1x00_close },
{ "[8088] VTech Laser Turbo XT", "vtech_ltxt", L"vtech/ltxt", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, machine_xt_laserxt_init, NULL, NULL },
{ "[8088] Xi8088", "malinov_xi8088", L"malinov/xi8088", {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA /*| MACDHINE_AT*/ | MACHINE_PS2, 64, 1024, 128, 128, machine_xt_xi8088_init, NULL, NULL },
{ "[8088] Zenith Data SupersPORT", "zenith_supersport", L"zenith/supersport", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 128, 640, 128, 0, machine_zenith_supersport_init, NULL, NULL },
{ "[8088] Compaq Portable", "compaq_portable", L"compaq/portable", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, m_xt_compaq_p1_init, NULL, NULL },
{ "[8088] DTK XT", "dtk_xt", L"dtk/xt", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, &m_xt_device, NULL },
{ "[8088] Juko XT", "juko_pc", L"juko/pc", 0, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, m_xt_init, NULL, NULL },
{ "[8088] Schneider EuroPC", "schneider_europc", L"schneider/europc", 0, {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 16, m_europc_init, NULL, NULL },
{ "[8088] Tandy 1000", "tandy_1000", L"tandy/t1000", -1, {{"Intel", cpus_europc}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, m_tandy1k_init, &m_tandy1k_device, NULL },
{ "[8088] Tandy 1000 HX", "tandy_1000hx", L"tandy/t1000hx", -1, {{"Intel", cpus_europc}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 256, 640, 128, 0, m_tandy1k_hx_init, &m_tandy1k_hx_device, NULL },
{ "[8088] Toshiba T1000", "toshiba_t1000", L"toshiba/t1000", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 64, m_xt_t1000_init, &m_xt_t1000_device, m_xt_t1x00_close },
{ "[8088] VTech Laser Turbo XT", "vtech_ltxt", L"vtech/ltxt", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, m_xt_laserxt_init, NULL, NULL },
{ "[8088] Xi8088", "malinov_xi8088", L"malinov/xi8088", -1, {{"Intel", cpus_8088}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA /*| MACDHINE_AT*/ | MACHINE_PS2, 64, 1024, 128, 128, m_xt_xi8088_init, NULL, NULL },
{ "[8088] Zenith Data SupersPORT", "zenith_supersport", L"zenith/supersport", -1, {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 128, 640, 128, 0, m_zenith_supersport_init, NULL, NULL },
/* 8086 */
{ "[8086] Amstrad PC1512", "amstrad_pc1512", L"amstrad/pc1512", {{"Intel", cpus_pc1512}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, machine_amstrad_1512_init, NULL, NULL },
{ "[8086] Amstrad PC1640", "amstrad_pc1640", L"amstrad/pc1640", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, machine_amstrad_1640_init, NULL, NULL },
{ "[8086] Amstrad PC2086", "amstrad_pc2086", L"amstrad/pc2086", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, machine_amstrad_2086_init, NULL, NULL },
{ "[8086] Amstrad PC3086", "amstrad_pc3086", L"amstrad/pc3086", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, machine_amstrad_3086_init, NULL, NULL },
{ "[8086] Amstrad PC20(0)", "amstrad_pc200", L"amstrad/pc200", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, machine_amstrad_200_init, NULL, NULL },
{ "[8086] Olivetti M24", "olivetti_m24", L"olivetti/m24", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy_1000sl2", L"tandy/t1000sl2", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, machine_tandy1k_sl2_init, &m_tandy1k_sl2_device, NULL },
{ "[8086] Toshiba T1200", "toshiba_t1200", L"toshiba/t1200", {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_HDC, 1024, 2048,1024, 64, machine_xt_t1200_init, &t1200_video_device, machine_xt_t1x00_close },
{ "[8086] VTech Laser XT3", "vtech_lxt3", L"vtech/lxt3", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, machine_xt_lxt3_init, NULL, NULL },
{ "[8086] Amstrad PC1512", "amstrad_pc1512", L"amstrad/pc1512", -1, {{"Intel", cpus_pc1512}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, m_amstrad_1512_init, NULL, NULL },
{ "[8086] Amstrad PC1640", "amstrad_pc1640", L"amstrad/pc1640", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, m_amstrad_1640_init, NULL, NULL },
{ "[8086] Amstrad PC2086", "amstrad_pc2086", L"amstrad/pc2086", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, m_amstrad_2086_init, NULL, NULL },
{ "[8086] Amstrad PC3086", "amstrad_pc3086", L"amstrad/pc3086", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 64, m_amstrad_3086_init, NULL, NULL },
{ "[8086] Amstrad PC20(0)", "amstrad_pc200", L"amstrad/pc200", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 64, m_amstrad_200_init, NULL, NULL },
{ "[8086] Olivetti M24", "olivetti_m24", L"olivetti/m24", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, m_olim24_init, NULL, NULL },
{ "[8086] Tandy 1000 SL/2", "tandy_1000sl2", L"tandy/t1000sl2", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, m_tandy1k_sl2_init, &m_tandy1k_sl2_device, NULL },
{ "[8086] Toshiba T1200", "toshiba_t1200", L"toshiba/t1200", -1, {{"Intel", cpus_8086}, {"NEC", cpus_nec}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_HDC, 1024, 2048,1024, 64, m_xt_t1200_init, &t1200_video_device, m_xt_t1x00_close },
{ "[8086] VTech Laser XT3", "vtech_lxt3", L"vtech/lxt3", -1, {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 640, 256, 0, m_xt_lxt3_init, NULL, NULL },
/* 80286 */
{ "[286 ISA] IBM AT", "ibm_at", L"ibm/at", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 64, machine_at_ibm_init, NULL, NULL },
{ "[286 ISA] IBM XT Model 286", "ibm_xt286", L"ibm/xt286", {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 128, machine_at_ibm_init, NULL, NULL },
{ "[286 ISA] IBM PS/1 model 2011", "ibm_ps1_2011", L"ibm/ps1_2011", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 512, 6144, 512, 64, machine_ps1_m2011_init, &m_ps1_device, NULL },
{ "[286 ISA] IBM PS/2 model 30-286", "ibm_ps2_m30_286", L"ibm/ps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 16, 1, 64, machine_ps2_m30_286_init, NULL, NULL },
{ "[286 ISA] IBM AT", "ibm_at", L"ibm/at", -1, {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 64, m_at_ibm_init, NULL, NULL },
{ "[286 ISA] IBM XT Model 286", "ibm_xt286", L"ibm/xt286", -1, {{"", cpus_ibmxt286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 128, m_at_ibm_init, NULL, NULL },
{ "[286 ISA] IBM PS/1 model 2011", "ibm_ps1_2011", L"ibm/ps1_2011", -1, {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 512, 6144, 512, 64, m_ps1_m2011_init, &m_ps1_device, NULL },
{ "[286 ISA] IBM PS/2 model 30-286", "ibm_ps2_m30_286", L"ibm/ps2_m30_286", -1, {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 16, 1, 64, m_ps2_m30_286_init, NULL, NULL },
{ "[286 ISA] AMI 286 (generic)", "ami_286", L"generic/at/ami", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 128, machine_at_neat_ami_init, NULL, NULL },
{ "[286 ISA] Award 286 (generic)", "award_286", L"generic/at/award", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, machine_at_scat_init, NULL, NULL },
{ "[286 ISA] AMI 286 (generic)", "ami_286", L"generic/at/ami", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 128, m_at_neat_ami_init, NULL, NULL },
{ "[286 ISA] Award 286 (generic)", "award_286", L"generic/at/award", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, m_at_scat_init, NULL, NULL },
{ "[286 ISA] Commodore PC 30 III", "commodore_pc30", L"commodore/pc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 128, machine_at_cmdpc_init, NULL, NULL },
{ "[286 ISA] Compaq Portable II", "compaq_portable2", L"compaq/portable2", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 128, machine_at_compaq_p2_init, NULL, NULL },
{ "[286 ISA] Commodore PC 30 III", "commodore_pc30", L"commodore/pc30", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 128, m_at_cmdpc_init, NULL, NULL },
{ "[286 ISA] Compaq Portable II", "compaq_portable2", L"compaq/portable2", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 128, m_at_compaq_p2_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[286 ISA] Compaq Portable III", "compaq_portable3", L"compaq/portable3", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 128, machine_at_compaq_p3_init, NULL, NULL },
{ "[286 ISA] Compaq Portable III", "compaq_portable3", L"compaq/portable3", 6, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 128, m_at_compaq_p3_init, NULL, NULL },
#endif
{ "[286 ISA] GW-286CT GEAR", "gw286ct", L"unknown/gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, machine_at_scat_gw286ct_init, NULL, NULL },
{ "[286 ISA] Hyundai Super-286TR", "hyundai_super286tr", L"hyundai/super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, machine_at_scat_init, NULL, NULL },
{ "[286 ISA] Samsung SPC-4200P", "samsung_spc4200p", L"samsung/spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 128, machine_at_scat_init, NULL, NULL },
{ "[286 ISA] Samsung SPC-4216P", "samsung_spc4216p", L"samsung/spc4216p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 128, machine_at_scat_spc4216p_init, NULL, NULL },
{ "[286 ISA] Toshiba T3100e", "toshiba_t3100e", L"toshiba/t3100e", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1024, 5120, 256, 64, machine_at_t3100e_init, NULL, NULL },
{ "[286 ISA] Trigem 286M", "tg286m", L"trigem/tg286m", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 128, machine_at_tg286m_init, NULL, NULL },
{ "[286 ISA] GW-286CT GEAR", "gw286ct", L"unknown/gw286ct", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, m_at_scat_gw286ct_init, NULL, NULL },
{ "[286 ISA] Hyundai Super-286TR", "hyundai_super286tr", L"hyundai/super286tr", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 128, m_at_scat_init, NULL, NULL },
{ "[286 ISA] Samsung SPC-4200P", "samsung_spc4200p", L"samsung/spc4200p", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 512, 2048, 128, 128, m_at_scat_init, NULL, NULL },
{ "[286 ISA] Samsung SPC-4216P", "samsung_spc4216p", L"samsung/spc4216p", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 1, 5, 1, 128, m_at_scat_spc4216p_init, NULL, NULL },
{ "[286 ISA] Toshiba T3100e", "toshiba_t3100e", L"toshiba/t3100e", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1024, 5120, 256, 64, m_at_t3100e_init, NULL, NULL },
{ "[286 ISA] Trigem 286M", "tg286m", L"trigem/tg286m", 8, {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 128, m_at_tg286m_init, NULL, NULL },
{ "[286 MCA] IBM PS/2 model 50", "ibm_ps2_m50", L"ibm/ps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 10, 1, 64, machine_ps2_model_50_init, NULL, NULL },
{ "[286 MCA] IBM PS/2 model 50", "ibm_ps2_m50", L"ibm/ps2_m50", -1, {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 10, 1, 64, m_ps2_model_50_init, NULL, NULL },
/* 80386SX */
{ "[386SX ISA] IBM PS/1 model 2121", "ibm_ps1_2121", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 64, machine_ps1_m2121_init, &m_ps1_device, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", "ibm_ps1_2121_isa", L"ibm/ps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 64, machine_ps1_m2121_init, &m_ps1_device, NULL },
{ "[386SX ISA] IBM PS/1 model 2121", "ibm_ps1_2121", L"ibm/ps1_2121", -1, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 64, m_ps1_m2121_init, &m_ps1_device, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", "ibm_ps1_2121_isa", L"ibm/ps1_2121", -1, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 64, m_ps1_m2121_init, &m_ps1_device, NULL },
{ "[386SX ISA] AMI 386SX", "ami_386sx", L"headland/386sx/ami", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 128, machine_at_headland_init, NULL, NULL },
{ "[386SX ISA] AMI 386SX (OPTi495)", "ami_386sx_opti495", L"opti495/ami", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, machine_at_opti495_ami_init, NULL, NULL },
{ "[386SX ISA] Award 386SX (Opti495)", "award_386sx_opti495", L"opti495/award", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, machine_at_opti495_award_init, NULL, NULL },
{ "[386SX ISA] MR 386SX (OPTi495)", "mr_386sx_opti495", L"opti495/mr", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, machine_at_opti495_mr_init, NULL },
{ "[386SX ISA] AMI 386SX", "ami_386sx", L"headland/386sx/ami", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 128, m_at_headland_init, NULL, NULL },
{ "[386SX ISA] AMI 386SX (OPTi495)", "ami_386sx_opti495", L"opti495/ami", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, m_at_opti495_ami_init, NULL, NULL },
{ "[386SX ISA] Award 386SX (Opti495)", "award_386sx_opti495", L"opti495/award", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, m_at_opti495_award_init, NULL, NULL },
{ "[386SX ISA] MR 386SX (OPTi495)", "mr_386sx_opti495", L"opti495/mr", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 128, m_at_opti495_mr_init, NULL, NULL },
{ "[386SX ISA] Amstrad MegaPC", "amstrad_megapc", L"amstrad/megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 16, 1, 128, machine_at_wd76c10_init, NULL, NULL },
{ "[386SX ISA] Arche AMA-932J", "arche_ama932j", L"arche/ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 128, machine_at_ama932j_init, &oti067_onboard_device, NULL },
{ "[386SX ISA] DTK 386SX clone", "dtk_386", L"dtk/386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 128, machine_at_neat_init, NULL, NULL },
{ "[386SX ISA] KMX-C-02", "kmxc02", L"unknown/kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 128, machine_at_scatsx_init, NULL, NULL },
{ "[386SX ISA] Amstrad MegaPC", "amstrad_megapc", L"amstrad/megapc", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 16, 1, 128, m_at_wd76c10_init, NULL, NULL },
{ "[386SX ISA] Arche AMA-932J", "arche_ama932j", L"arche/ama932j", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 128, m_at_ama932j_init, &oti067_onboard_device, NULL },
{ "[386SX ISA] DTK 386SX clone", "dtk_386", L"dtk/386", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 128, m_at_neat_init, NULL, NULL },
{ "[386SX ISA] KMX-C-02", "kmxc02", L"unknown/kmxc02", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 128, m_at_scatsx_init, NULL, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", "ibm_ps2_m55sx", L"ibm/ps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 8, 1, 64, machine_ps2_model_55sx_init, NULL, NULL },
{ "[386SX MCA] IBM PS/2 model 55SX", "ibm_ps2_m55sx", L"ibm/ps2_m55sx", 16, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 8, 1, 64, m_ps2_model_55sx_init, NULL, NULL },
/* 80386DX */
{ "[386DX ISA] AMI 386DX (Opti495)", "ami_386dx_opti495", L"opti495/ami", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_ami_init, NULL, NULL },
{ "[386DX ISA] Award 386DX (Opti495)", "award_386dx_opti495", L"opti495/award", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_award_init, NULL, NULL },
{ "[386DX ISA] MR 386DX (Opti495)", "mr_386dx_opti495", L"opti495/mr", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_mr_init, NULL, NULL },
{ "[386DX ISA] AMI 386DX (Opti495)", "ami_386dx_opti495", L"opti495/ami", 0, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_opti495_ami_init, NULL, NULL },
{ "[386DX ISA] Award 386DX (Opti495)", "award_386dx_opti495", L"opti495/award", 0, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_opti495_award_init, NULL, NULL },
{ "[386DX ISA] MR 386DX (Opti495)", "mr_386dx_opti495", L"opti495/mr", 0, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_opti495_mr_init, NULL, NULL },
{ "[386DX ISA] Amstrad MegaPC 386DX", "amstrad_megapc_dx", L"amstrad/megapc", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 32, 1, 128, machine_at_wd76c10_init, NULL, NULL },
{ "[386DX ISA] Amstrad MegaPC 386DX", "amstrad_megapc_dx", L"amstrad/megapc", 0, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 32, 1, 128, m_at_wd76c10_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[386DX ISA] Compaq Portable III (386)", "portable3_386", L"compaq/deskpro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, machine_at_compaq_p3_386_init, NULL, NULL },
{ "[386DX ISA] Compaq Portable III (386)", "portable3_386", L"compaq/deskpro386", -1, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 128, m_at_compaq_p3_386_init, NULL, NULL },
#endif
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type3_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 80", "ibm_ps2_m80", L"ibm/ps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 12, 1, 64, machine_ps2_model_80_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 70 (type 3)", "ibm_ps2_m70_type3", L"ibm/ps2_m70_type3", -1, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 2, 16, 2, 64, m_ps2_model_70_type3_init, NULL, NULL },
{ "[386DX MCA] IBM PS/2 model 80", "ibm_ps2_m80", L"ibm/ps2_m80", -1, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC_PS2, 1, 12, 1, 64, m_ps2_model_80_init, NULL, NULL },
/* 80486 */
{ "[486 ISA] IBM PS/1 model 2133", "ibm_ps1_2133", L"ibm/ps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI, 1, 64, 1, 128, machine_ps1_m2133_init, NULL, NULL },
{ "[486 ISA] IBM PS/1 model 2133", "ibm_ps1_2133", L"ibm/ps1_2133", -1, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI, 1, 64, 1, 128, m_ps1_m2133_init, NULL, NULL },
{ "[486 ISA] AMI 486 (ALi1429)", "ami_486_ali1429", L"ali1429/ami", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, NULL },
{ "[486 ISA] AMI 486 (ALi1429)", "ami_486_ali1429", L"ali1429/ami", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_ali1429_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_SIS471)
{ "[486 ISA] AMI 486 (SiS471)", "ami_486_sis471", L"sis471/ami", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_sis471_ami_init, NULL, NULL },
{ "[486 ISA] AMI 486 (SiS471)", "ami_486_sis471", L"sis471/ami", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, m_at_sis471_ami_init, NULL, NULL },
#endif
{ "[486 ISA] AMI WinBIOS486 (ALi1429)", "ami_win486_ali1429", L"ali1429/ami_win", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_ali1429_init, NULL, NULL },
{ "[486 ISA] Award 486 (Opti495)", "award_486_opti495", L"opti495/award", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_award_init, NULL, NULL },
{ "[486 ISA] MR 486 (Opti495)", "mr_486dx_opti495", L"opti495/mr", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, machine_at_opti495_mr_init, NULL, NULL },
{ "[486 ISA] AMI WinBIOS486 (ALi1429)", "ami_win486_ali1429", L"ali1429/ami_win", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_ali1429_init, NULL, NULL },
{ "[486 ISA] Award 486 (Opti495)", "award_486_opti495", L"opti495/award", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_opti495_award_init, NULL, NULL },
{ "[486 ISA] MR 486 (Opti495)", "mr_486dx_opti495", L"opti495/mr", 0, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 128, m_at_opti495_mr_init, NULL, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", "dtk_486", L"dtk/486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, machine_at_dtk486_init, NULL, NULL },
{ "[486 ISA] DTK PKM-0038S E-2", "dtk_486", L"dtk/486", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 128, m_at_dtk486_init, NULL, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, machine_ps2_model_70_type4_init, NULL, NULL },
{ "[486 MCA] IBM PS/2 model 70 (type 4)", "ibm_ps2_m70_type4", L"ibm/ps2_m70_type4", -1, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 2, 16, 2, 64, m_ps2_model_70_type4_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_SIS496)
{ "[486 PCI] AMI 486 (SiS496)", "ami_486_sis496", L"sis496/ami", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_sis496_ami_init, NULL, NULL },
{ "[486 PCI] AMI 486 (SiS496)", "ami_486_sis496", L"sis496/ami", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, m_at_sis496_ami_init, NULL, NULL },
#endif
{ "[486 PCI] Rise Computer R418", "rise_r418", L"rise/r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, machine_at_r418_init, NULL, NULL },
{ "[486 PCI] Rise Computer R418", "rise_r418", L"rise/r418", 0, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 128, m_at_r418_init, NULL, NULL },
/* Pentium, Socket4 (LX) */
{ "[Socket 4 LX] Intel Premiere/PCI", "intel_revenge", L"intel/revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 128, machine_at_batman_init, NULL, NULL },
{ "[Socket 4 LX] Intel Premiere/PCI", "intel_revenge", L"intel/revenge", -1, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 128, m_at_batman_init, NULL, NULL },
/* Pentium, Socket5 (NX) */
{ "[Socket 5 NX] Intel Premiere/PCI II", "intel_plato", L"intel/plato", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 128, machine_at_plato_init, NULL, NULL },
{ "[Socket 5 NX] Intel Premiere/PCI II", "intel_plato", L"intel/plato", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 128, m_at_plato_init, NULL, NULL },
/* Pentium, Socket5 (FX) */
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", "asus_p54tp4xe", L"asus/p54tp4xe", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, machine_at_p54tp4xe_init, NULL, NULL },
{ "[Socket 5 FX] Intel Advanced/ZP", "intel_zappa", L"intel/zappa", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_zappa_init, NULL, NULL },
{ "[Socket 5 FX] PC Partner MB500N", "pcpartner_mb500n", L"pcpartner/mb500n", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, machine_at_mb500n_init, NULL, NULL },
{ "[Socket 5 FX] President Award 430FX PCI","president", L"president/president", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, machine_at_president_init, NULL, NULL },
{ "[Socket 5 FX] ASUS P/I-P54TP4XE", "asus_p54tp4xe", L"asus/p54tp4xe", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, m_at_p54tp4xe_init, NULL, NULL },
{ "[Socket 5 FX] Intel Advanced/ZP", "intel_zappa", L"intel/zappa", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_zappa_init, NULL, NULL },
{ "[Socket 5 FX] PC Partner MB500N", "pcpartner_mb500n", L"pcpartner/mb500n", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, m_at_mb500n_init, NULL, NULL },
{ "[Socket 5 FX] President Award 430FX PCI","president", L"president/president", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K5, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 128, m_at_president_init, NULL, NULL },
/* Pentium, Socket7 (FX) */
{ "[Socket 7 FX] Intel Advanced/ATX", "intel_thor", L"intel/thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, NULL },
{ "[Socket 7 FX] MR Intel Advanced/ATX", "intel_thor_mr", L"intel/thor_mr", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_thor_init, NULL, NULL },
{ "[Socket 7 FX] Intel Advanced/EV", "intel_endeavor", L"intel/endeavor", {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 128, machine_at_endeavor_init, &s3_phoenix_trio64_onboard_pci_device, NULL },
{ "[Socket 7 FX] Packard Bell PB640", "pbell_pb640", L"pbell/pb640", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 128, machine_at_pb640_init, &gd5440_onboard_pci_device, NULL },
{ "[Socket 7 FX] Intel Advanced/ATX", "intel_thor", L"intel/thor", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_thor_init, NULL, NULL },
{ "[Socket 7 FX] MR Intel Advanced/ATX", "intel_thor_mr", L"intel/thor_mr", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_thor_init, NULL, NULL },
{ "[Socket 7 FX] Intel Advanced/EV", "intel_endeavor", L"intel/endeavor", -1, {{"Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 128, m_at_endeavor_init, &s3_phoenix_trio64_onboard_pci_device, NULL },
{ "[Socket 7 FX] Packard Bell PB640", "pbell_pb640", L"pbell/pb640", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 128, m_at_pb640_init, &gd5440_onboard_pci_device, NULL },
/* Pentium, Socket7 (HX) */
{ "[Socket 7 HX] Acer M3a", "acer_m3a", L"acer/m3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerm3a_init, NULL, NULL },
{ "[Socket 7 HX] Acer V35n", "acer_v35n", L"acer/v35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, machine_at_acerv35n_init, NULL, NULL },
{ "[Socket 7 HX] AOpen AP53", "aopen_ap53", L"aopen/ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 128, machine_at_ap53_init, NULL, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", "asus_p55t2p4", L"asus/p55t2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 128, machine_at_p55t2p4_init, NULL, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", "supermicro_p55t2s", L"supermicro/p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 128, machine_at_p55t2s_init, NULL, NULL },
{ "[Socket 7 HX] Acer M3a", "acer_m3a", L"acer/m3a", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, m_at_acerm3a_init, NULL, NULL },
{ "[Socket 7 HX] Acer V35n", "acer_v35n", L"acer/v35n", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 128, m_at_acerv35n_init, NULL, NULL },
{ "[Socket 7 HX] AOpen AP53", "aopen_ap53", L"aopen/ap53", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 128, m_at_ap53_init, NULL, NULL },
{ "[Socket 7 HX] ASUS P/I-P55T2P4", "asus_p55t2p4", L"asus/p55t2p4", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 128, m_at_p55t2p4_init, NULL, NULL },
{ "[Socket 7 HX] SuperMicro Super P55T2S", "supermicro_p55t2s", L"supermicro/p55t2s", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 128, m_at_p55t2s_init, NULL, NULL },
/* Pentium, Socket7 (VX) */
{ "[Socket 7 VX] ASUS P/I-P55TVP4", "asus_p55tvp4", L"asus/p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_p55tvp4_init, NULL, NULL },
{ "[Socket 7 VX] Award 430VX PCI", "award_430vx", L"generic/430vx/award", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_i430vx_init, NULL, NULL },
{ "[Socket 7 VX] Epox P55-VA", "epox_p55va", L"epox/p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_p55va_init, NULL, NULL },
{ "[Socket 7 VX] Jetway J656VXD", "jetway_j656vxd", L"jetway/j656vxd", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, machine_at_j656vxd_init, NULL, NULL },
{ "[Socket 7 VX] ASUS P/I-P55TVP4", "asus_p55tvp4", L"asus/p55tvp4", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_p55tvp4_init, NULL, NULL },
{ "[Socket 7 VX] Award 430VX PCI", "award_430vx", L"generic/430vx/award", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_i430vx_init, NULL, NULL },
{ "[Socket 7 VX] Epox P55-VA", "epox_p55va", L"epox/p55va", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_p55va_init, NULL, NULL },
{ "[Socket 7 VX] Jetway J656VXD", "jetway_j656vxd", L"jetway/j656vxd", -1, {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, CPU_AMD_K56, {"Cyrix", cpus_6x86}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 128, m_at_j656vxd_init, NULL, NULL },
#if defined(DEV_BRANCH) && defined(USE_I686)
/* Pentium, Socket5 */
{ "[Socket 8 FX] Tyan Titan-Pro AT", "tyan_440fx", L"tyan/440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 128, machine_at_i440fx_init, NULL, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tyan_tpatx", L"tyan/tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 128, machine_at_s1668_init, NULL, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro AT", "tyan_440fx", L"tyan/440fx", -1, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 128, m_at_i440fx_init, NULL, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tyan_tpatx", L"tyan/tpatx", -1, {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 128, m_at_s1668_init, NULL, NULL },
#endif
{ NULL, NULL, NULL, {{"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
{ NULL, NULL, NULL, -1, {{"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL }
};

49
src/pc.c
View File

@@ -8,7 +8,7 @@
*
* Main emulator module where most things are controlled.
*
* Version: @(#)pc.c 1.0.64 2019/02/15
* Version: @(#)pc.c 1.0.65 2019/02/28
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -341,7 +341,7 @@ fatal(const char *fmt, ...)
config_save();
dumppic();
pic_dump();
dumpregs(1);
/*
@@ -735,13 +735,39 @@ usage:
}
/* Set the active processor speed for this machine. */
void
pc_set_speed(void)
{
if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286)
pit_setclock(machine_speed());
else
pit_setclock(14318184);
uint32_t speed;
int turbo = 1; /* for now */
/*
* Get the selected processor's desired speed.
*
* For 286+, this is usually 8 (slow) or max speed.
* For PC and XT class, this will return max speed.
*/
speed = machine_speed(turbo);
INFO("PC: set_speed(%d): speed=%lu\n", speed);
if (machine_type() >= CPU_286) {
/* For 286+, we are done. */
pit_setclock(speed);
} else {
/*
* Not so easy for PC and XT class machines.
*
* The TURBO setting on these machines (if they had
* one at all) basically is the maximum speed of the
* selected processor. The slow speed is, in pretty
* much all cases, the original 4.77MHz setting.
*/
if (turbo)
pit_setclock(14318184);
else
pit_setclock(14318184);
}
}
@@ -867,7 +893,7 @@ pc_init(void)
* video card are available, so we can proceed with the
* initialization of things.
*/
cpuspeed2 = (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286) ? 2 : 1;
cpuspeed2 = (machine_type() >= CPU_286) ? 2 : 1;
atfullspeed = 0;
random_init();
@@ -934,7 +960,7 @@ pc_close(thread_t *ptr)
// floppy_close();
if (dump_on_exit)
dumppic();
pic_dump();
dumpregs(0);
video_close();
@@ -1009,7 +1035,7 @@ pc_reset_hard_init(void)
* For now, we will call their reset functions here, but
* that will be a call to device_reset_all() later !
*/
#if 0
#if 1
/* FIXME: move elsewhere? */
shadowbios = 0;
#endif
@@ -1137,7 +1163,8 @@ pc_thread(void *param)
/* Run a block of code. */
plat_startblit();
clockrate = machine_speed();
clockrate = machine_speed(1);
//INFO("PC: clockrate=%lu, cpuspeed=%lu\n", clockrate, cpuspeed);
if (is386) {
#ifdef USE_DYNAREC
@@ -1146,7 +1173,7 @@ pc_thread(void *param)
else
#endif
exec386(clockrate/100);
} else if (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type >= CPU_286) {
} else if (machine_type() >= CPU_286) {
exec386(clockrate/100);
} else {
execx86(clockrate/100);