+ @if(Model.Processors[i].Processor.ModelCode != null && Model.Processors[i].Processor.ModelCode != Model.Processors[i].Processor.Name)
+ {
+
+ | Model |
+ @Model.Processors[i].Processor.ModelCode |
+
+ }
+
+ | Manufacturer |
+
+
+ @Model.Processors[i].Processor.Company.Name
+ |
+
+ @if(Model.Processors[i].Processor.Introduced != DateTime.MinValue)
+ {
+
+ | Introduction date |
+ @($"{Model.Processors[i].Processor.Introduced:yyyy}") |
+
+ }
+ @if(Model.Processors[i].Processor.InstructionSet != null)
+ {
+
+ | Instruction set |
+ @Model.Processors[i].Processor.InstructionSet.Name |
+
+ }
+ @if(Model.Processors[i].Processor.Speed > 0)
+ {
+
+ | Nominal speed |
+ @Model.Processors[i].Processor.Speed MHz |
+
+ }
+ @if(Model.Processors[i].Processor.Gpr > 0 || Model.Processors[i].Processor.Fpr > 0 || Model.Processors[i].Processor.Simd > 0)
+ {
+
+ | Registers |
+
+
+ @if(Model.Processors[i].Processor.Gpr > 0)
+ {
+
+ |
+ @Model.Processors[i].Processor.Gpr general purpose registers of @Model.Processors[i].Processor.GprSize bits
+ @if(Model.Processors[i].Processor.FprSize > 0 && Model.Processors[i].Processor.Fpr == 0) { @($", that can be used as floating point registers of {Model.Processors[i].Processor.FprSize}") }
+ @if(Model.Processors[i].Processor.SimdSize > 0 && Model.Processors[i].Processor.Simd == 0) { @($", that can be used as SIMD registers of {Model.Processors[i].Processor.FprSize}") }
+ |
+
+ }
+ @if(Model.Processors[i].Processor.Fpr > 0)
+ {
+
+ |
+ @Model.Processors[i].Processor.Fpr floating-point registers of @Model.Processors[i].Processor.FprSize bits
+ @if(Model.Processors[i].Processor.SimdSize > 0 && Model.Processors[i].Processor.Simd == 0) { @($", that can be used as SIMD registers of {Model.Processors[i].Processor.FprSize}") }
+ |
+
+ }
+ @if(Model.Processors[i].Processor.Simd > 0)
+ {
+
+ |
+ @Model.Processors[i].Processor.Simd SIMDregisters of @Model.Processors[i].Processor.SimdSize bits
+ |
+
+ }
+
+ |
+
+ }
+ @if(Model.Processors[i].Processor.Cores > 1)
+ {
+
+ | Multi-core |
+ @Model.Processors[i].Processor.Cores cores |
+
+ }
+ @if(Model.Processors[i].Processor.Cores > 1)
+ {
+
+ |
+ SMT
+ |
+
+ @Model.Processors[i].Processor.ThreadsPerCore threads
+ @if(Model.Processors[i].Processor.Cores > 1) { @(" per core") }
+ |
+
+ }
+ @if(Model.Processors[i].Processor.DataBus > 0 || Model.Processors[i].Processor.AddressBus > 0)
+ {
+
+ | Bus |
+
+
+ @if(Model.Processors[i].Processor.DataBus > 0)
+ {
+
+ |
+ @Model.Processors[i].Processor.DataBus-bit data
+ |
+
+ }
+ @if(Model.Processors[i].Processor.AddressBus > 0)
+ {
+
+ |
+ @Model.Processors[i].Processor.AddressBus-bit address
+ |
+
+ }
+
+ |
+
+ }
- @if(Model.Cpu2.L1Instruction > 0 || Model.Cpu2.L1Data > 0 || Model.Cpu2.L2 > 0 || Model.Cpu2.L2 > 0)
- {
-
- | Cache |
-
-
- @if(Model.Cpu2.L1Instruction > 0)
- {
-
- |
- @(Model.Cpu2.L1Data < 0 ? $"{Model.Cpu2.L1Instruction}KiB combined instruction-data L1" : $"{Model.Cpu2.L1Instruction}KiB instruction L1")
- |
-
- }
- @if(Model.Cpu2.L1Data > 0)
- {
-
- |
- @($"{Model.Cpu2.L1Data}KiB data L1")
- |
-
- }
- @if(Model.Cpu2.L2 > 0)
- {
-
- |
- @($"{Model.Cpu2.L2}KiB L2")
- |
-
- }
- @if(Model.Cpu2.L3 > 0)
- {
-
- |
- @($"{Model.Cpu2.L3}KiB L3")
- |
-
- }
-
+ @if(Model.Processors[i].Processor.L1Instruction > 0 || Model.Processors[i].Processor.L1Data > 0 || Model.Processors[i].Processor.L2 > 0 || Model.Processors[i].Processor.L2 > 0)
+ {
+ |
+ | Cache |
+
+
+ @if(Model.Processors[i].Processor.L1Instruction > 0)
+ {
+
+ |
+ @(Model.Processors[i].Processor.L1Data < 0 ? $"{Model.Processors[i].Processor.L1Instruction}KiB combined instruction-data L1" : $"{Model.Processors[i].Processor.L1Instruction}KiB instruction L1")
+ |
+
+ }
+ @if(Model.Processors[i].Processor.L1Data > 0)
+ {
+
+ |
+ @($"{Model.Processors[i].Processor.L1Data}KiB data L1")
+ |
+
+ }
+ @if(Model.Processors[i].Processor.L2 > 0)
+ {
+
+ |
+ @($"{Model.Processors[i].Processor.L2}KiB L2")
+ |
+
+ }
+ @if(Model.Processors[i].Processor.L3 > 0)
+ {
+
+ |
+ @($"{Model.Processors[i].Processor.L3}KiB L3")
+ |
+
+ }
+
+ |
+
+ }
+ @if(Model.Processors[i].Processor.Package != null)
+ {
+
+ | Package |
+ @Model.Processors[i].Processor.Package |
+
+ }
+ @if(Model.Processors[i].Processor.Process != null || Model.Processors[i].Processor.ProcessNm > 0)
+ {
+
+ | Manufacturing process |
+
+ @if(Model.Processors[i].Processor.Process != null && Model.Processors[i].Processor.ProcessNm > 0)
+ {
+ @Model.Processors[i].Processor.Process
+ @("@")
+ @(Model.Processors[i].Processor.ProcessNm > 100 ? $"{Model.Processors[i].Processor.ProcessNm / 100}µm" : $"{Model.Processors[i].Processor.ProcessNm}nm")
+ }
+ else if(Model.Processors[i].Processor.ProcessNm > 0) { @(Model.Processors[i].Processor.ProcessNm > 100 ? $"{Model.Processors[i].Processor.ProcessNm / 100}µm" : $"{Model.Processors[i].Processor.ProcessNm}nm") }
+ else
+ { @Model.Processors[i].Processor.Process }
+ |
+
+ }
+ @if(Model.Processors[i].Processor.DieSize > 0)
+ {
+
+ | Die size |
+ @Model.Processors[i].Processor.DieSize mm² |
+
+ }
+ @if(Model.Processors[i].Processor.Transistors > 0)
+ {
+
+ | Transistors |
+ @Model.Processors[i].Processor.Transistors |
+
+ }
+