Major refactor and cleanup.

This commit is contained in:
2025-11-13 04:05:35 +00:00
parent 1d67081792
commit 8f6d334af4
833 changed files with 86800 additions and 74355 deletions

View File

@@ -29,69 +29,71 @@ using System.Collections.Generic;
using System.ComponentModel;
using System.ComponentModel.DataAnnotations;
namespace Marechai.Database.Models
namespace Marechai.Database.Models;
public class Processor : BaseModel<int>
{
public class Processor : BaseModel<int>
public Processor()
{
public Processor()
{
InstructionSetExtensions = new HashSet<InstructionSetExtensionsByProcessor>();
ProcessorsByMachine = new HashSet<ProcessorsByMachine>();
}
[Required, StringLength(50)]
public string Name { get; set; }
public int? CompanyId { get; set; }
[DisplayName("Model code"), StringLength(45)]
public string ModelCode { get; set; }
[DisplayFormat(DataFormatString = "{0:d}"), DataType(DataType.Date)]
public DateTime? Introduced { get; set; }
[DisplayName("Instruction set")]
public int? InstructionSetId { get; set; }
[DisplayName("Nominal speed (MHz)")]
public double? Speed { get; set; }
[StringLength(45)]
public string Package { get; set; }
[DisplayName("General Purpose Registers")]
public int? Gprs { get; set; }
[DisplayName("General Purporse Register size")]
public int? GprSize { get; set; }
[DisplayName("Floating Point Registers")]
public int? Fprs { get; set; }
[DisplayName("Floating Point Register Size")]
public int? FprSize { get; set; }
public int? Cores { get; set; }
[DisplayName("Threads per core")]
public int? ThreadsPerCore { get; set; }
[StringLength(45)]
public string Process { get; set; }
[DisplayName("Process (nm)")]
public float? ProcessNm { get; set; }
[DisplayName("Die size (mm²)")]
public float? DieSize { get; set; }
public long? Transistors { get; set; }
[DisplayName("Data bus size")]
public int? DataBus { get; set; }
[DisplayName("Address bus size")]
public int? AddrBus { get; set; }
[DisplayName("SIMD registers")]
public int? SimdRegisters { get; set; }
[DisplayName("SIMD register size")]
public int? SimdSize { get; set; }
[DisplayName("L1 instruction cache (KiB)")]
public float? L1Instruction { get; set; }
[DisplayName("L1 data cache (KiB)")]
public float? L1Data { get; set; }
[DisplayName("L2 cache (KiB)")]
public float? L2 { get; set; }
[DisplayName("L3 cache (KiB)")]
public float? L3 { get; set; }
public virtual Company Company { get; set; }
[DisplayName("Instruction set")]
public virtual InstructionSet InstructionSet { get; set; }
public virtual ICollection<InstructionSetExtensionsByProcessor> InstructionSetExtensions { get; set; }
public virtual ICollection<ProcessorsByMachine> ProcessorsByMachine { get; set; }
public virtual ICollection<ProcessorsBySoftwareVariant> Software { get; set; }
InstructionSetExtensions = new HashSet<InstructionSetExtensionsByProcessor>();
ProcessorsByMachine = new HashSet<ProcessorsByMachine>();
}
[Required]
[StringLength(50)]
public string Name { get; set; }
public int? CompanyId { get; set; }
[DisplayName("Model code")]
[StringLength(45)]
public string ModelCode { get; set; }
[DisplayFormat(DataFormatString = "{0:d}")]
[DataType(DataType.Date)]
public DateTime? Introduced { get; set; }
[DisplayName("Instruction set")]
public int? InstructionSetId { get; set; }
[DisplayName("Nominal speed (MHz)")]
public double? Speed { get; set; }
[StringLength(45)]
public string Package { get; set; }
[DisplayName("General Purpose Registers")]
public int? Gprs { get; set; }
[DisplayName("General Purporse Register size")]
public int? GprSize { get; set; }
[DisplayName("Floating Point Registers")]
public int? Fprs { get; set; }
[DisplayName("Floating Point Register Size")]
public int? FprSize { get; set; }
public int? Cores { get; set; }
[DisplayName("Threads per core")]
public int? ThreadsPerCore { get; set; }
[StringLength(45)]
public string Process { get; set; }
[DisplayName("Process (nm)")]
public float? ProcessNm { get; set; }
[DisplayName("Die size (mm²)")]
public float? DieSize { get; set; }
public long? Transistors { get; set; }
[DisplayName("Data bus size")]
public int? DataBus { get; set; }
[DisplayName("Address bus size")]
public int? AddrBus { get; set; }
[DisplayName("SIMD registers")]
public int? SimdRegisters { get; set; }
[DisplayName("SIMD register size")]
public int? SimdSize { get; set; }
[DisplayName("L1 instruction cache (KiB)")]
public float? L1Instruction { get; set; }
[DisplayName("L1 data cache (KiB)")]
public float? L1Data { get; set; }
[DisplayName("L2 cache (KiB)")]
public float? L2 { get; set; }
[DisplayName("L3 cache (KiB)")]
public float? L3 { get; set; }
public virtual Company Company { get; set; }
[DisplayName("Instruction set")]
public virtual InstructionSet InstructionSet { get; set; }
public virtual ICollection<InstructionSetExtensionsByProcessor> InstructionSetExtensions { get; set; }
public virtual ICollection<ProcessorsByMachine> ProcessorsByMachine { get; set; }
public virtual ICollection<ProcessorsBySoftwareVariant> Software { get; set; }
}