/****************************************************************************** // Canary Islands Computer Museum Website // ---------------------------------------------------------------------------- // // Filename : Processor.cs // Author(s) : Natalia Portillo // // --[ Description ] ---------------------------------------------------------- // // High level representation of a processor . // // --[ License ] -------------------------------------------------------------- // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as // published by the Free Software Foundation, either version 3 of the // License, or (at your option) any later version. // // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see . // // ---------------------------------------------------------------------------- // Copyright © 2003-2018 Natalia Portillo *******************************************************************************/ using System; namespace Cicm.Database.Schemas { /// Processor public class Processor { /// Size in bits of address bus with host (not interprocessor) public int AddressBus; /// Company public Company Company; /// How many processor cores per processor package public int Cores; /// Size in bits of data bus with host (not interprocessor) public int DataBus; /// Size of die in square milimeters public float DieSize; /// Number of available Floating Point Registers public int Fpr; /// Size in bits of FPRs public int FprSize; /// Number of available General Purpose Registers public int Gpr; /// Size in bits of GPRs public int GprSize; /// ID public int Id; /// Instruction set public InstructionSet InstructionSet; /// Extensions to the instruction set that are implemented in this processor public InstructionSetExtension[] InstructionSetExtensions; /// Datetime of introduction public DateTime Introduced; /// Size in kibibytes of L1 data cache. If -1, is size of L1 unified cache public float L1Data; /// Size in kibibytes of L1 instruction cache. If is -1, this is size of L1 unified cache public float L1Instruction; /// /// Size in kibibytes of L2 cache. It includes cache that's in same physical package but not in same chip die /// (e.g. Pentium II) /// public float L2; /// Size in kibibytes of L3 cache public float L3; /// Model/SKU code public string ModelCode; /// Name public string Name; /// Package public string Package; /// Name of litography process public string Process; /// Nanometers of litography process public float ProcessNm; /// Number of available SIMD registers public int Simd; /// Size in bits of SIMD registers public int SimdSize; /// Nominal speed, in MHz public double Speed; /// How many simultaneos threads can run on each processor core public int ThreadsPerCore; /// How many transistors in package public long Transistors; } }