From 192faac49cfae5752e71a2ddf72a0f27ba71418a Mon Sep 17 00:00:00 2001 From: Matt Sealey Date: Fri, 3 Dec 2010 01:27:44 -0600 Subject: [PATCH] put back accidentially removed original spi chipselect code for SPI_MXC --- arch/arm/mach-mx5/mx51_efikamx_spi.c | 60 ++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/mach-mx5/mx51_efikamx_spi.c b/arch/arm/mach-mx5/mx51_efikamx_spi.c index d58ff06a68b..1542052852c 100644 --- a/arch/arm/mach-mx5/mx51_efikamx_spi.c +++ b/arch/arm/mach-mx5/mx51_efikamx_spi.c @@ -66,6 +66,8 @@ static struct mxc_iomux_pin_cfg __initdata mx51_efikamx_spi_iomux_pins[] = { #if defined(CONFIG_SPI_MXC) +#if defined (PURE_GPIO_CHIPSELECTS) + /* mxc_spi chipselect pin twiddlers for pmic and nor flash */ void mx51_efikamx_spi_chipselect_active(int cspi_mode, int status, int chipselect) { @@ -93,6 +95,64 @@ void mx51_efikamx_spi_chipselect_inactive(int cspi_mode, int status, int chipsel } } +#elif + +}/* ecspi chipselect pin for pmic and nor flash */ +void mx51_efikamx_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, SPI_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), !(status & 0x02)); + break; + case 0x2: + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, SPI_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), !(status & 0x01)); + break; + default: + break; + } + break; + default: + break; + } +} + +void mx51_efikamx_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_free_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + break; + case 0x2: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + break; + default: + break; + } + break; + default: + break; + } + +} + +#endif + struct mxc_spi_master mx51_efikamx_spi_data = { .maxchipselect = 4, .spi_version = 23,