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[PATCH] powerpc: Merge bitops.h
Here's a revised version. This re-introduces the set_bits() function from ppc64, which I removed because I thought it was unused (it exists on no other arch). In fact it is used in the powermac interrupt code (but not on pSeries). - We use LARXL/STCXL macros to generate the right (32 or 64 bit) instructions, similar to LDL/STL from ppc_asm.h, used in fpu.S - ppc32 previously used a full "sync" barrier at the end of test_and_*_bit(), whereas ppc64 used an "isync". The merged version uses "isync", since I believe that's sufficient. - The ppc64 versions of then minix_*() bitmap functions have changed semantics. Previously on ppc64, these functions were big-endian (that is bit 0 was the LSB in the first 64-bit, big-endian word). On ppc32 (and x86, for that matter, they were little-endian. As far as I can tell, the big-endian usage was simply wrong - I guess no-one ever tried to use minixfs on ppc64. - On ppc32 find_next_bit() and find_next_zero_bit() are no longer inline (they were already out-of-line on ppc64). - For ppc64, sched_find_first_bit() has moved from mmu_context.h to the merged bitops. What it was doing in mmu_context.h in the first place, I have no idea. - The fls() function is now implemented using the cntlzw instruction on ppc64, instead of generic_fls(), as it already was on ppc32. - For ARCH=ppc, this patch requires adding arch/powerpc/lib to the arch/ppc/Makefile. This in turn requires some changes to arch/powerpc/lib/Makefile which didn't correctly handle ARCH=ppc. Built and running on G5. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
committed by
Paul Mackerras
Paul Mackerras
parent
031ef0a72a
commit
a0e60b2033
@@ -1,126 +0,0 @@
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/*
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* Copyright (C) 1996 Paul Mackerras.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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/*
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* If the bitops are not inlined in bitops.h, they are defined here.
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* -- paulus
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*/
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#if !__INLINE_BITOPS
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void set_bit(int nr, volatile void * addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%3 \n\
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or %0,%0,%2 \n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc" );
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}
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void clear_bit(int nr, volatile void *addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%3 \n\
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andc %0,%0,%2 \n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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}
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void change_bit(int nr, volatile void *addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%3 \n\
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xor %0,%0,%2 \n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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}
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int test_and_set_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%4 \n\
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or %1,%0,%3 \n"
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PPC405_ERR77(0,%4)
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" stwcx. %1,0,%4 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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int test_and_clear_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%4 \n\
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andc %1,%0,%3 \n"
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PPC405_ERR77(0,%4)
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" stwcx. %1,0,%4 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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int test_and_change_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\n\
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1: lwarx %0,0,%4 \n\
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xor %1,%0,%3 \n"
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PPC405_ERR77(0,%4)
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" stwcx. %1,0,%4 \n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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#endif /* !__INLINE_BITOPS */
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