mirror of
https://github.com/genesi/linux-legacy.git
synced 2026-09-24 15:44:22 +00:00
Merge /spare/repo/linux-2.6 into upstream
This commit is contained in:
@@ -104,6 +104,7 @@ enum s3c2410_chan_op_e {
|
||||
S3C2410_DMAOP_RESUME,
|
||||
S3C2410_DMAOP_FLUSH,
|
||||
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
|
||||
S3C2410_DMAOP_STARTED, /* indicate channel started */
|
||||
};
|
||||
|
||||
typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#ifndef __ASM_ARCH_REGS_RTC_H
|
||||
#define __ASM_ARCH_REGS_RTC_H __FILE__
|
||||
|
||||
#define S3C2410_RTCREG(x) ((x) + S3C24XX_VA_RTC)
|
||||
#define S3C2410_RTCREG(x) (x)
|
||||
|
||||
#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
|
||||
#define S3C2410_RTCCON_RTCEN (1<<0)
|
||||
|
||||
@@ -55,5 +55,6 @@ extern unsigned int elf_hwcap;
|
||||
#define HWCAP_VFP 64
|
||||
#define HWCAP_EDSP 128
|
||||
#define HWCAP_JAVA 256
|
||||
#define HWCAP_IWMMXT 512
|
||||
|
||||
#endif
|
||||
|
||||
@@ -14,7 +14,7 @@ extern struct pglist_data *node_data[];
|
||||
|
||||
#ifdef CONFIG_X86_NUMAQ
|
||||
#include <asm/numaq.h>
|
||||
#else /* summit or generic arch */
|
||||
#elif defined(CONFIG_ACPI_SRAT)/* summit or generic arch */
|
||||
#include <asm/srat.h>
|
||||
#endif
|
||||
|
||||
|
||||
@@ -117,7 +117,7 @@ static inline void pte_free(struct page *ptepage)
|
||||
pte_free_kernel(page_address(ptepage));
|
||||
}
|
||||
|
||||
#define PGF_CACHENUM_MASK 0xf
|
||||
#define PGF_CACHENUM_MASK 0x3
|
||||
|
||||
typedef struct pgtable_free {
|
||||
unsigned long val;
|
||||
|
||||
@@ -53,6 +53,15 @@
|
||||
#define smp_read_barrier_depends() do { } while(0)
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* This is a barrier which prevents following instructions from being
|
||||
* started until the value of the argument x is known. For example, if
|
||||
* x is a variable loaded from memory, this prevents following
|
||||
* instructions from being executed until the load has been performed.
|
||||
*/
|
||||
#define data_barrier(x) \
|
||||
asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
|
||||
|
||||
struct task_struct;
|
||||
struct pt_regs;
|
||||
|
||||
|
||||
@@ -1,16 +1,18 @@
|
||||
/*
|
||||
* include/asm-ppc/tsi108.h
|
||||
*
|
||||
* common routine and memory layout for Tundra TSI108(Grendel) host bridge
|
||||
* memory controller.
|
||||
*
|
||||
* Author: Jacob Pan (jacob.pan@freescale.com)
|
||||
* Alex Bounine (alexandreb@tundra.com)
|
||||
* 2004 (c) Freescale Semiconductor Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Copyright 2004-2006 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PPC_KERNEL_TSI108_H
|
||||
#define __PPC_KERNEL_TSI108_H
|
||||
|
||||
|
||||
124
include/asm-powerpc/tsi108_irq.h
Normal file
124
include/asm-powerpc/tsi108_irq.h
Normal file
@@ -0,0 +1,124 @@
|
||||
/*
|
||||
* (C) Copyright 2005 Tundra Semiconductor Corp.
|
||||
* Alex Bounine, <alexandreb at tundra.com).
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* definitions for interrupt controller initialization and external interrupt
|
||||
* demultiplexing on TSI108EMU/SVB boards.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_PPC_TSI108_IRQ_H
|
||||
#define _ASM_PPC_TSI108_IRQ_H
|
||||
|
||||
/*
|
||||
* Tsi108 interrupts
|
||||
*/
|
||||
#ifndef TSI108_IRQ_REG_BASE
|
||||
#define TSI108_IRQ_REG_BASE 0
|
||||
#endif
|
||||
|
||||
#define TSI108_IRQ(x) (TSI108_IRQ_REG_BASE + (x))
|
||||
|
||||
#define TSI108_MAX_VECTORS (36 + 4) /* 36 sources + PCI INT demux */
|
||||
#define MAX_TASK_PRIO 0xF
|
||||
|
||||
#define TSI108_IRQ_SPURIOUS (TSI108_MAX_VECTORS)
|
||||
|
||||
#define DEFAULT_PRIO_LVL 10 /* initial priority level */
|
||||
|
||||
/* Interrupt vectors assignment to external and internal
|
||||
* sources of requests. */
|
||||
|
||||
/* EXTERNAL INTERRUPT SOURCES */
|
||||
|
||||
#define IRQ_TSI108_EXT_INT0 TSI108_IRQ(0) /* External Source at INT[0] */
|
||||
#define IRQ_TSI108_EXT_INT1 TSI108_IRQ(1) /* External Source at INT[1] */
|
||||
#define IRQ_TSI108_EXT_INT2 TSI108_IRQ(2) /* External Source at INT[2] */
|
||||
#define IRQ_TSI108_EXT_INT3 TSI108_IRQ(3) /* External Source at INT[3] */
|
||||
|
||||
/* INTERNAL INTERRUPT SOURCES */
|
||||
|
||||
#define IRQ_TSI108_RESERVED0 TSI108_IRQ(4) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_RESERVED1 TSI108_IRQ(5) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_RESERVED2 TSI108_IRQ(6) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_RESERVED3 TSI108_IRQ(7) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_DMA0 TSI108_IRQ(8) /* DMA0 */
|
||||
#define IRQ_TSI108_DMA1 TSI108_IRQ(9) /* DMA1 */
|
||||
#define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
|
||||
#define IRQ_TSI108_DMA3 TSI108_IRQ(11) /* DMA3 */
|
||||
#define IRQ_TSI108_UART0 TSI108_IRQ(12) /* UART0 */
|
||||
#define IRQ_TSI108_UART1 TSI108_IRQ(13) /* UART1 */
|
||||
#define IRQ_TSI108_I2C TSI108_IRQ(14) /* I2C */
|
||||
#define IRQ_TSI108_GPIO TSI108_IRQ(15) /* GPIO */
|
||||
#define IRQ_TSI108_GIGE0 TSI108_IRQ(16) /* GIGE0 */
|
||||
#define IRQ_TSI108_GIGE1 TSI108_IRQ(17) /* GIGE1 */
|
||||
#define IRQ_TSI108_RESERVED4 TSI108_IRQ(18) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_HLP TSI108_IRQ(19) /* HLP */
|
||||
#define IRQ_TSI108_SDRAM TSI108_IRQ(20) /* SDC */
|
||||
#define IRQ_TSI108_PROC_IF TSI108_IRQ(21) /* Processor IF */
|
||||
#define IRQ_TSI108_RESERVED5 TSI108_IRQ(22) /* Reserved IRQ */
|
||||
#define IRQ_TSI108_PCI TSI108_IRQ(23) /* PCI/X block */
|
||||
|
||||
#define IRQ_TSI108_MBOX0 TSI108_IRQ(24) /* Mailbox 0 register */
|
||||
#define IRQ_TSI108_MBOX1 TSI108_IRQ(25) /* Mailbox 1 register */
|
||||
#define IRQ_TSI108_MBOX2 TSI108_IRQ(26) /* Mailbox 2 register */
|
||||
#define IRQ_TSI108_MBOX3 TSI108_IRQ(27) /* Mailbox 3 register */
|
||||
|
||||
#define IRQ_TSI108_DBELL0 TSI108_IRQ(28) /* Doorbell 0 */
|
||||
#define IRQ_TSI108_DBELL1 TSI108_IRQ(29) /* Doorbell 1 */
|
||||
#define IRQ_TSI108_DBELL2 TSI108_IRQ(30) /* Doorbell 2 */
|
||||
#define IRQ_TSI108_DBELL3 TSI108_IRQ(31) /* Doorbell 3 */
|
||||
|
||||
#define IRQ_TSI108_TIMER0 TSI108_IRQ(32) /* Global Timer 0 */
|
||||
#define IRQ_TSI108_TIMER1 TSI108_IRQ(33) /* Global Timer 1 */
|
||||
#define IRQ_TSI108_TIMER2 TSI108_IRQ(34) /* Global Timer 2 */
|
||||
#define IRQ_TSI108_TIMER3 TSI108_IRQ(35) /* Global Timer 3 */
|
||||
|
||||
/*
|
||||
* PCI bus INTA# - INTD# lines demultiplexor
|
||||
*/
|
||||
#define IRQ_PCI_INTAD_BASE TSI108_IRQ(36)
|
||||
#define IRQ_PCI_INTA (IRQ_PCI_INTAD_BASE + 0)
|
||||
#define IRQ_PCI_INTB (IRQ_PCI_INTAD_BASE + 1)
|
||||
#define IRQ_PCI_INTC (IRQ_PCI_INTAD_BASE + 2)
|
||||
#define IRQ_PCI_INTD (IRQ_PCI_INTAD_BASE + 3)
|
||||
#define NUM_PCI_IRQS (4)
|
||||
|
||||
/* number of entries in vector dispatch table */
|
||||
#define IRQ_TSI108_TAB_SIZE (TSI108_MAX_VECTORS + 1)
|
||||
|
||||
/* Mapping of MPIC outputs to processors' interrupt pins */
|
||||
|
||||
#define IDIR_INT_OUT0 0x1
|
||||
#define IDIR_INT_OUT1 0x2
|
||||
#define IDIR_INT_OUT2 0x4
|
||||
#define IDIR_INT_OUT3 0x8
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
* IRQ line configuration parameters */
|
||||
|
||||
/* Interrupt delivery modes */
|
||||
typedef enum {
|
||||
TSI108_IRQ_DIRECTED,
|
||||
TSI108_IRQ_DISTRIBUTED,
|
||||
} TSI108_IRQ_MODE;
|
||||
#endif /* _ASM_PPC_TSI108_IRQ_H */
|
||||
@@ -1093,5 +1093,100 @@ typedef struct im_idma {
|
||||
|
||||
#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
|
||||
|
||||
/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
|
||||
* in order to use clock-computing stuff below for the FCC x
|
||||
*/
|
||||
|
||||
/* Automatically generates register configurations */
|
||||
#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
|
||||
|
||||
#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
|
||||
#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
|
||||
#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
|
||||
#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
|
||||
#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
|
||||
#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
|
||||
|
||||
#define PC_F1RXCLK PC_CLK(F1_RXCLK)
|
||||
#define PC_F1TXCLK PC_CLK(F1_TXCLK)
|
||||
#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
|
||||
#define CMX1_CLK_MASK ((uint)0xff000000)
|
||||
|
||||
#define PC_F2RXCLK PC_CLK(F2_RXCLK)
|
||||
#define PC_F2TXCLK PC_CLK(F2_TXCLK)
|
||||
#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
|
||||
#define CMX2_CLK_MASK ((uint)0x00ff0000)
|
||||
|
||||
#define PC_F3RXCLK PC_CLK(F3_RXCLK)
|
||||
#define PC_F3TXCLK PC_CLK(F3_TXCLK)
|
||||
#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
|
||||
#define CMX3_CLK_MASK ((uint)0x0000ff00)
|
||||
|
||||
#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
|
||||
#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
|
||||
|
||||
#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
|
||||
|
||||
/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
|
||||
* but there is little variation among the choices.
|
||||
*/
|
||||
#define PA1_COL 0x00000001U
|
||||
#define PA1_CRS 0x00000002U
|
||||
#define PA1_TXER 0x00000004U
|
||||
#define PA1_TXEN 0x00000008U
|
||||
#define PA1_RXDV 0x00000010U
|
||||
#define PA1_RXER 0x00000020U
|
||||
#define PA1_TXDAT 0x00003c00U
|
||||
#define PA1_RXDAT 0x0003c000U
|
||||
#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
|
||||
#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
|
||||
PA1_RXDV | PA1_RXER)
|
||||
#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
|
||||
#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
|
||||
|
||||
|
||||
/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
|
||||
* but there is little variation among the choices.
|
||||
*/
|
||||
#define PB2_TXER 0x00000001U
|
||||
#define PB2_RXDV 0x00000002U
|
||||
#define PB2_TXEN 0x00000004U
|
||||
#define PB2_RXER 0x00000008U
|
||||
#define PB2_COL 0x00000010U
|
||||
#define PB2_CRS 0x00000020U
|
||||
#define PB2_TXDAT 0x000003c0U
|
||||
#define PB2_RXDAT 0x00003c00U
|
||||
#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
|
||||
PB2_RXER | PB2_RXDV | PB2_TXER)
|
||||
#define PB2_PSORB1 (PB2_TXEN)
|
||||
#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
|
||||
#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
|
||||
|
||||
|
||||
/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
|
||||
* but there is little variation among the choices.
|
||||
*/
|
||||
#define PB3_RXDV 0x00004000U
|
||||
#define PB3_RXER 0x00008000U
|
||||
#define PB3_TXER 0x00010000U
|
||||
#define PB3_TXEN 0x00020000U
|
||||
#define PB3_COL 0x00040000U
|
||||
#define PB3_CRS 0x00080000U
|
||||
#define PB3_TXDAT 0x0f000000U
|
||||
#define PC3_TXDAT 0x00000010U
|
||||
#define PB3_RXDAT 0x00f00000U
|
||||
#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
|
||||
PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
|
||||
#define PB3_PSORB1 0
|
||||
#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
|
||||
#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
|
||||
#define PC3_DIRC1 (PC3_TXDAT)
|
||||
|
||||
/* Handy macro to specify mem for FCCs*/
|
||||
#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
|
||||
#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
|
||||
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
|
||||
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2)
|
||||
|
||||
#endif /* __CPM2__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@@ -82,6 +82,7 @@ enum ppc_sys_devices {
|
||||
MPC82xx_CPM_SMC2,
|
||||
MPC82xx_CPM_USB,
|
||||
MPC82xx_SEC1,
|
||||
MPC82xx_MDIO_BB,
|
||||
NUM_PPC_SYS_DEVS,
|
||||
};
|
||||
|
||||
|
||||
@@ -110,6 +110,7 @@ enum ppc_sys_devices {
|
||||
MPC8xx_CPM_SMC1,
|
||||
MPC8xx_CPM_SMC2,
|
||||
MPC8xx_CPM_USB,
|
||||
MPC8xx_MDIO_FEC,
|
||||
NUM_PPC_SYS_DEVS,
|
||||
};
|
||||
|
||||
|
||||
@@ -234,7 +234,7 @@ static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
|
||||
sz_bits = 0UL;
|
||||
if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
|
||||
__asm__ __volatile__(
|
||||
"\n661: sethi %uhi(%1), %0\n"
|
||||
"\n661: sethi %%uhi(%1), %0\n"
|
||||
" sllx %0, 32, %0\n"
|
||||
" .section .sun4v_2insn_patch, \"ax\"\n"
|
||||
" .word 661b\n"
|
||||
|
||||
@@ -216,6 +216,7 @@ COMPATIBLE_IOCTL(VT_RESIZE)
|
||||
COMPATIBLE_IOCTL(VT_RESIZEX)
|
||||
COMPATIBLE_IOCTL(VT_LOCKSWITCH)
|
||||
COMPATIBLE_IOCTL(VT_UNLOCKSWITCH)
|
||||
COMPATIBLE_IOCTL(VT_GETHIFONTMASK)
|
||||
/* Little p (/dev/rtc, /dev/envctrl, etc.) */
|
||||
COMPATIBLE_IOCTL(RTC_AIE_ON)
|
||||
COMPATIBLE_IOCTL(RTC_AIE_OFF)
|
||||
|
||||
@@ -570,13 +570,14 @@ struct inode {
|
||||
* 3: quota file
|
||||
*
|
||||
* The locking order between these classes is
|
||||
* parent -> child -> normal -> quota
|
||||
* parent -> child -> normal -> xattr -> quota
|
||||
*/
|
||||
enum inode_i_mutex_lock_class
|
||||
{
|
||||
I_MUTEX_NORMAL,
|
||||
I_MUTEX_PARENT,
|
||||
I_MUTEX_CHILD,
|
||||
I_MUTEX_XATTR,
|
||||
I_MUTEX_QUOTA
|
||||
};
|
||||
|
||||
|
||||
@@ -69,34 +69,21 @@ enum fs_ioport {
|
||||
fsiop_porte,
|
||||
};
|
||||
|
||||
struct fs_mii_bus_info {
|
||||
int method; /* mii method */
|
||||
int id; /* the id of the mii_bus */
|
||||
int disable_aneg; /* if the controller needs to negothiate speed & duplex */
|
||||
int lpa; /* the default board-specific vallues will be applied otherwise */
|
||||
|
||||
union {
|
||||
struct {
|
||||
int duplex;
|
||||
int speed;
|
||||
} fixed;
|
||||
|
||||
struct {
|
||||
/* nothing */
|
||||
} fec;
|
||||
|
||||
struct {
|
||||
/* nothing */
|
||||
} scc;
|
||||
|
||||
struct {
|
||||
int mdio_port; /* port & bit for MDIO */
|
||||
int mdio_bit;
|
||||
int mdc_port; /* port & bit for MDC */
|
||||
int mdc_bit;
|
||||
int delay; /* delay in us */
|
||||
} bitbang;
|
||||
} i;
|
||||
struct fs_mii_bit {
|
||||
u32 offset;
|
||||
u8 bit;
|
||||
u8 polarity;
|
||||
};
|
||||
struct fs_mii_bb_platform_info {
|
||||
struct fs_mii_bit mdio_dir;
|
||||
struct fs_mii_bit mdio_dat;
|
||||
struct fs_mii_bit mdc_dat;
|
||||
int mdio_port; /* port & bit for MDIO */
|
||||
int mdio_bit;
|
||||
int mdc_port; /* port & bit for MDC */
|
||||
int mdc_bit;
|
||||
int delay; /* delay in us */
|
||||
int irq[32]; /* irqs per phy's */
|
||||
};
|
||||
|
||||
struct fs_platform_info {
|
||||
@@ -119,6 +106,7 @@ struct fs_platform_info {
|
||||
u32 device_flags;
|
||||
|
||||
int phy_addr; /* the phy address (-1 no phy) */
|
||||
const char* bus_id;
|
||||
int phy_irq; /* the phy irq (if it exists) */
|
||||
|
||||
const struct fs_mii_bus_info *bus_info;
|
||||
@@ -130,6 +118,10 @@ struct fs_platform_info {
|
||||
int napi_weight; /* NAPI weight */
|
||||
|
||||
int use_rmii; /* use RMII mode */
|
||||
int has_phy; /* if the network is phy container as well...*/
|
||||
};
|
||||
struct fs_mii_fec_platform_info {
|
||||
u32 irq[32];
|
||||
u32 mii_speed;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -59,27 +59,6 @@ static inline int task_nice_ioprio(struct task_struct *task)
|
||||
/*
|
||||
* For inheritance, return the highest of the two given priorities
|
||||
*/
|
||||
static inline int ioprio_best(unsigned short aprio, unsigned short bprio)
|
||||
{
|
||||
unsigned short aclass = IOPRIO_PRIO_CLASS(aprio);
|
||||
unsigned short bclass = IOPRIO_PRIO_CLASS(bprio);
|
||||
|
||||
if (!ioprio_valid(aprio))
|
||||
return bprio;
|
||||
if (!ioprio_valid(bprio))
|
||||
return aprio;
|
||||
|
||||
if (aclass == IOPRIO_CLASS_NONE)
|
||||
aclass = IOPRIO_CLASS_BE;
|
||||
if (bclass == IOPRIO_CLASS_NONE)
|
||||
bclass = IOPRIO_CLASS_BE;
|
||||
|
||||
if (aclass == bclass)
|
||||
return min(aprio, bprio);
|
||||
if (aclass > bclass)
|
||||
return bprio;
|
||||
else
|
||||
return aprio;
|
||||
}
|
||||
extern int ioprio_best(unsigned short aprio, unsigned short bprio);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -72,6 +72,9 @@ extern int journal_enable_debug;
|
||||
#endif
|
||||
|
||||
extern void * __jbd_kmalloc (const char *where, size_t size, gfp_t flags, int retry);
|
||||
extern void * jbd_slab_alloc(size_t size, gfp_t flags);
|
||||
extern void jbd_slab_free(void *ptr, size_t size);
|
||||
|
||||
#define jbd_kmalloc(size, flags) \
|
||||
__jbd_kmalloc(__FUNCTION__, (size), (flags), journal_oom_retry)
|
||||
#define jbd_rep_kmalloc(size, flags) \
|
||||
|
||||
@@ -48,15 +48,25 @@ enum nf_br_hook_priorities {
|
||||
|
||||
/* Only used in br_forward.c */
|
||||
static inline
|
||||
void nf_bridge_maybe_copy_header(struct sk_buff *skb)
|
||||
int nf_bridge_maybe_copy_header(struct sk_buff *skb)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (skb->nf_bridge) {
|
||||
if (skb->protocol == __constant_htons(ETH_P_8021Q)) {
|
||||
err = skb_cow(skb, 18);
|
||||
if (err)
|
||||
return err;
|
||||
memcpy(skb->data - 18, skb->nf_bridge->data, 18);
|
||||
skb_push(skb, 4);
|
||||
} else
|
||||
} else {
|
||||
err = skb_cow(skb, 16);
|
||||
if (err)
|
||||
return err;
|
||||
memcpy(skb->data - 16, skb->nf_bridge->data, 16);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This is called by the IP fragmenting code and it ensures there is
|
||||
|
||||
@@ -659,7 +659,7 @@ struct nfs4_rename_res {
|
||||
struct nfs4_setclientid {
|
||||
const nfs4_verifier * sc_verifier; /* request */
|
||||
unsigned int sc_name_len;
|
||||
char sc_name[32]; /* request */
|
||||
char sc_name[48]; /* request */
|
||||
u32 sc_prog; /* request */
|
||||
unsigned int sc_netid_len;
|
||||
char sc_netid[4]; /* request */
|
||||
|
||||
@@ -30,12 +30,20 @@ extern struct node node_devices[];
|
||||
|
||||
extern int register_node(struct node *, int, struct node *);
|
||||
extern void unregister_node(struct node *node);
|
||||
#ifdef CONFIG_NUMA
|
||||
extern int register_one_node(int nid);
|
||||
extern void unregister_one_node(int nid);
|
||||
#ifdef CONFIG_NUMA
|
||||
extern int register_cpu_under_node(unsigned int cpu, unsigned int nid);
|
||||
extern int unregister_cpu_under_node(unsigned int cpu, unsigned int nid);
|
||||
#else
|
||||
static inline int register_one_node(int nid)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int unregister_one_node(int nid)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int register_cpu_under_node(unsigned int cpu, unsigned int nid)
|
||||
{
|
||||
return 0;
|
||||
|
||||
@@ -378,6 +378,7 @@ int phy_mii_ioctl(struct phy_device *phydev,
|
||||
struct mii_ioctl_data *mii_data, int cmd);
|
||||
int phy_start_interrupts(struct phy_device *phydev);
|
||||
void phy_print_status(struct phy_device *phydev);
|
||||
struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id);
|
||||
|
||||
extern struct bus_type mdio_bus_type;
|
||||
#endif /* __PHY_H */
|
||||
|
||||
@@ -42,9 +42,9 @@ RPC_I(struct inode *inode)
|
||||
extern int rpc_queue_upcall(struct inode *, struct rpc_pipe_msg *);
|
||||
|
||||
extern struct dentry *rpc_mkdir(char *, struct rpc_clnt *);
|
||||
extern int rpc_rmdir(char *);
|
||||
extern int rpc_rmdir(struct dentry *);
|
||||
extern struct dentry *rpc_mkpipe(char *, void *, struct rpc_pipe_ops *, int flags);
|
||||
extern int rpc_unlink(char *);
|
||||
extern int rpc_unlink(struct dentry *);
|
||||
extern struct vfsmount *rpc_get_mount(void);
|
||||
extern void rpc_put_mount(void);
|
||||
|
||||
|
||||
@@ -37,7 +37,7 @@ extern unsigned int xprt_max_resvport;
|
||||
|
||||
#define RPC_MIN_RESVPORT (1U)
|
||||
#define RPC_MAX_RESVPORT (65535U)
|
||||
#define RPC_DEF_MIN_RESVPORT (650U)
|
||||
#define RPC_DEF_MIN_RESVPORT (665U)
|
||||
#define RPC_DEF_MAX_RESVPORT (1023U)
|
||||
|
||||
/*
|
||||
|
||||
@@ -59,6 +59,7 @@ struct tty_bufhead {
|
||||
struct tty_buffer *head; /* Queue head */
|
||||
struct tty_buffer *tail; /* Active buffer */
|
||||
struct tty_buffer *free; /* Free queue head */
|
||||
int memory_used; /* Buffer space used excluding free queue */
|
||||
};
|
||||
/*
|
||||
* The pty uses char_buf and flag_buf as a contiguous buffer
|
||||
|
||||
@@ -60,5 +60,6 @@ struct vt_consize {
|
||||
#define VT_RESIZEX 0x560A /* set kernel's idea of screensize + more */
|
||||
#define VT_LOCKSWITCH 0x560B /* disallow vt switching */
|
||||
#define VT_UNLOCKSWITCH 0x560C /* allow vt switching */
|
||||
#define VT_GETHIFONTMASK 0x560D /* return hi font mask */
|
||||
|
||||
#endif /* _LINUX_VT_H */
|
||||
|
||||
@@ -404,19 +404,6 @@ static inline int sctp_list_single_entry(struct list_head *head)
|
||||
return ((head->next != head) && (head->next == head->prev));
|
||||
}
|
||||
|
||||
/* Calculate the size (in bytes) occupied by the data of an iovec. */
|
||||
static inline size_t get_user_iov_size(struct iovec *iov, int iovlen)
|
||||
{
|
||||
size_t retval = 0;
|
||||
|
||||
for (; iovlen > 0; --iovlen) {
|
||||
retval += iov->iov_len;
|
||||
iov++;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* Generate a random jitter in the range of -50% ~ +50% of input RTO. */
|
||||
static inline __s32 sctp_jitter(__u32 rto)
|
||||
{
|
||||
|
||||
@@ -221,8 +221,7 @@ struct sctp_chunk *sctp_make_abort_no_data(const struct sctp_association *,
|
||||
const struct sctp_chunk *,
|
||||
__u32 tsn);
|
||||
struct sctp_chunk *sctp_make_abort_user(const struct sctp_association *,
|
||||
const struct sctp_chunk *,
|
||||
const struct msghdr *);
|
||||
const struct msghdr *, size_t msg_len);
|
||||
struct sctp_chunk *sctp_make_abort_violation(const struct sctp_association *,
|
||||
const struct sctp_chunk *,
|
||||
const __u8 *,
|
||||
|
||||
@@ -60,6 +60,7 @@ struct iscsi_nopin;
|
||||
#define TMABORT_SUCCESS 0x1
|
||||
#define TMABORT_FAILED 0x2
|
||||
#define TMABORT_TIMEDOUT 0x3
|
||||
#define TMABORT_NOT_FOUND 0x4
|
||||
|
||||
/* Connection suspend "bit" */
|
||||
#define ISCSI_SUSPEND_BIT 1
|
||||
@@ -83,6 +84,12 @@ struct iscsi_mgmt_task {
|
||||
struct list_head running;
|
||||
};
|
||||
|
||||
enum {
|
||||
ISCSI_TASK_COMPLETED,
|
||||
ISCSI_TASK_PENDING,
|
||||
ISCSI_TASK_RUNNING,
|
||||
};
|
||||
|
||||
struct iscsi_cmd_task {
|
||||
/*
|
||||
* Becuae LLDs allocate their hdr differently, this is a pointer to
|
||||
@@ -101,6 +108,8 @@ struct iscsi_cmd_task {
|
||||
struct iscsi_conn *conn; /* used connection */
|
||||
struct iscsi_mgmt_task *mtask; /* tmf mtask in progr */
|
||||
|
||||
/* state set/tested under session->lock */
|
||||
int state;
|
||||
struct list_head running; /* running cmd list */
|
||||
void *dd_data; /* driver/transport data */
|
||||
};
|
||||
@@ -126,6 +135,14 @@ struct iscsi_conn {
|
||||
int id; /* CID */
|
||||
struct list_head item; /* maintains list of conns */
|
||||
int c_stage; /* connection state */
|
||||
/*
|
||||
* Preallocated buffer for pdus that have data but do not
|
||||
* originate from scsi-ml. We never have two pdus using the
|
||||
* buffer at the same time. It is only allocated to
|
||||
* the default max recv size because the pdus we support
|
||||
* should always fit in this buffer
|
||||
*/
|
||||
char *data;
|
||||
struct iscsi_mgmt_task *login_mtask; /* mtask used for login/text */
|
||||
struct iscsi_mgmt_task *mtask; /* xmit mtask in progress */
|
||||
struct iscsi_cmd_task *ctask; /* xmit ctask in progress */
|
||||
@@ -134,7 +151,7 @@ struct iscsi_conn {
|
||||
struct kfifo *immqueue; /* immediate xmit queue */
|
||||
struct kfifo *mgmtqueue; /* mgmt (control) xmit queue */
|
||||
struct list_head mgmt_run_list; /* list of control tasks */
|
||||
struct kfifo *xmitqueue; /* data-path cmd queue */
|
||||
struct list_head xmitqueue; /* data-path cmd queue */
|
||||
struct list_head run_list; /* list of cmds in progress */
|
||||
struct work_struct xmitwork; /* per-conn. xmit workqueue */
|
||||
/*
|
||||
|
||||
@@ -57,8 +57,6 @@ struct sockaddr;
|
||||
* @stop_conn: suspend/recover/terminate connection
|
||||
* @send_pdu: send iSCSI PDU, Login, Logout, NOP-Out, Reject, Text.
|
||||
* @session_recovery_timedout: notify LLD a block during recovery timed out
|
||||
* @suspend_conn_recv: susepend the recv side of the connection
|
||||
* @termincate_conn: destroy socket connection. Called with mutex lock.
|
||||
* @init_cmd_task: Initialize a iscsi_cmd_task and any internal structs.
|
||||
* Called from queuecommand with session lock held.
|
||||
* @init_mgmt_task: Initialize a iscsi_mgmt_task and any internal structs.
|
||||
@@ -112,8 +110,6 @@ struct iscsi_transport {
|
||||
char *data, uint32_t data_size);
|
||||
void (*get_stats) (struct iscsi_cls_conn *conn,
|
||||
struct iscsi_stats *stats);
|
||||
void (*suspend_conn_recv) (struct iscsi_conn *conn);
|
||||
void (*terminate_conn) (struct iscsi_conn *conn);
|
||||
void (*init_cmd_task) (struct iscsi_cmd_task *ctask);
|
||||
void (*init_mgmt_task) (struct iscsi_conn *conn,
|
||||
struct iscsi_mgmt_task *mtask,
|
||||
|
||||
Reference in New Issue
Block a user