Commit Graph

104 Commits

Author SHA1 Message Date
Sammy He
bbaaecc647 ENGR00132971 Workaround for imx5x M4IF burst len errata for armv7 neon
Workaround for imx5x M4IF burst len errata when armv7 neon enabled, use
pgprot_writecombine instead of pgprot_noncached, to avoid burst len > 8.

Signed-off-by: Sammy He <r62914@freescale.com>
2010-12-13 14:01:20 -06:00
Matt Sealey
6942fd4666 ENGR00133681 VPU:Fix kernel dump when VPU doesn't use IRAM
If VPU doesn't use IRAM, there will be a kernel dump when
we enter VPU driver probe function.
This issue is caused by allocating IRAM with zero buffer
size.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-12-13 12:14:16 -06:00
Jason Chen
d74111ac5b ENGR00127358 ipuv3: make display data signal negative during blanking period
make display data signal negative during blanking period.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-12-03 10:42:46 -06:00
Jason Chen
1b4a64e634 ENGR00127332 ipuv3: change the disalbe dp-dc timming
disable dp-dc in the display flow end irq handler, otherwise,
ipu may get NFB4EOF error for next fb enabling under big resolution(like 1080p).

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-12-03 10:42:15 -06:00
Matt Sealey
816d9d06f2 Remove custom clock setting code as FSL fixed that bug in 10.09.00 2010-12-03 10:41:13 -06:00
Matt Sealey
12ee5014b5 Modify IPU behavior not to try to adapt panel v_end_width since this fix
is really only for 800x600 TFT panels directly connected with weird
requirements. Make sure it's well and truly #if'd out.
2010-11-20 17:26:20 -06:00
Matt Sealey
b29b1f8cbd * Remove weird pin wiggling in EDID fetch
* Remove VGA support
* Remove HDMI customization (was for the old driver)
* Consolidate DI clock setting (view is to remove it eventually since
  the bug it was meant to work around is fixed)
* Remove mxc_ipuv3_fb.c dependency on EfikaMX includes
2010-11-20 10:46:21 -06:00
Matt Sealey
26a3feaa56 AMD GPU update 2010-11-13 10:32:27 -06:00
Matt Sealey
0616c12255 Clarify OpenVG disabled error (should be impossible with new defconfig anyway) 2010-11-13 10:32:14 -06:00
Jie Zhou
73685d49b8 ENGR00126565-2 GPU: Provide z160 precision info to user space libraries
MX50 Z160 has higher gradient/texture precision than MX51/53.

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-11-13 10:10:00 -06:00
Jie Zhou
ef5ea51ba2 ENGR00126064 GPU: disable mmu to pass OpenVG CTS
If enabled MMU, there is AXI read/write error on MX508 when run
OpenVG CTS.

Besides, change EMEM1 size to 10MB by default to make gpu driver
work on MX50_ARM2 board with 128MB memory installed.

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-11-13 10:09:43 -06:00
Jie Zhou
90875b3f6c ENGR00125984 GPU: enable MMU for MX508 and MX35
Remove GSL_MMU_TRANSLATION_ENABLED macro originally used for conditional
compile, and replace it with runtime check to support one mx5x image

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-11-13 10:09:41 -06:00
Jie Zhou
dd4baeffab ENGR00125615 GPU: disable z160 in gsl when X-Accel enabled
When X-accel is enabled, uio driver is used for X server to access
z160 device, so in gsl, we should not operate z160 to avoid conflicts

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-11-13 10:08:00 -06:00
Jie Zhou
373272e191 ENGR00125729-2 GPU: merge hal for MX35/MX50 and MX51/MX53
Add MX508 support, and adapt the gpu driver to one image

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-11-13 10:07:57 -06:00
Matt Sealey
5b0051e382 ipu: make disable/unitialized "error" into "info" since it doesn't mean anything went wrong 2010-10-28 04:16:01 -05:00
Jason Chen
e8fe793cf5 ENGR00126156 ipuv3: check own clk count only when around clk rate
If dual display enabled, the second one may not be able to set
correct clock rate if it's from ext clk.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-10-21 13:17:58 -05:00
Dinh Nguyen
cc1ca49e78 ENGR00126861-2: ipu: pass csi clock in ipu platform data
ipu: pass csi clock in platform data
ipu: use ipu hw rev instead of chip version

Acked-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
2010-10-21 13:17:38 -05:00
Matt Sealey
81163a41f4 Smarttop: remove modes which do not match IPU restrictions (vertical border needs to be >2) in order not to have them be "reconfigured" later to be potentially incompatible with the monitor. 2010-09-28 12:15:55 -05:00
Matt Sealey
b26a7674e0 EfikaMX Smartbook Kernel support, initial 2010-09-03 14:36:46 -05:00
Matt Sealey
a8c4657dbb Workaround for pm_power_off being overwritten by PMIC code later in init. System should
properly shut down (i.e. power is turned off) and reboot (i.e. goes back to U-Boot) now.
2010-08-19 17:19:30 -05:00
Matt Sealey
68657eb619 Workaround for monitor blank when xres > 1024 due to g_di_clk[disp] > ipu clock 2010-08-14 21:50:20 -05:00
Jie Zhou
03bc7b8a7a ENGR00125616 GPU: make sure device is stopped before close
When terminating some applications such as OpenGL ES2.0 conf. test,
kgsl_device_stop is not triggered. And run such kind of application
for several times, system hang happens for inconsistency of device
states. So make sure device is stopped in kgsl_device_close, which
is only called by last running caller process.

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-08-10 11:52:10 -05:00
Jason Chen
8f6187a728 ENGR00125506 ipu dev: change mmap to writethrough policy
The mmap policy should be writethrough.

Signed-off-by: Jason Chen <b02280@freescale.com>
(cherry picked from commit aceea32a54b8aa248d771b589d46ce8fbe3c2806)
2010-08-10 11:52:08 -05:00
Jie Zhou
29e496fc89 ENGR00125556 GPU: Check device refcnt before free memstore
memstore should only be freed when the device has been stopped with
device->refcnt equalling zero.

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-08-10 11:52:05 -05:00
Jie Zhou
4bb70f55fc ENGR00125434 GPU: Fix kernel oops when run ES2.0 conf. test for second time
memstore should be freed properly. a following change will be prepared to
improve the alloc/free logic for device memstore.

Signed-off-by: Jie Zhou <b30303@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
2010-08-10 11:52:04 -05:00
Jie Zhou
4cd2daf53c ENGR00125353 GPU: use writecombine for mmap
Change pgprot_noncached to pgprot_writecombine in gsl_kmod_mmap to
improve performance

Signed-off-by: Thomas Peng <r80085@freescale.com>
Signed-off-by: Jie Zhou <b30303@freescale.com>
(cherry picked from commit 847baca41bceed49e397eaba8b1b3b00e86e20a3)
2010-08-10 11:52:02 -05:00
Jie Zhou
25d42e43ac ENGR00125327 GPU: solve some problems in latest integration
With latest VG/GL fix integration from RC16/EA, there will be some problems
as below, which can be solved by this patch:
- ENGR00124884 will happen again
- suspend/resume will not be supported in gpu driver

Signed-off-by: Jie Zhou <b30303@freescale.com>
2010-08-10 11:52:00 -05:00
Jason Chen
e53608c008 ENGR00125265 ipuv3: change the unlock position in ipu_disable_channel
change the unlock position in ipu_disable_channel.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:51:58 -05:00
Jason Chen
9eb606141a ENGR00125250 ipuv3:wait display EOF interrupt before disable its IDMA channel
It should avoid the NFB4EOF error.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:51:58 -05:00
r80085
b8ed88ab15 ENGR00125256 Integrate AMD Rc16/EA VG/GL fix to GPU kernel module
Fix the VG/GL issue in GPU kernel module when running VG/GL at the same time

Signed-off-by: Gene Chouiniere <Gene.Chouiniere@amd.com>
Signed-off-by: r80085 <thomas.peng@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
2010-08-10 11:51:57 -05:00
Gene Chouiniere
da25d30bfa ENGR00125010-1 gpu: add gpu driver support
Migrate from RC14 with freescale changes.

Signed-off-by: Gene Chouiniere <Gene.Chouiniere@amd.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
2010-08-10 11:51:46 -05:00
Jason Chen
5587d66a12 ENGR00125173 ipuv3: remove stat check wait in _ipu_dp_dc_disable()
The stat check wait will add ipu operation time which degrade the ipu
performance.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:51:44 -05:00
Jason Chen
743a8eed30 ENGR00125171 ipu dev: add sync method
The memory mmap by ipu device is write-back, so user space need sync
method.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:51:43 -05:00
Zhou Jingyu
fa9167503b ENGR00125077: pmic battery: disable battery for MX50 Arm2 board
pmic battery: disable battery for MX50 Arm2 board

Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
2010-08-10 11:51:38 -05:00
mark gutman
0fbba7a43f ENGR00124942 MX51: YUV422 output for 720P data
Ignore UGDE using for non YUYV output formats

Signed-off-by: Mark Gutman <r58412@freescale.com>
2010-08-10 11:51:33 -05:00
Sammy He
9fe0e34c9f ENGR00124683-1 Add CCIR interlaced mode for TV decoder
Add CCIR interlaced mode for TV decoder. And add pwdn callback
function in mxc_camera_platform_data.

Signed-off-by: Sammy He <r62914@freescale.com>
2010-08-10 11:51:15 -05:00
Liu Ying
ab9b6e2c7a ENGR00124569 IPUv3:Change for support VDI in IPU lib
1) Support select VDI input channel buffer ioctrl.
2) Add VDI input channels' EOF interrupt.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-08-10 11:51:13 -05:00
Liu Ying
cb4c5628ce ENGR00124082-1 IPUv3:Fix some bugs related with VDI
1) Read buffer 1 ready register before setting buffer 1 ready.
2) Enable ISP in IPU_CONF when using VDI.
3) Fix link issue between MEM_VDI_PRP_VF_MEM and MEM_ROT_VF_MEM.
4) Correct g_channel_init_mask value.
5) Use fixed top field for VDI.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-08-10 11:51:12 -05:00
Jason Chen
6a487d0bde ENGR00124360 v4l2 output: rework v4l2 output
1. remove ADC support.
2. remove work queue for not ic bypass mode which improve the
performance.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:51:09 -05:00
mark gutman
e65a92ffe5 ENGR00119736 MX51: YUV422 output for 720P data
The support for YUV422 different combinations are added
	The YUV422 is supported for DI1 interface for 720P frames with 16bits bus  only:
	di1_primary video=mxcdi1fb:YUYV16,720P60
	To define required YUV422 format use one of:
	YUYV16
	YVYU16
	UYVY16
	VYUY16

	Signed-off-by: Mark Gutman <r58412@freescale.com>
2010-08-10 11:51:06 -05:00
Jason Chen
4fd83bff23 ENGR00124023 v4l2 output:modify the operation of ic-bypass mode
/unit_test//unit_tests/mxc_v4l2_output.out -iw 1920 -ih 1080 -ow 1920
-oh 1080 -d 3 -l 600 -fr 80 /dev/shm/1920_1080_E18_c2.yuv

Error information:
It report the following error:
video4linux video16: unable to update buffer 0 address rc=-13

Fix above issue by modify the operation of ic-bypass mode.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:50:48 -05:00
Jason Chen
8a22766c4b ENGR00123731 ipuv3: change the submodules enable timming
change the ipu submodules enable timming.

Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:50:45 -05:00
Liu Ying
3d5466a5b7 ENGR00123507 IPUv3:Set suitable IDMAC burst size for UYVY and ABGR32
1)Set the IDMAC channel's burst size to be 32 pixels if the channel is
in UYVY pixel format.
2)Set the IDMAC channel's burst size to be 16 pixels if the channel is
in ABGR32 pixel format.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-08-10 11:50:24 -05:00
mark gutman
b70ba43911 ENGR00123294 MX53: 4 stripes algorithm for support resizing for big screen
The updated algorithm allows output frame size up to 2048x2048

Signed-off-by: Mark Gutman <Mark.Gutman@freescale.com>
2010-08-10 11:50:24 -05:00
Ran Ferderber
71d0502031 ENGR00123439 DMFC size: IPU DMFC DP high resulution fail to display small frame
update the DMFC size to avoid usage of WAIT4EOT when possible

Signed-off-by: Ran Ferderber <r53561@freescale.com>
2010-08-10 11:50:23 -05:00
Sammy He
5fb06cff8a ENGR00123489 Support vpu suspend/resume on mx53
Support vpu suspend/resume on mx53. Don't do power gating and
firmware re-install on mx53.

Signed-off-by: Sammy He <r62914@freescale.com>
2010-08-10 11:50:20 -05:00
Liu Ying
46fcac840e ENGR00122216-2 Support LDB driver
This patch adds LDB driver support.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-08-10 11:50:18 -05:00
Jason Chen
cedf277fe5 ENGR00122780 ipufb: rework display device setting method
Rework the display command line options to not require new option for
every new display. Add mxcdi0fb/mxcdi1fb option <fmt> and to tell system
what kind of display device is going to use.

Use "di1_primary" to make DI1 the primary display (i.e. fb0).

The display selection is done using video= parameter.

        For example on imx51:

                  di             di_fmt      video_mode
        DVI:      0              RGB24      mxcdi0fb:800x600M-16@60 etc
        DVI-HDMI: 0              RGB24      mxcdi0fb:720P60
        LVDS:     0              LVDS666    mxcdi0fb:XGA
        WVGA lcd: 1              RGB565     mxcdi1fb:800x480M-16@55
        TVE:      1              YUV444     mxcdi1fb:TV-NTSC
                                            mxcdi1fb:TV-PAL
                                            mxcdi1fb:720P60
        For example on imx53:

                  di             di_fmt      video_mode
        DVI:      0              RGB24      mxcdi0fb:800x600M-16@60 etc
        DVI-HDMI: 0              RGB24      mxcdi0fb:720P60
        WVGA lcd: 0              RGB565     mxcdi0fb:800x480M-16@55
        TVE:      1              YUV444     mxcdi1fb:TV-NTSC
                                            mxcdi1fb:TV-PAL
                                            mxcdi1fb:720P60

If you want to set NTSC tv as primary display, and make second display
DI0 as DVI 1024x768 resolution, just add

"di1_primary video=mxcdi0fb:RGB24,1024x768M-16@60 video=mxcdi1fb:YUV444,TV-NTSC"

to cmdline.

Signed-off-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Jason Chen <b02280@freescale.com>
2010-08-10 11:50:15 -05:00
Rob Herring
d168c16c2a ENGR00122962 ipu: don't set axi id to 1 on mx53
Setting the AXI ID on to 1 for sync display channels on MX53 causes
display flickering when system is heavily loaded.

Signed-off-by: Rob Herring <r.herring@freescale.com>
(cherry picked from commit 30df5734fcea4146b60f35238aaf5368f3392b0d)
2010-08-10 11:50:13 -05:00
Liu Ying
9ba5a62a58 ENGR00123129 IPUv3:Enable DMFC watermark
Enable IDMAC WM enable bit when enable corresponding
DMFC channel's watermark.

Signed-off-by: Liu Ying <b17645@freescale.com>
2010-08-10 11:49:55 -05:00