mirror of
https://github.com/genesi/linux-legacy.git
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b422b1ca4e
Added improved timing calculations to the driver, and various other support work. Signed-off-by: Patrick Turley <patrick.turley@freescale.com>
1597 lines
38 KiB
C
1597 lines
38 KiB
C
/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/iram_alloc.h>
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#include <linux/platform_device.h>
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#include <mach/clock.h>
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#include "regs-clkctrl.h"
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#include "regs-digctl.h"
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#include <mach/regs-rtc.h>
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#include <mach/mx23.h>
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#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR)
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#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR)
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#define RTC_BASE_ADDR IO_ADDRESS(RTC_PHYS_ADDR)
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/* these are the maximum clock speeds that have been
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* validated to run at the minumum VddD target voltage level for cpu operation
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* (presently 1.05V target, .975V Brownout). Higher clock speeds for GPMI and
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* SSP have not been validated.
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*/
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#define PLL_ENABLED_MAX_CLK_SSP 96000000
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#define PLL_ENABLED_MAX_CLK_GPMI 96000000
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/* external clock input */
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static struct clk pll_clk;
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static struct clk ref_xtal_clk;
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#ifdef DEBUG
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static void print_ref_counts(void);
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#endif
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static unsigned long enet_mii_phy_rate;
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static inline int clk_is_busy(struct clk *clk)
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{
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if ((clk->parent == &ref_xtal_clk) && (clk->xtal_busy_bits))
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return __raw_readl(clk->busy_reg) & (1 << clk->xtal_busy_bits);
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else if (clk->busy_bits && clk->busy_reg)
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return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits);
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else {
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printk(KERN_ERR "WARNING: clock has no assigned busy \
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register or bits\n");
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udelay(10);
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return 0;
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}
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}
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static inline int clk_busy_wait(struct clk *clk)
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{
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int i;
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for (i = 10000000; i; i--)
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if (!clk_is_busy(clk))
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break;
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if (!i)
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return -ETIMEDOUT;
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else
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return 0;
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}
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static bool mx23_enable_h_autoslow(bool enable)
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{
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bool currently_enabled;
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if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) &
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BM_CLKCTRL_HBUS_AUTO_SLOW_MODE)
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currently_enabled = true;
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else
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currently_enabled = false;
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if (enable)
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__raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
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else
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__raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
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return currently_enabled;
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}
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static void mx23_set_hbus_autoslow_flags(u16 mask)
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{
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u32 reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
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reg &= 0xFFFF;
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reg |= mask << 16;
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__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
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}
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static void local_clk_disable(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->ref)
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return;
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if ((--clk->ref) & CLK_EN_MASK)
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return;
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if (clk->disable)
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clk->disable(clk);
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local_clk_disable(clk->secondary);
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local_clk_disable(clk->parent);
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}
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static int local_clk_enable(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if ((clk->ref++) & CLK_EN_MASK)
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return 0;
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if (clk->parent)
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local_clk_enable(clk->parent);
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if (clk->secondary)
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local_clk_enable(clk->secondary);
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if (clk->enable)
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clk->enable(clk);
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return 0;
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}
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static bool mx23_is_clk_enabled(struct clk *clk)
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{
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if (clk->enable_reg)
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return (__raw_readl(clk->enable_reg) &
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clk->enable_bits) ? 0 : 1;
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else
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return (clk->ref & CLK_EN_MASK) ? 1 : 0;
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}
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static int mx23_raw_enable(struct clk *clk)
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{
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unsigned int reg;
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if (clk->enable_reg) {
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reg = __raw_readl(clk->enable_reg);
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reg &= ~clk->enable_bits;
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__raw_writel(reg, clk->enable_reg);
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}
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if (clk->busy_reg)
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clk_busy_wait(clk);
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return 0;
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}
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static void mx23_raw_disable(struct clk *clk)
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{
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unsigned int reg;
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if (clk->enable_reg) {
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reg = __raw_readl(clk->enable_reg);
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reg |= clk->enable_bits;
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__raw_writel(reg, clk->enable_reg);
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}
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}
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static unsigned long ref_xtal_get_rate(struct clk *clk)
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{
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return 24000000;
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}
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static struct clk ref_xtal_clk = {
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.flags = RATE_FIXED,
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.get_rate = ref_xtal_get_rate,
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};
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static unsigned long pll_get_rate(struct clk *clk);
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static int pll_enable(struct clk *clk);
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static void pll_disable(struct clk *clk);
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static struct clk pll_clk = {
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.parent = &ref_xtal_clk,
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.flags = RATE_FIXED,
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.get_rate = pll_get_rate,
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.enable = pll_enable,
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.disable = pll_disable,
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};
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static unsigned long pll_get_rate(struct clk *clk)
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{
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return 480000000;
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}
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static int pll_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0);
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if ((reg & BM_CLKCTRL_PLLCTRL0_POWER) &&
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(reg & BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS))
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return 0;
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__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
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BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
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/* only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
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* and is incorrect (excessive). Per definition of the PLLCTRL0
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* POWER field, waiting at least 10us.
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*/
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udelay(10);
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return 0;
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}
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static void pll_disable(struct clk *clk)
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{
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__raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
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BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
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return;
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}
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static inline unsigned long
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ref_clk_get_rate(unsigned long base, unsigned int div)
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{
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unsigned long rate = base / 1000;
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return 1000 * ((rate * 18) / div);
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}
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static unsigned long ref_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long base = clk->parent->get_rate(clk->parent);
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unsigned long div = (base * 18) / rate;
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return (base / div) * 18;
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}
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static int ref_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long base = clk->parent->get_rate(clk->parent);
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unsigned long div = ((base/1000) * 18) / (rate/1000);
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if (rate != ((base / div) * 18))
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return -EINVAL;
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if (clk->scale_reg == 0)
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return -EINVAL;
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base = __raw_readl(clk->scale_reg);
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base &= ~(0x3F << clk->scale_bits);
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base |= (div << clk->scale_bits);
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__raw_writel(base, clk->scale_reg);
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return 0;
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}
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static unsigned long ref_cpu_get_rate(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_CPUFRAC;
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return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
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}
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static struct clk ref_cpu_clk = {
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.parent = &pll_clk,
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.enable = mx23_raw_enable,
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.disable = mx23_raw_disable,
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.get_rate = ref_cpu_get_rate,
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.round_rate = ref_clk_round_rate,
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.set_rate = ref_clk_set_rate,
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.enable_bits = BM_CLKCTRL_FRAC_CLKGATECPU,
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.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.scale_bits = BP_CLKCTRL_FRAC_CPUFRAC,
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.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU,
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.busy_bits = 28,
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};
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static unsigned long ref_emi_get_rate(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_EMIFRAC;
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reg >>= BP_CLKCTRL_FRAC_EMIFRAC;
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return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
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}
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static struct clk ref_emi_clk = {
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.parent = &pll_clk,
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.enable = mx23_raw_enable,
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.disable = mx23_raw_disable,
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.get_rate = ref_emi_get_rate,
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.set_rate = ref_clk_set_rate,
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.round_rate = ref_clk_round_rate,
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.enable_bits = BM_CLKCTRL_FRAC_CLKGATEEMI,
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.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.scale_bits = BP_CLKCTRL_FRAC_EMIFRAC,
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};
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static unsigned long ref_io_get_rate(struct clk *clk);
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static struct clk ref_io_clk = {
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.parent = &pll_clk,
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.enable = mx23_raw_enable,
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.disable = mx23_raw_disable,
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.get_rate = ref_io_get_rate,
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO,
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};
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static unsigned long ref_io_get_rate(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_IOFRAC;
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reg >>= BP_CLKCTRL_FRAC_IOFRAC;
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return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
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}
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static unsigned long ref_pix_get_rate(struct clk *clk)
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{
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unsigned long reg;
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reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_PIXFRAC;
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reg >>= BP_CLKCTRL_FRAC_PIXFRAC;
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return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
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}
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static struct clk ref_pix_clk = {
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.parent = &pll_clk,
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.enable = mx23_raw_enable,
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.disable = mx23_raw_disable,
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.get_rate = ref_pix_get_rate,
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.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
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.enable_bits = BM_CLKCTRL_FRAC_CLKGATEPIX,
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};
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static struct clk cpu_clk, h_clk;
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static int clkseq_set_parent(struct clk *clk, struct clk *parent)
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{
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int shift;
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if (clk->parent == parent)
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return 0; /* clock parent already at target. nothing to do */
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/* bypass? */
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if (parent == &ref_xtal_clk)
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shift = 4;
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else
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shift = 8;
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if (clk->bypass_reg)
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__raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift);
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return 0;
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}
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static unsigned long lcdif_get_rate(struct clk *clk)
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{
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long rate = clk->parent->get_rate(clk->parent);
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long div;
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const int mask = 0xff;
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div = (__raw_readl(clk->scale_reg) >> clk->scale_bits) & mask;
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if (div) {
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rate /= div;
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div = (__raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
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BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
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rate /= div;
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}
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return rate;
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}
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static int lcdif_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = 0;
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/*
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* ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
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* which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
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*
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* ns_cycle >= 2*18e3/(18*480) = 25/6
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* ns_cycle <= 2*35e3/(18*480) = 875/108
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*
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* Multiply the ns_cycle by 'div' to lengthen it until it fits the
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* bounds. This is the divider we'll use after ref_pix.
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*
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* 6 * ns_cycle >= 25 * div
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* 108 * ns_cycle <= 875 * div
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*/
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u32 ns_cycle = 1000000000 / rate;
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u32 div, reg_val;
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u32 lowest_result = (u32) -1;
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u32 lowest_div = 0, lowest_fracdiv = 0;
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ns_cycle *= 2; /* Fix calculate double frequency */
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for (div = 1; div < 256; ++div) {
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u32 fracdiv;
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u32 ps_result;
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int lower_bound = 6 * ns_cycle >= 25 * div;
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int upper_bound = 108 * ns_cycle <= 875 * div;
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if (!lower_bound)
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break;
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if (!upper_bound)
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continue;
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/*
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* Found a matching div. Calculate fractional divider needed,
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* rounded up.
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*/
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fracdiv = ((clk->parent->get_rate(clk->parent) / 1000000 * 18 / 2) *
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ns_cycle + 1000 * div - 1) /
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(1000 * div);
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if (fracdiv < 18 || fracdiv > 35) {
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ret = -EINVAL;
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goto out;
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}
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/* Calculate the actual cycle time this results in */
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ps_result = 6250 * div * fracdiv / 27;
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/* Use the fastest result that doesn't break ns_cycle */
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if (ps_result <= lowest_result) {
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lowest_result = ps_result;
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lowest_div = div;
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lowest_fracdiv = fracdiv;
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}
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}
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if (div >= 256 || lowest_result == (u32) -1) {
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ret = -EINVAL;
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goto out;
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}
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pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
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"PIXCLK=%uMHz cycle=%u.%03uns\n",
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lowest_fracdiv, lowest_div,
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480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
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lowest_result / 1000, lowest_result % 1000);
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/* Program ref_pix phase fractional divider */
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reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
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reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
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reg_val |= BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv);
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__raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
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/* Ungate PFD */
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__raw_writel(BM_CLKCTRL_FRAC_CLKGATEPIX,
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CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC_CLR);
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/* Program pix divider */
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reg_val = __raw_readl(clk->scale_reg);
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reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
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reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div);
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__raw_writel(reg_val, clk->scale_reg);
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/* Wait for divider update */
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ret = clk_busy_wait(clk);
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if (ret)
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goto out;
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/* Switch to ref_pix source */
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reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
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reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
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__raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
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out:
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return ret;
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}
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/*
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* We set lcdif_clk's parent as &pll_clk deliberately, although
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* in IC spec lcdif_clk(CLK_PIX) is derived from ref_pix which in turn
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* is derived from PLL. By doing so, users just need to set/get clock rate
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* for lcdif_clk, without need to take care of ref_pix, because the clock
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* driver will automatically calculate the fracdivider for HW_CLKCTRL_FRAC
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* and the divider for HW_CLKCTRL_PIX conjointly.
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*/
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|
static struct clk lcdif_clk = {
|
|
.parent = &pll_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
|
|
.busy_bits = 29,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
|
|
.enable_bits = 31,
|
|
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_bits = 1,
|
|
.get_rate = lcdif_get_rate,
|
|
.set_rate = lcdif_set_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
.flags = CPU_FREQ_TRIG_UPDATE,
|
|
};
|
|
|
|
static unsigned long cpu_get_rate(struct clk *clk)
|
|
{
|
|
unsigned long rate, div;
|
|
rate = (clk->parent->get_rate(clk->parent));
|
|
div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU) &
|
|
BM_CLKCTRL_CPU_DIV_CPU;
|
|
rate = rate/div;
|
|
return rate;
|
|
}
|
|
|
|
static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long frac_rate, root_rate = clk->parent->get_rate(clk->parent);
|
|
unsigned int div = root_rate / rate;
|
|
if (div == 0)
|
|
return root_rate;
|
|
if (clk->parent == &ref_cpu_clk) {
|
|
if (div > 0x3F)
|
|
div = 0x3F;
|
|
return root_rate / div;
|
|
}
|
|
|
|
frac_rate = root_rate % rate;
|
|
div = root_rate / rate;
|
|
if ((div == 0) || (div >= 0x400))
|
|
return root_rate;
|
|
if (frac_rate == 0)
|
|
return rate;
|
|
return rate;
|
|
}
|
|
|
|
static int cpu_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long root_rate = pll_clk.get_rate(&pll_clk);
|
|
int ret = -EINVAL;
|
|
u32 clkctrl_cpu = 1;
|
|
u32 c = clkctrl_cpu;
|
|
u32 clkctrl_frac = 1;
|
|
u32 val;
|
|
u32 reg_val, hclk_reg;
|
|
bool h_autoslow;
|
|
|
|
/* make sure the cpu div_xtal is 1 */
|
|
reg_val = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU);
|
|
reg_val &= ~(BM_CLKCTRL_CPU_DIV_XTAL);
|
|
reg_val |= (1 << BP_CLKCTRL_CPU_DIV_XTAL);
|
|
__raw_writel(reg_val, CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU);
|
|
|
|
if (rate < ref_xtal_get_rate(&ref_xtal_clk))
|
|
return -EINVAL;
|
|
|
|
if (rate == clk_get_rate(clk))
|
|
return 0;
|
|
/* temporaily disable h autoslow to avoid
|
|
* hclk getting too slow while temporarily
|
|
* changing clocks
|
|
*/
|
|
h_autoslow = mx23_enable_h_autoslow(false);
|
|
|
|
if (rate == ref_xtal_get_rate(&ref_xtal_clk)) {
|
|
|
|
/* switch to the 24M source */
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
|
|
/* to avoid bus starvation issues, we'll go ahead
|
|
* and change hbus clock divider to 1 now. Cpufreq
|
|
* or other clock management can lower it later if
|
|
* desired for power savings or other reasons, but
|
|
* there should be no need to with hbus autoslow
|
|
* functionality enabled.
|
|
*/
|
|
|
|
ret = clk_busy_wait(&cpu_clk);
|
|
if (ret) {
|
|
printk(KERN_ERR "* couldn't set\
|
|
up CPU divisor\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_busy_wait(&h_clk);
|
|
if (ret) {
|
|
printk(KERN_ERR "* H_CLK busy timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS);
|
|
hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV);
|
|
hclk_reg |= (1 << BP_CLKCTRL_HBUS_DIV);
|
|
|
|
__raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
|
|
|
|
ret = clk_busy_wait(&cpu_clk);
|
|
if (ret) {
|
|
printk(KERN_ERR "** couldn't set\
|
|
up CPU divisor\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_busy_wait(&h_clk);
|
|
if (ret) {
|
|
printk(KERN_ERR "** CLK busy timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
} else {
|
|
for ( ; c < 0x40; c++) {
|
|
u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) /
|
|
(rate/1000);
|
|
int s1, s2;
|
|
|
|
if (f < 18 || f > 35)
|
|
continue;
|
|
s1 = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu -
|
|
(rate/1000);
|
|
s2 = (root_rate/1000)*18/c/f - (rate/1000);
|
|
if (abs(s1) > abs(s2)) {
|
|
clkctrl_cpu = c;
|
|
clkctrl_frac = f;
|
|
}
|
|
if (s2 == 0)
|
|
break;
|
|
};
|
|
if (c == 0x40) {
|
|
int d = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu -
|
|
(rate/1000);
|
|
if ((abs(d) > 100) || (clkctrl_frac < 18) ||
|
|
(clkctrl_frac > 35))
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* prepare Frac div */
|
|
val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
|
val &= ~(BM_CLKCTRL_FRAC_CPUFRAC);
|
|
val |= (clkctrl_frac << BP_CLKCTRL_FRAC_CPUFRAC);
|
|
|
|
/* prepare clkctrl_cpu div*/
|
|
reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
|
|
reg_val &= ~0x3F;
|
|
reg_val |= clkctrl_cpu;
|
|
|
|
/* set safe hbus clock divider. A divider of 3 ensure that
|
|
* the Vddd voltage required for the cpuclk is sufficiently
|
|
* high for the hbus clock and under 24MHz cpuclk conditions,
|
|
* a divider of at least 3 ensures hbusclk doesn't remain
|
|
* uneccesarily low which hurts performance
|
|
*/
|
|
hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS);
|
|
hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV);
|
|
hclk_reg |= (3 << BP_CLKCTRL_HBUS_DIV);
|
|
|
|
/* if the pll was OFF, we need to turn it ON.
|
|
* Even if it was ON, we want to temporarily
|
|
* increment it by 1 to avoid turning off
|
|
* in the upcoming parent clock change to xtal. This
|
|
* avoids waiting an extra 10us for every cpu clock
|
|
* change between ref_cpu sourced frequencies.
|
|
*/
|
|
pll_enable(&pll_clk);
|
|
pll_clk.ref++;
|
|
|
|
/* switch to XTAL CLK source temparily while
|
|
* we manipulate ref_cpu frequency */
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
|
|
ret = clk_busy_wait(&h_clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-* HCLK busy wait timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_busy_wait(clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-* couldn't set\
|
|
up CPU divisor\n");
|
|
return ret;
|
|
}
|
|
|
|
__raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
|
|
|
|
/* clear the gate */
|
|
__raw_writel(BM_CLKCTRL_FRAC_CLKGATECPU, CLKCTRL_BASE_ADDR +
|
|
HW_CLKCTRL_FRAC_CLR);
|
|
|
|
/* set the ref_cpu integer divider */
|
|
__raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
|
|
|
|
/* wait for the ref_cpu path to become stable before
|
|
* switching over to it
|
|
*/
|
|
|
|
ret = clk_busy_wait(&ref_cpu_clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-** couldn't set\
|
|
up CPU divisor\n");
|
|
return ret;
|
|
}
|
|
|
|
/* change hclk divider to safe value for any ref_cpu
|
|
* value.
|
|
*/
|
|
__raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
|
|
ret = clk_busy_wait(&h_clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-** HCLK busy wait timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
clk_set_parent(clk, &ref_cpu_clk);
|
|
|
|
/* decrement the pll_clk ref count because
|
|
* we temporarily enabled/incremented the count
|
|
* above.
|
|
*/
|
|
pll_clk.ref--;
|
|
|
|
ret = clk_busy_wait(&cpu_clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-*** Couldn't set\
|
|
up CPU divisor\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_busy_wait(&h_clk);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "-*** HCLK busy wait timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
}
|
|
mx23_enable_h_autoslow(h_autoslow);
|
|
return ret;
|
|
}
|
|
|
|
static struct clk cpu_clk = {
|
|
.parent = &ref_cpu_clk,
|
|
.get_rate = cpu_get_rate,
|
|
.round_rate = cpu_round_rate,
|
|
.set_rate = cpu_set_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
|
|
.scale_bits = 0,
|
|
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_bits = 7,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU,
|
|
.busy_bits = 28,
|
|
.xtal_busy_bits = 29,
|
|
};
|
|
|
|
static unsigned long uart_get_rate(struct clk *clk)
|
|
{
|
|
unsigned int div;
|
|
div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) &
|
|
BM_CLKCTRL_XTAL_DIV_UART;
|
|
return clk->parent->get_rate(clk->parent) / div;
|
|
}
|
|
|
|
static struct clk uart_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
|
|
.enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE,
|
|
.get_rate = uart_get_rate,
|
|
};
|
|
|
|
static struct clk pwm_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
|
|
.enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE,
|
|
};
|
|
|
|
static unsigned long clk_32k_get_rate(struct clk *clk)
|
|
{
|
|
return clk->parent->get_rate(clk->parent) / 750;
|
|
}
|
|
|
|
static struct clk clk_32k = {
|
|
.parent = &ref_xtal_clk,
|
|
.flags = RATE_FIXED,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
|
|
.enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE,
|
|
.get_rate = clk_32k_get_rate,
|
|
};
|
|
|
|
static unsigned long lradc_get_rate(struct clk *clk)
|
|
{
|
|
return clk->parent->get_rate(clk->parent) / 16;
|
|
}
|
|
|
|
static struct clk lradc_clk = {
|
|
.parent = &clk_32k,
|
|
.flags = RATE_FIXED,
|
|
.get_rate = lradc_get_rate,
|
|
};
|
|
|
|
static unsigned long x_get_rate(struct clk *clk)
|
|
{
|
|
unsigned long reg;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS) &
|
|
BM_CLKCTRL_XBUS_DIV;
|
|
return clk->parent->get_rate(clk->parent) / reg;
|
|
}
|
|
|
|
static unsigned long x_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned int root_rate, frac_rate;
|
|
unsigned int div;
|
|
root_rate = clk->parent->get_rate(clk->parent);
|
|
frac_rate = root_rate % rate;
|
|
div = root_rate / rate;
|
|
/* while the reference manual specifies that divider
|
|
* values up to 1023 are aloud, other critial SoC compents
|
|
* require higher x clock values at all times. Through
|
|
* limited testing, the lradc functionality to measure
|
|
* the battery voltage and copy this value to the
|
|
* power supply requires at least a 64kHz xclk.
|
|
* so the divider will be limited to 375.
|
|
*/
|
|
if ((div == 0) || (div > 375))
|
|
return root_rate;
|
|
if (frac_rate == 0)
|
|
return rate;
|
|
else
|
|
return root_rate / (div + 1);
|
|
}
|
|
|
|
static int x_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long root_rate;
|
|
unsigned long round_rate;
|
|
unsigned int reg, div;
|
|
root_rate = clk->parent->get_rate(clk->parent);
|
|
|
|
if ((!clk->round_rate) || !(clk->scale_reg))
|
|
return -EINVAL;
|
|
|
|
round_rate = clk->round_rate(clk, rate);
|
|
div = root_rate / round_rate;
|
|
|
|
if (root_rate % round_rate)
|
|
return -EINVAL;
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
|
reg &= ~(BM_CLKCTRL_XBUS_DIV_FRAC_EN | BM_CLKCTRL_XBUS_DIV);
|
|
reg |= BF_CLKCTRL_XBUS_DIV(div);
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
|
|
|
|
return clk_busy_wait(clk);
|
|
|
|
}
|
|
|
|
static struct clk x_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
.get_rate = x_get_rate,
|
|
.set_rate = x_set_rate,
|
|
.round_rate = x_round_rate,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS,
|
|
.busy_bits = 31,
|
|
};
|
|
|
|
|
|
|
|
static struct clk ana_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
};
|
|
|
|
|
|
|
|
static unsigned long xtal_clock32k_get_rate(struct clk *clk)
|
|
{
|
|
if (__raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0) &
|
|
BM_RTC_PERSISTENT0_XTAL32_FREQ)
|
|
return 32000;
|
|
else
|
|
return 32768;
|
|
}
|
|
|
|
static struct clk xtal_clock32k_clk = {
|
|
.get_rate = xtal_clock32k_get_rate,
|
|
};
|
|
|
|
static unsigned long rtc32k_get_rate(struct clk *clk)
|
|
{
|
|
if (clk->parent == &ref_xtal_clk)
|
|
/* mx23 reference manual had error.
|
|
* fixed divider is 750 not 768
|
|
*/
|
|
return clk->parent->get_rate(clk->parent) / 750;
|
|
else
|
|
return xtal_clock32k_get_rate(clk);
|
|
}
|
|
|
|
static struct clk rtc32k_clk = {
|
|
.parent = &xtal_clock32k_clk,
|
|
.get_rate = rtc32k_get_rate,
|
|
};
|
|
|
|
static unsigned long h_get_rate(struct clk *clk)
|
|
{
|
|
unsigned long reg, div;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
div = reg & BM_CLKCTRL_HBUS_DIV;
|
|
return clk->parent->get_rate(clk->parent) / div;
|
|
}
|
|
|
|
static unsigned long h_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned int root_rate, frac_rate;
|
|
unsigned int div;
|
|
root_rate = clk->parent->get_rate(clk->parent);
|
|
frac_rate = root_rate % rate;
|
|
div = root_rate / rate;
|
|
if ((div == 0) || (div >= 0x20))
|
|
return root_rate;
|
|
if (frac_rate == 0)
|
|
return rate;
|
|
else
|
|
return root_rate / (div + 1);
|
|
}
|
|
|
|
static int h_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long root_rate;
|
|
unsigned long round_rate;
|
|
unsigned int reg, div;
|
|
root_rate = clk->parent->get_rate(clk->parent);
|
|
round_rate = h_round_rate(clk, rate);
|
|
div = root_rate / round_rate;
|
|
if ((div == 0) || (div >= 0x20))
|
|
return -EINVAL;
|
|
|
|
if (root_rate % round_rate)
|
|
return -EINVAL;
|
|
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV);
|
|
reg |= BF_CLKCTRL_HBUS_DIV(div);
|
|
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
|
|
|
|
if (clk_busy_wait(clk)) {
|
|
printk(KERN_ERR "couldn't set up AHB divisor\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk h_clk = {
|
|
.parent = &cpu_clk,
|
|
.get_rate = h_get_rate,
|
|
.set_rate = h_set_rate,
|
|
.round_rate = h_round_rate,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS,
|
|
.busy_bits = 31,
|
|
};
|
|
|
|
static struct clk ocrom_clk = {
|
|
.parent = &h_clk,
|
|
};
|
|
|
|
static unsigned long emi_get_rate(struct clk *clk)
|
|
{
|
|
unsigned long reg;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI);
|
|
if (clk->parent == &ref_emi_clk)
|
|
reg = (reg & BM_CLKCTRL_EMI_DIV_EMI);
|
|
else
|
|
reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >>
|
|
BP_CLKCTRL_EMI_DIV_XTAL;
|
|
return clk->parent->get_rate(clk->parent) / reg;
|
|
}
|
|
|
|
static unsigned long emi_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
unsigned long root_rate = clk->parent->get_rate(clk->parent);
|
|
unsigned int div = root_rate / rate;
|
|
if (div == 0)
|
|
return root_rate;
|
|
if (clk->parent == &ref_emi_clk) {
|
|
if (div > 0x3F)
|
|
div = 0x3F;
|
|
return root_rate / div;
|
|
}
|
|
if (div > 0xF)
|
|
div = 0xF;
|
|
return root_rate / div;
|
|
}
|
|
|
|
/* when changing the emi clock, dram access must be
|
|
* disabled. Special handling is needed to perform
|
|
* the emi clock change without touching sdram.
|
|
*/
|
|
static int emi_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = 0;
|
|
|
|
struct mxs_emi_scaling_data sc_data;
|
|
|
|
unsigned long clkctrl_emi;
|
|
unsigned long clkctrl_frac;
|
|
int div = 1;
|
|
unsigned long root_rate, cur_emi_div, cur_emi_frac;
|
|
struct clk *target_parent_p = &ref_xtal_clk;
|
|
|
|
if (rate < ref_xtal_get_rate(&ref_xtal_clk))
|
|
return -EINVAL;
|
|
|
|
if (!mxs_ram_funcs_sz)
|
|
goto out;
|
|
|
|
sc_data.cur_freq = (clk->get_rate(clk)) / 1000 / 1000;
|
|
sc_data.new_freq = rate / 1000 / 1000;
|
|
|
|
if (sc_data.cur_freq == sc_data.new_freq)
|
|
goto out;
|
|
|
|
if (rate != ref_xtal_get_rate(&ref_xtal_clk)) {
|
|
target_parent_p = &ref_emi_clk;
|
|
pll_enable(&pll_clk);
|
|
|
|
root_rate = pll_clk.get_rate(&pll_clk);
|
|
|
|
for (clkctrl_emi = div; clkctrl_emi < 0x3f;
|
|
clkctrl_emi += div) {
|
|
clkctrl_frac = ((root_rate / 1000) * 18 +
|
|
(rate / 1000) * clkctrl_emi / 2) /
|
|
((rate / 1000) * clkctrl_emi);
|
|
if (clkctrl_frac >= 18 && clkctrl_frac <= 35) {
|
|
pr_debug("%s: clkctrl_frac found %ld for %ld\n",
|
|
__func__, clkctrl_frac, clkctrl_emi);
|
|
if (((root_rate / 1000) * 18 /
|
|
clkctrl_frac / clkctrl_emi) / 1000 ==
|
|
rate / 1000 / 1000)
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (clkctrl_emi >= 0x3f)
|
|
return -EINVAL;
|
|
pr_debug("%s: clkctrl_emi %ld, clkctrl_frac %ld\n",
|
|
__func__, clkctrl_emi, clkctrl_frac);
|
|
|
|
sc_data.emi_div = clkctrl_emi;
|
|
sc_data.frac_div = clkctrl_frac;
|
|
}
|
|
|
|
|
|
cur_emi_div = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_EMI) &
|
|
BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_EMI_DIV_EMI);
|
|
cur_emi_frac = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_FRAC) &
|
|
BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_FRAC_EMIFRAC);
|
|
|
|
if ((cur_emi_div == sc_data.emi_div) &&
|
|
(cur_emi_frac == sc_data.frac_div))
|
|
goto out;
|
|
{
|
|
unsigned long iram_phy;
|
|
bool h_autoslow;
|
|
int (*scale)(struct mxs_emi_scaling_data *) =
|
|
iram_alloc(mxs_ram_funcs_sz, &iram_phy);
|
|
|
|
if (NULL == scale) {
|
|
pr_err("%s Not enough iram\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* temporaily disable h autoslow to maximize
|
|
* performance/minimize time spent with no
|
|
* sdram access
|
|
*/
|
|
h_autoslow = mx23_enable_h_autoslow(false);
|
|
|
|
memcpy(scale, mxs_ram_freq_scale, mxs_ram_funcs_sz);
|
|
|
|
local_irq_disable();
|
|
local_fiq_disable();
|
|
|
|
scale(&sc_data);
|
|
|
|
iram_free(iram_phy, mxs_ram_funcs_sz);
|
|
|
|
local_fiq_enable();
|
|
local_irq_enable();
|
|
|
|
/* temporaily disable h autoslow to avoid
|
|
* hclk getting too slow while temporarily
|
|
* changing clocks
|
|
*/
|
|
mx23_enable_h_autoslow(h_autoslow);
|
|
}
|
|
|
|
/* this code is for keeping track of ref counts.
|
|
* and disabling previous parent if necessary
|
|
* actual clkseq changes have already
|
|
* been made.
|
|
*/
|
|
clk_set_parent(clk, target_parent_p);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static struct clk emi_clk = {
|
|
.parent = &ref_emi_clk,
|
|
.get_rate = emi_get_rate,
|
|
.set_rate = emi_set_rate,
|
|
.round_rate = emi_round_rate,
|
|
.set_parent = clkseq_set_parent,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI,
|
|
.enable_bits = BM_CLKCTRL_EMI_CLKGATE,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI,
|
|
.busy_bits = 28,
|
|
.xtal_busy_bits = 29,
|
|
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_bits = 6,
|
|
};
|
|
|
|
static unsigned long ssp_get_rate(struct clk *clk);
|
|
|
|
static int ssp_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
u32 reg, div;
|
|
bool is_clk_enable;
|
|
|
|
is_clk_enable = mx23_is_clk_enabled(clk);
|
|
if (!is_clk_enable)
|
|
local_clk_enable(clk);
|
|
|
|
/* if the desired clock can be sourced from ref_xtal,
|
|
* use ref_xtal to save power
|
|
*/
|
|
if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) &&
|
|
((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0))
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
else
|
|
clk_set_parent(clk, &ref_io_clk);
|
|
|
|
if (rate > PLL_ENABLED_MAX_CLK_SSP)
|
|
rate = PLL_ENABLED_MAX_CLK_SSP;
|
|
|
|
div = (clk_get_rate(clk->parent) + rate - 1) / rate;
|
|
|
|
if (div == 0 || div > BM_CLKCTRL_SSP_DIV)
|
|
goto out;
|
|
|
|
reg = __raw_readl(clk->scale_reg);
|
|
reg &= ~(BM_CLKCTRL_SSP_DIV | BM_CLKCTRL_SSP_DIV_FRAC_EN);
|
|
reg |= div << clk->scale_bits;
|
|
__raw_writel(reg, clk->scale_reg);
|
|
|
|
ret = clk_busy_wait(clk);
|
|
out:
|
|
if (!is_clk_enable)
|
|
local_clk_disable(clk);
|
|
|
|
if (ret != 0)
|
|
printk(KERN_ERR "%s: error %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
static int ssp_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
if (clk->bypass_reg) {
|
|
if (clk->parent == parent)
|
|
return 0;
|
|
if (parent == &ref_io_clk)
|
|
__raw_writel(1 << clk->bypass_bits,
|
|
clk->bypass_reg + CLR_REGISTER);
|
|
else
|
|
__raw_writel(1 << clk->bypass_bits,
|
|
clk->bypass_reg + SET_REGISTER);
|
|
clk->parent = parent;
|
|
ret = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* handle peripheral clocks whose optimal parent dependent on
|
|
* system parameters such as cpu_clk rate. For now, this optimization
|
|
* only occurs to the peripheral clock when it's not in use to avoid
|
|
* handling more complex system clock coordination issues.
|
|
*/
|
|
static int ssp_set_sys_dependent_parent(struct clk *clk)
|
|
{
|
|
if ((clk->ref & CLK_EN_MASK) == 0) {
|
|
if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) {
|
|
clk_set_parent(clk, &ref_io_clk);
|
|
clk_set_rate(clk, PLL_ENABLED_MAX_CLK_SSP);
|
|
} else {
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk));
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk ssp_clk = {
|
|
.parent = &ref_io_clk,
|
|
.get_rate = ssp_get_rate,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
|
|
.enable_bits = BM_CLKCTRL_SSP_CLKGATE,
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
|
|
.busy_bits = 29,
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
|
|
.scale_bits = 0,
|
|
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_bits = 5,
|
|
.set_rate = ssp_set_rate,
|
|
.set_parent = ssp_set_parent,
|
|
.set_sys_dependent_parent = ssp_set_sys_dependent_parent,
|
|
};
|
|
|
|
static unsigned long ssp_get_rate(struct clk *clk)
|
|
{
|
|
unsigned int reg;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP) &
|
|
BM_CLKCTRL_SSP_DIV;
|
|
|
|
return clk->parent->get_rate(clk->parent) / reg;
|
|
}
|
|
|
|
static unsigned long gpmi_get_rate(struct clk *clk)
|
|
{
|
|
unsigned int reg;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) &
|
|
BM_CLKCTRL_GPMI_DIV;
|
|
|
|
return clk->parent->get_rate(clk->parent) / reg;
|
|
}
|
|
|
|
static int gpmi_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
u32 reg, div;
|
|
|
|
/* Make absolutely certain the clock is enabled. */
|
|
local_clk_enable(clk);
|
|
|
|
/* if the desired clock can be sourced from ref_xtal,
|
|
* use ref_xtal to save power
|
|
*/
|
|
if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) &&
|
|
((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0))
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
else
|
|
clk_set_parent(clk, &ref_io_clk);
|
|
|
|
if (rate > PLL_ENABLED_MAX_CLK_SSP)
|
|
rate = PLL_ENABLED_MAX_CLK_GPMI;
|
|
|
|
div = (clk_get_rate(clk->parent) + rate - 1) / rate;
|
|
|
|
if (div == 0 || div > BM_CLKCTRL_GPMI_DIV)
|
|
goto out;
|
|
|
|
reg = __raw_readl(clk->scale_reg);
|
|
reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN);
|
|
reg |= div << clk->scale_bits;
|
|
__raw_writel(reg, clk->scale_reg);
|
|
|
|
ret = clk_busy_wait(clk);
|
|
|
|
out:
|
|
|
|
/* Undo the enable above. */
|
|
local_clk_disable(clk);
|
|
|
|
if (ret != 0)
|
|
printk(KERN_ERR "%s: error %d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
static int gpmi_set_parent(struct clk *clk, struct clk *parent)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
if (clk->bypass_reg) {
|
|
if (clk->parent == parent)
|
|
return 0;
|
|
if (parent == &ref_io_clk)
|
|
__raw_writel(1 << clk->bypass_bits,
|
|
clk->bypass_reg + CLR_REGISTER);
|
|
else
|
|
__raw_writel(1 << clk->bypass_bits,
|
|
clk->bypass_reg + SET_REGISTER);
|
|
clk->parent = parent;
|
|
ret = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* handle peripheral clocks whose optimal parent dependent on
|
|
* system parameters such as cpu_clk rate. For now, this optimization
|
|
* only occurs to the peripheral clock when it's not in use to avoid
|
|
* handling more complex system clock coordination issues.
|
|
*/
|
|
static int gpmi_set_sys_dependent_parent(struct clk *clk)
|
|
{
|
|
|
|
if ((clk->ref & CLK_EN_MASK) == 0) {
|
|
if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) {
|
|
clk_set_parent(clk, &ref_io_clk);
|
|
clk_set_rate(clk, PLL_ENABLED_MAX_CLK_GPMI);
|
|
} else {
|
|
clk_set_parent(clk, &ref_xtal_clk);
|
|
clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk));
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk gpmi_clk = {
|
|
.parent = &ref_io_clk,
|
|
.secondary = 0,
|
|
.flags = 0,
|
|
.set_parent = gpmi_set_parent,
|
|
.set_sys_dependent_parent = gpmi_set_sys_dependent_parent,
|
|
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
|
|
.enable_bits = BM_CLKCTRL_GPMI_CLKGATE,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
|
|
.scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
|
|
.scale_bits = 0,
|
|
.round_rate = 0,
|
|
.set_rate = gpmi_set_rate,
|
|
.get_rate = gpmi_get_rate,
|
|
|
|
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
|
|
.bypass_bits = 4,
|
|
|
|
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
|
|
.busy_bits = 29,
|
|
};
|
|
|
|
static unsigned long pcmspdif_get_rate(struct clk *clk)
|
|
{
|
|
return clk->parent->get_rate(clk->parent) / 4;
|
|
}
|
|
|
|
static struct clk pcmspdif_clk = {
|
|
.parent = &pll_clk,
|
|
.get_rate = pcmspdif_get_rate,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF,
|
|
.enable_bits = BM_CLKCTRL_SPDIF_CLKGATE,
|
|
};
|
|
|
|
/* usb_clk for usb0 */
|
|
static struct clk usb_clk = {
|
|
.parent = &pll_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL,
|
|
.enable_bits = BM_DIGCTL_CTRL_USB_CLKGATE,
|
|
.flags = CPU_FREQ_TRIG_UPDATE,
|
|
};
|
|
|
|
static struct clk audio_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
|
|
.enable_bits = BM_CLKCTRL_XTAL_FILT_CLK24M_GATE,
|
|
};
|
|
|
|
static struct clk vid_clk = {
|
|
.parent = &ref_xtal_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1,
|
|
.enable_bits = BM_CLKCTRL_FRAC1_CLKGATEVID,
|
|
};
|
|
|
|
static struct clk tv108M_ng_clk = {
|
|
.parent = &vid_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV,
|
|
.enable_bits = BM_CLKCTRL_TV_CLK_TV108M_GATE,
|
|
.flags = RATE_FIXED,
|
|
};
|
|
|
|
static struct clk tv27M_clk = {
|
|
.parent = &vid_clk,
|
|
.enable = mx23_raw_enable,
|
|
.disable = mx23_raw_disable,
|
|
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV,
|
|
.enable_bits = BM_CLKCTRL_TV_CLK_TV_GATE,
|
|
.flags = RATE_FIXED,
|
|
};
|
|
|
|
static struct clk_lookup onchip_clocks[] = {
|
|
{
|
|
.con_id = "pll.0",
|
|
.clk = &pll_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_xtal",
|
|
.clk = &ref_xtal_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_cpu",
|
|
.clk = &ref_cpu_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_emi",
|
|
.clk = &ref_emi_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_io.0",
|
|
.clk = &ref_io_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_pix",
|
|
.clk = &ref_pix_clk,
|
|
},
|
|
{
|
|
.con_id = "lcdif",
|
|
.clk = &lcdif_clk,
|
|
},
|
|
{
|
|
.con_id = "xtal_clock32k",
|
|
.clk = &xtal_clock32k_clk,
|
|
},
|
|
{
|
|
.con_id = "rtc",
|
|
.clk = &rtc32k_clk,
|
|
},
|
|
{
|
|
.con_id = "cpu",
|
|
.clk = &cpu_clk,
|
|
},
|
|
{
|
|
.con_id = "h",
|
|
.clk = &h_clk,
|
|
},
|
|
{
|
|
.con_id = "x",
|
|
.clk = &x_clk,
|
|
},
|
|
{
|
|
.con_id = "ocrom",
|
|
.clk = &ocrom_clk,
|
|
},
|
|
{
|
|
.con_id = "clk_32k",
|
|
.clk = &clk_32k,
|
|
},
|
|
{
|
|
.con_id = "uart",
|
|
.clk = &uart_clk,
|
|
},
|
|
{
|
|
.con_id = "pwm",
|
|
.clk = &pwm_clk,
|
|
},
|
|
{
|
|
.con_id = "lradc",
|
|
.clk = &lradc_clk,
|
|
},
|
|
{
|
|
.con_id = "ssp.0",
|
|
.clk = &ssp_clk,
|
|
},
|
|
{
|
|
.con_id = "emi",
|
|
.clk = &emi_clk,
|
|
},
|
|
{
|
|
.con_id = "usb_clk0",
|
|
.clk = &usb_clk,
|
|
},
|
|
{
|
|
.con_id = "audio",
|
|
.clk = &audio_clk,
|
|
},
|
|
{
|
|
.con_id = "spdif",
|
|
.clk = &pcmspdif_clk,
|
|
},
|
|
{
|
|
.con_id = "ref_vid",
|
|
.clk = &vid_clk,
|
|
},
|
|
{
|
|
.con_id = "tv108M_ng",
|
|
.clk = &tv108M_ng_clk,
|
|
},
|
|
{
|
|
.con_id = "tv27M",
|
|
.clk = &tv27M_clk,
|
|
},
|
|
{
|
|
.con_id = "gpmi",
|
|
.clk = &gpmi_clk,
|
|
},
|
|
};
|
|
|
|
/* for debugging */
|
|
#ifdef DEBUG
|
|
static void print_ref_counts(void)
|
|
{
|
|
|
|
printk(KERN_INFO "pll_clk ref count: %i\n",
|
|
pll_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "ref_cpu_clk ref count: %i\n",
|
|
ref_cpu_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "ref_emi_clk ref count: %i\n",
|
|
ref_emi_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "lcdif_clk ref count: %i\n",
|
|
lcdif_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "ref_io_clk ref count: %i\n",
|
|
ref_io_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "ssp_clk ref count: %i\n",
|
|
ssp_clk.ref & CLK_EN_MASK);
|
|
|
|
printk(KERN_INFO "gpmi_clk ref count: %i\n",
|
|
gpmi_clk.ref & CLK_EN_MASK);
|
|
|
|
}
|
|
#endif
|
|
|
|
static void mx23_clock_scan(void)
|
|
{
|
|
unsigned long reg;
|
|
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
|
|
if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU)
|
|
cpu_clk.parent = &ref_xtal_clk;
|
|
if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI)
|
|
emi_clk.parent = &ref_xtal_clk;
|
|
if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP)
|
|
ssp_clk.parent = &ref_xtal_clk;
|
|
if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI)
|
|
gpmi_clk.parent = &ref_xtal_clk;
|
|
|
|
reg = __raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0);
|
|
if (!(reg & BM_RTC_PERSISTENT0_CLOCKSOURCE))
|
|
rtc32k_clk.parent = &ref_xtal_clk;
|
|
};
|
|
|
|
void __init mx23_set_input_clk(unsigned long xtal0,
|
|
unsigned long xtal1,
|
|
unsigned long xtal2, unsigned long enet)
|
|
{
|
|
|
|
}
|
|
|
|
void __init mx23_clock_init(void)
|
|
{
|
|
int i;
|
|
mx23_clock_scan();
|
|
for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++)
|
|
clk_register(&onchip_clocks[i]);
|
|
|
|
clk_enable(&cpu_clk);
|
|
clk_enable(&emi_clk);
|
|
|
|
clk_en_public_h_asm_ctrl(mx23_enable_h_autoslow,
|
|
mx23_set_hbus_autoslow_flags);
|
|
}
|