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4e0a4ca5be
Convert all i.MX platforms over to iram allocator functions. Signed-off-by: Rob Herring <r.herring@freescale.com>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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/*!
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* @file mach-mx3/cpu.c
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*
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* @brief This file contains the CPU initialization code.
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*
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* @ingroup MSL_MX31
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iram_alloc.h>
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#include <mach/hardware.h>
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#include <asm/hardware/cache-l2x0.h>
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/*!
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* CPU initialization. It is called by fixup_mxc_board()
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*/
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void __init mxc_cpu_init(void)
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{
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/* Setup Peripheral Port Remap register for AVIC */
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asm("ldr r0, =0xC0000015 \n\
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mcr p15, 0, r0, c15, c2, 4");
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if (!system_rev) {
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mxc_set_system_rev(0x31, CHIP_REV_2_0);
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}
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}
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/*!
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* Post CPU init code
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*
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* @return 0 always
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*/
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static int __init post_cpu_init(void)
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{
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volatile unsigned long aips_reg;
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iram_init(MX31_IRAM_BASE_ADDR, MX31_IRAM_SIZE);
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/*
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* S/W workaround: Clear the off platform peripheral modules
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* Supervisor Protect bit for SDMA to access them.
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*/
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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return 0;
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}
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postcore_initcall(post_cpu_init);
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