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4e0a4ca5be
Convert all i.MX platforms over to iram allocator functions. Signed-off-by: Rob Herring <r.herring@freescale.com>
86 lines
2.2 KiB
C
86 lines
2.2 KiB
C
/*
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* Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file mach-mx35/cpu.c
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*
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* @brief This file contains the CPU initialization code.
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*
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* @ingroup MSL_MX35
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iram_alloc.h>
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#include <mach/hardware.h>
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#include <asm/hardware/cache-l2x0.h>
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/*!
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* CPU initialization. It is called by fixup_mxc_board()
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*/
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void __init mxc_cpu_init(void)
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{
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/* Setup Peripheral Port Remap register for AVIC */
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asm("ldr r0, =0xC0000015 \n\
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mcr p15, 0, r0, c15, c2, 4");
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/*TODO:Add code to check chip version */
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if (!system_rev)
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mxc_set_system_rev(0x35, CHIP_REV_1_0);
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}
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/*!
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* Post CPU init code
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*
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* @return 0 always
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*/
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static int __init post_cpu_init(void)
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{
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void *l2_base;
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unsigned long aips_reg;
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/* Initialize L2 cache */
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l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
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if (l2_base)
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l2x0_init(l2_base, 0x00030024, 0x00000000);
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iram_init(MX35_IRAM_BASE_ADDR, MX35_IRAM_SIZE);
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/*
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* S/W workaround: Clear the off platform peripheral modules
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* Supervisor Protect bit for SDMA to access them.
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*/
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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return 0;
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}
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postcore_initcall(post_cpu_init);
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