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6c1242b45e
Change registered vpu resource, move vpu iram allocator from device to vpu driver and add vpu_reset function. Signed-off-by: Sammy He <r62914@freescale.com>
108 lines
2.6 KiB
C
108 lines
2.6 KiB
C
/*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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/*!
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* @file mach-mx37/cpu.c
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*
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* @brief This file contains the CPU initialization code.
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*
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* @ingroup MSL_MX37
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iram_alloc.h>
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#include <mach/hardware.h>
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#include <asm/hardware/cache-l2x0.h>
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void __iomem *gpc_base;
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/*!
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* CPU initialization. It is called by fixup_mxc_board()
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*/
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void __init mxc_cpu_init(void)
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{
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if (!system_rev) {
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mxc_set_system_rev(0x37, CHIP_REV_1_0);
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}
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}
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void mx37_vpu_reset(void)
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{
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u32 reg;
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void __iomem *src_base;
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src_base = ioremap(SRC_BASE_ADDR, PAGE_SIZE);
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reg = __raw_readl(src_base);
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reg |= 0x02; /* SW_VPU_RST_BIT */
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__raw_writel(reg, src_base);
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while (__raw_readl(src_base) & 0x02)
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;
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iounmap(src_base);
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}
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#define MXC_ARM1176_BASE IO_ADDRESS(ARM1176_BASE_ADDR)
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/*!
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* Post CPU init code
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*
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* @return 0 always
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*/
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static int __init post_cpu_init(void)
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{
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u32 reg;
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void *l2_base;
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volatile unsigned long aips_reg;
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int iram_size = IRAM_SIZE;
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#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE)
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iram_size -= SCC_RAM_SIZE;
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#endif
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iram_init(IRAM_BASE_ADDR, iram_size);
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gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K);
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/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
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reg = __raw_readl(MXC_ARM1176_BASE + 0x1C);
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reg = 0x8;
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__raw_writel(reg, MXC_ARM1176_BASE + 0x1C);
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/* Initialize L2 cache */
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l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
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if (l2_base) {
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l2x0_init(l2_base, 0x0003001B, 0x00000000);
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}
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
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__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
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aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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aips_reg &= 0x00FFFFFF;
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__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
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return 0;
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}
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postcore_initcall(post_cpu_init);
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