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0d3e4e8356
- add set_rate functionality for x_clk. Added the x_set_rate and x_round_rate functions. A lower x_clk rate will be used for the lowest power 24Mhz state. This implementation to be added later into cpufreq but going ahead and providing the necessary clock driver functionality now. - add enable/disable functionality to ref clocks Assigned the enable and disable function pointers of each of the *_ref_clk tables to the mx23 enable and disable functions. - change lcd clock (default) parent to ref_pix Self explanatory. Previously this was incorrectly assigned directly to the PLL which would cause ref_pix clock to never be gated when not being used which causes very small but unnecessary additional power usage to occur when the LCD is disabled. - add hbus autoslow function to be used by cpufreq Added this function for eventual used by cpufreq driver. - fix pll_enable() delay This delay was changed to match delay requirements given in the mx23 reference manual from the definition of the PLLCTRL0 POWER bitfield. - revise emi_set_rate emi_set_rate had several small issues. The amount of iram it was asking for was set to an arbitrary amount instead of being assigned to the size of the assembly code. Instead, assigning it to the size of the assembly code. When no changes in emiclk speed were being made, we didn't need to spend the time allocating iram, disabling fiqs/irqs, and jumping to the assembly routines Added checks to minimize the time spent in emi_set_rate if then new clock divisors were the same as the old. Added functionality for switching the parent between ref_emi_clk and ref_xtal_clk source based on the clock speed. - added "set_sys_dependent_parent" functionality to allow the reduction some of the peripheral clocks (mainly SSP and GPMI) during the lowest power 24MHz cpu_clk state was needed to allow the PLL to turn off and achieve minimum power usage for that state. The "set_sys_dependent_parent" functionality implements this functionality by checking the cpu speed and changing the parent as needed (but only when the ref count is zero). - other minor cleanup In a couple of locations, I saw the following syntax being used: > -val &= ~(BM_CLKCTRL_FRAC_CPUFRAC << BP_CLKCTRL_FRAC_CPUFRAC); > -val |= clkctrl_frac; This was incorrect because the BM_ definition is already shifted to the correct bitfield location of the register. Shifting it over further by BP_ is a bug. This bug didn't cause problems in these cases because the BP_ value happended to be zero, but needed cleaning up anyway. The mx23_raw_enable was being called without any delays to ensure the clock was ready for use. Added a call to check the clock busy bit to ensure the clock is ready before being used. - Added clock_busy_wait function which replaced all the individual busy_wait handling and properly accounts for clocks with xtal source (which use a separate xtal sourced busy bit). - Cleaned up xtal and rtc clocks/sources functionality. - Added functionality to SSP and GPMI set_rate function to allow changing the parent clock to the xtal if the rate is a factor of 24MHz. Signed-off-by: Robert Lee <robert.lee@freescale.com>