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373272e191
Add MX508 support, and adapt the gpu driver to one image Signed-off-by: Jie Zhou <b30303@freescale.com>
222 lines
6.6 KiB
C
222 lines
6.6 KiB
C
/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __GSL__CONFIG_H
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#define __GSL__CONFIG_H
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/* ------------------------
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* Yamato ringbuffer config
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* ------------------------ */
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static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K;
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static const unsigned int gsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16;
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/* ------------------------
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* Yamato MH arbiter config
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* ------------------------ */
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static const mh_arbiter_config_t gsl_cfg_yamato_mharb = {
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0x10, /* same_page_limit */
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0, /* same_page_granularity */
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1, /* l1_arb_enable */
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1, /* l1_arb_hold_enable */
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0, /* l2_arb_control */
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1, /* page_size */
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1, /* tc_reorder_enable */
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1, /* tc_arb_hold_enable */
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1, /* in_flight_limit_enable */
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0x8, /* in_flight_limit */
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1, /* cp_clnt_enable */
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1, /* vgt_clnt_enable */
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1, /* tc_clnt_enable */
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1, /* rb_clnt_enable */
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1, /* pa_clnt_enable */
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};
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/* ---------------------
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* G12 MH arbiter config
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* --------------------- */
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static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = {
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0x10, /* SAME_PAGE_LIMIT */
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0, /* SAME_PAGE_GRANULARITY */
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1, /* L1_ARB_ENABLE */
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1, /* L1_ARB_HOLD_ENABLE */
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0, /* L2_ARB_CONTROL */
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1, /* PAGE_SIZE */
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1, /* TC_REORDER_ENABLE */
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1, /* TC_ARB_HOLD_ENABLE */
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0, /* IN_FLIGHT_LIMIT_ENABLE */
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0x8, /* IN_FLIGHT_LIMIT */
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1, /* CP_CLNT_ENABLE */
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1, /* VGT_CLNT_ENABLE */
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1, /* TC_CLNT_ENABLE */
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1, /* RB_CLNT_ENABLE */
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1, /* PA_CLNT_ENABLE */
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};
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/* -----------------------------
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* interrupt block register data
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* ----------------------------- */
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static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = {
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{ /* Yamato MH */
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GSL_INTR_BLOCK_YDX_MH,
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GSL_INTR_YDX_MH_AXI_READ_ERROR,
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GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
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mmMH_INTERRUPT_STATUS,
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mmMH_INTERRUPT_CLEAR,
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mmMH_INTERRUPT_MASK
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},
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{ /* Yamato CP */
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GSL_INTR_BLOCK_YDX_CP,
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GSL_INTR_YDX_CP_SW_INT,
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GSL_INTR_YDX_CP_RING_BUFFER,
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mmCP_INT_STATUS,
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mmCP_INT_ACK,
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mmCP_INT_CNTL
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},
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{ /* Yamato RBBM */
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GSL_INTR_BLOCK_YDX_RBBM,
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GSL_INTR_YDX_RBBM_READ_ERROR,
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GSL_INTR_YDX_RBBM_GUI_IDLE,
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mmRBBM_INT_STATUS,
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mmRBBM_INT_ACK,
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mmRBBM_INT_CNTL
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},
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{ /* Yamato SQ */
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GSL_INTR_BLOCK_YDX_SQ,
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GSL_INTR_YDX_SQ_PS_WATCHDOG,
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GSL_INTR_YDX_SQ_VS_WATCHDOG,
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mmSQ_INT_STATUS,
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mmSQ_INT_ACK,
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mmSQ_INT_CNTL
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},
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{ /* G12 */
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GSL_INTR_BLOCK_G12,
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GSL_INTR_G12_MH,
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#ifndef _Z180
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GSL_INTR_G12_FBC,
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#else
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GSL_INTR_G12_FIFO,
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#endif /* _Z180 */
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(ADDR_VGC_IRQSTATUS >> 2),
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(ADDR_VGC_IRQSTATUS >> 2),
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(ADDR_VGC_IRQENABLE >> 2)
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},
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{ /* G12 MH */
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GSL_INTR_BLOCK_G12_MH,
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GSL_INTR_G12_MH_AXI_READ_ERROR,
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GSL_INTR_G12_MH_MMU_PAGE_FAULT,
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ADDR_MH_INTERRUPT_STATUS, /* G12 MH offsets are considered to be dword based, therefore no down shift */
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ADDR_MH_INTERRUPT_CLEAR,
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ADDR_MH_INTERRUPT_MASK
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},
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};
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/* -----------------------
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* interrupt mask bit data
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* ----------------------- */
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static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = {
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MH_INTERRUPT_MASK__AXI_READ_ERROR,
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MH_INTERRUPT_MASK__AXI_WRITE_ERROR,
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MH_INTERRUPT_MASK__MMU_PAGE_FAULT,
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CP_INT_CNTL__SW_INT_MASK,
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CP_INT_CNTL__T0_PACKET_IN_IB_MASK,
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CP_INT_CNTL__OPCODE_ERROR_MASK,
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CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK,
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CP_INT_CNTL__RESERVED_BIT_ERROR_MASK,
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CP_INT_CNTL__IB_ERROR_MASK,
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CP_INT_CNTL__IB2_INT_MASK,
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CP_INT_CNTL__IB1_INT_MASK,
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CP_INT_CNTL__RB_INT_MASK,
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RBBM_INT_CNTL__RDERR_INT_MASK,
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RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK,
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RBBM_INT_CNTL__GUI_IDLE_INT_MASK,
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SQ_INT_CNTL__PS_WATCHDOG_MASK,
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SQ_INT_CNTL__VS_WATCHDOG_MASK,
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(1 << VGC_IRQENABLE_MH_FSHIFT),
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(1 << VGC_IRQENABLE_G2D_FSHIFT),
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(1 << VGC_IRQENABLE_FIFO_FSHIFT),
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#ifndef _Z180
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(1 << VGC_IRQENABLE_FBC_FSHIFT),
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#endif
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(1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT),
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(1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT),
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(1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT),
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};
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/* -----------------
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* mmu register data
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* ----------------- */
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static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = {
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{ /* Yamato */
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mmMH_MMU_CONFIG,
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mmMH_MMU_MPU_BASE,
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mmMH_MMU_MPU_END,
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mmMH_MMU_VA_RANGE,
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mmMH_MMU_PT_BASE,
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mmMH_MMU_PAGE_FAULT,
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mmMH_MMU_TRAN_ERROR,
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mmMH_MMU_INVALIDATE,
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},
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{ /* G12 - MH offsets are considered to be dword based, therefore no down shift */
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ADDR_MH_MMU_CONFIG,
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ADDR_MH_MMU_MPU_BASE,
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ADDR_MH_MMU_MPU_END,
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ADDR_MH_MMU_VA_RANGE,
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ADDR_MH_MMU_PT_BASE,
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ADDR_MH_MMU_PAGE_FAULT,
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ADDR_MH_MMU_TRAN_ERROR,
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ADDR_MH_MMU_INVALIDATE,
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},
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};
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/* -----------------
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* mh interrupt data
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* ----------------- */
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static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] =
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{
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{ /* Yamato */
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GSL_INTR_YDX_MH_AXI_READ_ERROR,
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GSL_INTR_YDX_MH_AXI_WRITE_ERROR,
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GSL_INTR_YDX_MH_MMU_PAGE_FAULT,
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},
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{ /* G12 */
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GSL_INTR_G12_MH_AXI_READ_ERROR,
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GSL_INTR_G12_MH_AXI_WRITE_ERROR,
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GSL_INTR_G12_MH_MMU_PAGE_FAULT,
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}
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};
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#endif /* __GSL__CONFIG_H */
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