diff --git a/src/armv5te/coproc.cpp b/src/armv5te/coproc.cpp index 338017a..0dcd534 100644 --- a/src/armv5te/coproc.cpp +++ b/src/armv5te/coproc.cpp @@ -84,8 +84,11 @@ void do_cp15_mcr(uint32_t insn) error("Bad or unimplemented control register value: %x (unsupported: %x)\n", value, (value & 0xFFFF8CF8) ^ 0x00050078); */ arm.control = value; - if (change & 1) // MMU is being turned on or off - addr_cache_flush(); + if (change & 1){ + // MMU is being turned on or off + addr_cache_flush(); + emuprintf("Turned MMU %s\n", value & 1 ? "on" : "off"); + } break; } case 0x020000: /* MCR p15, 0, , c2, c0, 0: Translation Table Base Register */ diff --git a/src/pxa260/pxa260.h b/src/pxa260/pxa260.h index 7021655..6ff6a95 100644 --- a/src/pxa260/pxa260.h +++ b/src/pxa260/pxa260.h @@ -30,6 +30,6 @@ uint32_t pxa260GetRegister(uint8_t reg);//only for debugging #define pxa260GetPc() pxa260GetRegister(15)//only for debugging uint32_t pxa260GetCpsr(void);//only for debugging uint32_t pxa260GetSpsr(void);//only for debugging -uint64_t pxa260ReadArbitraryMemory(uint32_t address, uint8_t size);//only for debugging +uint64_t pxa260ReadArbitraryMemory(uint32_t address, uint8_t size);//only for debugging, uses physical address not MMU mapped #endif diff --git a/src/pxa260/pxa260Udc.c b/src/pxa260/pxa260Udc.c index 4aa2da6..f844522 100644 --- a/src/pxa260/pxa260Udc.c +++ b/src/pxa260/pxa260Udc.c @@ -38,7 +38,7 @@ uint32_t pxa260UdcReadWord(uint32_t address){ switch(address){ case UDCCR: //TODO: is incomplete - debugLog("Snoot boop, PC:0x%08X\n", pxa260GetPc()); + debugLog("PXA260 UDC UDCCR read, PC:0x%08X\n", pxa260GetPc()); return pxa260UdcUdccr; case UDCCS0: @@ -70,6 +70,12 @@ void pxa260UdcWriteWord(uint32_t address, uint32_t value){ pxa260UdcUdccr = value & 0xFF; return; + case UDCCS0: + pxa260UdcUdccs0 &= ~(value & 0x91);//clear clear on 1 bits + pxa260UdcUdccs0 |= value & 0x26;//set set on 1 bits + //TODO: need to update interrupts + return; + case UICR0: pxa260UdcUicr0 = value & 0xFF; //TODO: need to update interrupts