From 433d64faaca650f989ca79d2574472093d54fe5a Mon Sep 17 00:00:00 2001
From: meepingsnesroms <guicrith@gmail.com>
Date: Sun, 8 Apr 2018 16:01:02 -0700
Subject: [PATCH] Add fixes from the correction datasheet

---
 src/hardwareRegisterNames.h | 7 +++++--
 src/hardwareRegisters.c     | 8 +++++---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/hardwareRegisterNames.h b/src/hardwareRegisterNames.h
index b2a447a..c96ee8e 100644
--- a/src/hardwareRegisterNames.h
+++ b/src/hardwareRegisterNames.h
@@ -15,7 +15,10 @@
 #define CSGBB     0x102 // Chip Select Group B Base Register
 #define CSGBC     0x104 // Chip Select Group C Base Register
 #define CSGBD     0x106 // Chip Select Group D Base Register
-#define CSUGBA    0x108 // Chip Select Upper Group Address Register
+#define CSUGBA    0x108 // Chip Select Upper Group Address Register
+#define CSCTRL1   0x10A // Chip Select Control Register 1
+#define CSCTRL2   0x10C // Chip Select Control Register 2
+#define CSCTRL3   0x150 // Chip Select Control Register 3
 #define CSA       0x110 // Group A Chip Select Register
 #define CSC       0x114 // Group C Chip Select Register
 #define CSD       0x116 // Group D Chip Select Register
@@ -150,7 +153,7 @@
 #define LPICF     0xA20 // Panel Interface Config Register
 #define LPXCD     0xA25 // Pixel Clock Divider Register
 #define LCKCON    0xA27 // Clocking Control Register
-#define LRRA      0xA29 // LCD Refresh Rate Adjustment Register
+#define LRRA      0xA28 // LCD Refresh Rate Adjustment Register
 // Reserved       0xA2B // Octet Terminal Count Register On Original Dragonball
 #define LFRCM     0xA31 // Frame Rate Control Modulation Register
 #define LGPMR     0xA33 // Gray Palette Mapping Register
diff --git a/src/hardwareRegisters.c b/src/hardwareRegisters.c
index 6842270..34884ca 100644
--- a/src/hardwareRegisters.c
+++ b/src/hardwareRegisters.c
@@ -924,6 +924,8 @@ void resetHwRegisters(){
    registerArrayWrite16(CSA, 0x00B0);
    registerArrayWrite16(CSD, 0x0200);
    registerArrayWrite16(EMUCS, 0x0060);
+   registerArrayWrite16(CSCTRL2, 0x1000);
+   registerArrayWrite16(CSCTRL3, 0x9C00);
    
    //phase lock loop
    registerArrayWrite16(PLLCR, 0x24B3);
@@ -984,8 +986,8 @@ void resetHwRegisters(){
    registerArrayWrite16(TCMP2, 0xFFFF);
    
    //serial i/o
-   registerArrayWrite16(UBAUD1, 0x003F);
-   registerArrayWrite16(UBAUD2, 0x003F);
+   registerArrayWrite16(UBAUD1, 0x0002);
+   registerArrayWrite16(UBAUD2, 0x0002);
    registerArrayWrite16(HMARK, 0x0102);
    
    //lcd control registers, unused since the sed1376 is present
@@ -994,7 +996,7 @@ void resetHwRegisters(){
    registerArrayWrite16(LYMAX, 0x01FF);
    registerArrayWrite16(LCWCH, 0x0101);
    registerArrayWrite8(LBLKC, 0x7F);
-   registerArrayWrite8(LRRA, 0xFF);
+   registerArrayWrite16(LRRA, 0x00FF);
    registerArrayWrite8(LGPMR, 0x84);
    registerArrayWrite8(DMACR, 0x62);