diff --git a/qtBuildSystem/Mu/Mu.pro b/qtBuildSystem/Mu/Mu.pro index ff92ed3..5da8b49 100644 --- a/qtBuildSystem/Mu/Mu.pro +++ b/qtBuildSystem/Mu/Mu.pro @@ -22,6 +22,7 @@ DEFINES += QT_DEPRECATED_WARNINGS # You can also select to disable deprecated APIs only up to a certain version of Qt. DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000 # disables all the APIs deprecated before Qt 6.0.0 +# OS 5 support is mandatory for the QT port CONFIG += support_palm_os5 windows{ @@ -158,6 +159,7 @@ support_palm_os5{ ../../src/armv5te/arm_interpreter.cpp \ ../../src/armv5te/cpu.cpp \ ../../src/armv5te/coproc.cpp \ + ../../src/armv5te/disasm.c \ ../../src/armv5te/emuVarPool.c \ ../../src/armv5te/thumb_interpreter.cpp \ ../../src/armv5te/mem.c \ @@ -190,6 +192,7 @@ support_palm_os5{ ../../src/armv5te/asmcode.h \ ../../src/armv5te/bitfield.h \ ../../src/armv5te/cpu.h \ + ../../src/armv5te/disasm.h \ ../../src/armv5te/emu.h \ ../../src/armv5te/mem.h \ ../../src/armv5te/translate.h \ diff --git a/qtBuildSystem/Mu/debugviewer.cpp b/qtBuildSystem/Mu/debugviewer.cpp index 58d8131..bc00181 100644 --- a/qtBuildSystem/Mu/debugviewer.cpp +++ b/qtBuildSystem/Mu/debugviewer.cpp @@ -94,6 +94,19 @@ void DebugViewer::on_debugGetHexValues_clicked(){ } } +void DebugViewer::on_debugDecompile_clicked(){ + EmuWrapper& emu = ((MainWindow*)parentWidget())->emu; + int64_t address = numberFromString(ui->debugAddress->text(), true/*negative not allowed*/); + int64_t length = numberFromString(ui->debugLength->text(), true/*negative not allowed*/); + + ui->debugValueList->clear(); + + if(address != INT64_MIN && length != INT64_MIN && length != 0) + ui->debugValueList->addItems(emu.debugDisassemble(address, length).split('\n')); + else + ui->debugValueList->addItem("Invalid Parameters"); +} + void DebugViewer::on_debug8Bit_clicked(){ bitsPerEntry = 8; debugRadioButtonHandler(); diff --git a/qtBuildSystem/Mu/debugviewer.h b/qtBuildSystem/Mu/debugviewer.h index d37cb74..f875477 100644 --- a/qtBuildSystem/Mu/debugviewer.h +++ b/qtBuildSystem/Mu/debugviewer.h @@ -23,6 +23,7 @@ private slots: void debugRadioButtonHandler(); void on_debugGetHexValues_clicked(); + void on_debugDecompile_clicked(); void on_debug8Bit_clicked(); void on_debug16Bit_clicked(); diff --git a/qtBuildSystem/Mu/debugviewer.ui b/qtBuildSystem/Mu/debugviewer.ui index 6631a45..414e54f 100644 --- a/qtBuildSystem/Mu/debugviewer.ui +++ b/qtBuildSystem/Mu/debugviewer.ui @@ -45,51 +45,19 @@ - - + + - 8bit + Dump To File + + + false - + - - - - 16bit - - - - - - - File Path - - - - - - - Address - - - - - - - Length - - - - - - - 32bit - - - @@ -100,34 +68,28 @@ - - + + - Show Registers + 32bit - - + + - Show Debug Logs + 8bit - - false + + + + + + Length - - - Dump To File - - - false - - - - Erase Debug Logs @@ -137,7 +99,24 @@ - + + + + Show Debug Logs + + + false + + + + + + + 16bit + + + + Dump To Terminal @@ -147,6 +126,34 @@ + + + + Address + + + + + + + File Path + + + + + + + Show Registers + + + + + + + Decompile + + + diff --git a/qtBuildSystem/Mu/emuwrapper.cpp b/qtBuildSystem/Mu/emuwrapper.cpp index 71f3e05..2a33fd4 100644 --- a/qtBuildSystem/Mu/emuwrapper.cpp +++ b/qtBuildSystem/Mu/emuwrapper.cpp @@ -22,7 +22,9 @@ extern "C"{ #include "../../src/flx68000.h" +#include "../../src/m68k/m68k.h" #include "../../src/pxa260/pxa260.h" +#include "../../src/armv5te/disasm.h" #include "../../src/debug/sandbox.h" } @@ -528,3 +530,32 @@ uint64_t EmuWrapper::debugGetEmulatorMemory(uint32_t address, uint8_t size){ return pxa260ReadArbitraryMemory(address, size); return flx68000ReadArbitraryMemory(address, size); } + +QString EmuWrapper::debugDisassemble(uint32_t address, uint32_t opcodes){ + QString output = ""; + + if(palmEmulatingTungstenT3){ + for(uint32_t index = 0; index < opcodes; index++){ + address += disasm_arm_insn(address); + output += disasmReturnBuf; + output += '\n'; + } + } + else{ + char temp[100]; + + for(uint32_t index = 0; index < opcodes; index++){ + uint8_t opcodeSize = m68k_disassemble(temp, address, M68K_CPU_TYPE_DBVZ); + QString opcodeHex = ""; + + for(uint8_t opcodeByteIndex = 0; opcodeByteIndex < opcodeSize; opcodeByteIndex++) + opcodeHex += QString::asprintf("%02X", flx68000ReadArbitraryMemory(address + opcodeByteIndex, 8)); + + output += QString::asprintf("0x%08X: 0x%s\t%s \n", address, opcodeHex.toStdString().c_str(), temp); + + address += opcodeSize; + } + } + + return output; +} diff --git a/qtBuildSystem/Mu/emuwrapper.h b/qtBuildSystem/Mu/emuwrapper.h index 9bf7e7b..5e00fb9 100644 --- a/qtBuildSystem/Mu/emuwrapper.h +++ b/qtBuildSystem/Mu/emuwrapper.h @@ -81,4 +81,5 @@ public: QVector& debugGetDuplicateLogEntryCount(); QString debugGetCpuRegisterString(); uint64_t debugGetEmulatorMemory(uint32_t address, uint8_t size); + QString debugDisassemble(uint32_t address, uint32_t opcodes); }; diff --git a/src/armv5te/arm_interpreter.cpp b/src/armv5te/arm_interpreter.cpp index b5485a2..e717843 100644 --- a/src/armv5te/arm_interpreter.cpp +++ b/src/armv5te/arm_interpreter.cpp @@ -376,7 +376,7 @@ void do_arm_instruction(Instruction i) value <<= 1; set_reg(insn >> 12 & 15, zeros); } else if ((insn & 0xFFF000F0) == 0xE1200070) { - gui_debug_printf("Software breakpoint at %08x (%04x)\n", + gui_debug_printf("Software breakpoint at %08X (%04X)\n", arm.reg[15], (insn >> 4 & 0xFFF0) | (insn & 0xF)); debugger(DBG_EXEC_BREAKPOINT, 0); } else diff --git a/src/armv5te/armsnippets.h b/src/armv5te/armsnippets.h index 1d049bd..facd254 100644 --- a/src/armv5te/armsnippets.h +++ b/src/armv5te/armsnippets.h @@ -1,7 +1,7 @@ /* Declarations for armsnippets */ -#ifndef _H_ARMSNIPPETS -#define _H_ARMSNIPPETS +#ifndef H_ARMSNIPPETS +#define H_ARMSNIPPETS //#include diff --git a/src/armv5te/asmcode.h b/src/armv5te/asmcode.h index 62293cd..d36fdcb 100644 --- a/src/armv5te/asmcode.h +++ b/src/armv5te/asmcode.h @@ -1,7 +1,7 @@ /* Declarations for asmcode.S */ -#ifndef _H_ASMCODE -#define _H_ASMCODE +#ifndef H_ASMCODE +#define H_ASMCODE #include "emu.h" diff --git a/src/armv5te/cpu.cpp b/src/armv5te/cpu.cpp index ba51ac9..5a97c2f 100644 --- a/src/armv5te/cpu.cpp +++ b/src/armv5te/cpu.cpp @@ -65,7 +65,7 @@ void cpu_arm_loop() else { if(*flags_ptr & RF_EXEC_BREAKPOINT) - gui_debug_printf("Breakpoint at 0x%08x\n", arm.reg[15]); + gui_debug_printf("Breakpoint at 0x%08X\n", arm.reg[15]); enter_debugger: uint32_t pc = arm.reg[15]; debugger(DBG_EXEC_BREAKPOINT, 0); @@ -115,7 +115,7 @@ void fix_pc_for_fault() void prefetch_abort(uint32_t mva, uint8_t status) { - warn("Prefetch abort: address=%08x status=%02x\n", mva, status); + warn("Prefetch abort: address=%08X status=%02X\n", mva, status); arm.reg[15] += 4; // Fault address register not changed arm.instruction_fault_status = status; @@ -128,7 +128,7 @@ void prefetch_abort(uint32_t mva, uint8_t status) void data_abort(uint32_t mva, uint8_t status) { fix_pc_for_fault(); - warn("Data abort: address=%08x status=%02x instruction at %08x\n", mva, status, arm.reg[15]); + warn("Data abort: address=%08X status=%02X instruction at %08X\n", mva, status, arm.reg[15]); arm.reg[15] += 8; arm.fault_address = mva; arm.data_fault_status = status; @@ -195,7 +195,7 @@ void * FASTCALL read_instruction(uint32_t addr) { ptr = addr_cache_miss(addr, false, prefetch_abort); if (!ptr) - error("Bad PC: %08x\n", addr); + error("Bad PC: %08X\n", addr); } return ptr; #endif diff --git a/src/armv5te/debug.h b/src/armv5te/debug.h index 0544325..f3500da 100644 --- a/src/armv5te/debug.h +++ b/src/armv5te/debug.h @@ -1,27 +1,22 @@ /* Declarations for debug.c */ -#ifndef _H_DEBUG -#define _H_DEBUG +#ifndef H_DEBUG +#define H_DEBUG #include #include #include #include +//#include "mmu.h" + #ifdef __cplusplus #include -//extern std::string ln_target_folder; extern "C" { #endif extern FILE *debugger_input; - -/* -extern bool gdb_connected; -extern bool in_debugger; -extern int rdbg_port; -*/ #define gdb_connected false #define in_debugger false #define rdbg_port 0 @@ -44,6 +39,13 @@ bool rdebug_bind(unsigned int port); void rdebug_quit(); */ #define virt_mem_ptr(x, y) NULL +/* +static inline void *virt_mem_ptr(uint32_t addr, uint32_t size) { + //this is needed by the disasembler + // Note: this is not guaranteed to be correct when range crosses page boundary + return (void *)(intptr_t)phys_mem_ptr(mmu_translate(addr, false, NULL, NULL), size); +} +*/ #define backtrace(x) #define process_debug_cmd(x) 0 #define debugger(x, y) diff --git a/src/armv5te/disasm.c b/src/armv5te/disasm.c new file mode 100644 index 0000000..d2fb0d3 --- /dev/null +++ b/src/armv5te/disasm.c @@ -0,0 +1,545 @@ +#include + +#include "debug.h" +#include "disasm.h" +#include "emu.h" + + +char disasmReturnBuf[80]; + + +static char *strcpy2(char *dest, const char *src) { + while ((*dest = *src)) { dest++; src++; } + return dest; +} + +const char reg_name[16][4] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" +}; + +static const char condcode[16][3] = { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "", "2" +}; + +enum suffix { + none_, + XY, // halfword signed mul + Y, // halfword signed mul + S, // Bit 20 S: alu, MUL etc + B, // Bit 22 B: LDR/STR, SWP + BT, // Bit 21 T: LDR/STR with postindex (bit 24=0) + M, // Bit 23-24 DA/IA/DB/IB + H, // H/SB/SH + D, // double-word insn + L, // Bit 22 L: LDC/STC +}; + +enum operand { + none, + REG0, // Bits 0-3 specify register + REG8, // Bits 8-11 specify register + REG12, // Bits 12-15 specify register + REG16, // Bits 16-19 specify register + PSR, + SHFOP, // Bits 0-11 specify shifted reg or immediate + IMMED, // Bits 0-11 specify rotated immediate + MEM, + MEMH, + MEM16, + MULTI, + BRCH, // Bits 0-23 specify branch target + BRCHT, // Bits 0-24 specify branch target for THUMB code + COPR, // Bits 8-11 specify coprocessor number + CDP, MRC, MRRC, MEMC, + BKPT, SWI, +}; + +static const struct arm_insn { + uint32_t mask; + uint32_t value; + char name[7]; + uint8_t suffix; + uint8_t op1, op2, op3, op4; +} table[] = { +{0xFD70F000,0xF550F000, "pld", 0, MEM, none, none, none }, +{0xFE000000,0xFA000000, "blx", 0, BRCHT, none, none, none }, + +/* Coprocessor instructions may have any condition field */ +{ 0xFF00000, 0xC400000, "mcrr", 0, COPR, MRRC, none, none }, +{ 0xFF00000, 0xC500000, "mrrc", 0, COPR, MRRC, none, none }, +{ 0xE100000, 0xC000000, "stc", L, COPR, MEMC, none, none }, +{ 0xE100000, 0xC100000, "ldc", L, COPR, MEMC, none, none }, +{ 0xF000010, 0xE000000, "cdp", 0, COPR, CDP, none, none }, +{ 0xF100010, 0xE000010, "mcr", 0, COPR, MRC, none, none }, +{ 0xF100010, 0xE100010, "mrc", 0, COPR, MRC, none, none }, + +/* No other instructions are valid with condition field 1111 */ +{0xF0000000,0xF0000000, "???", 0, none, none, none, none }, + +{ 0xFE0F0F0, 0x0000090, "mul", S, REG16, REG0, REG8, none }, +{ 0xFE000F0, 0x0200090, "mla", S, REG16, REG0, REG8, REG12 }, +{ 0xFE000F0, 0x0800090, "umull", S, REG12, REG16, REG0, REG8 }, +{ 0xFE000F0, 0x0A00090, "umlal", S, REG12, REG16, REG0, REG8 }, +{ 0xFE000F0, 0x0C00090, "smull", S, REG12, REG16, REG0, REG8 }, +{ 0xFE000F0, 0x0E00090, "smlal", S, REG12, REG16, REG0, REG8 }, +{ 0xFB00FF0, 0x1000090, "swp", B, REG12, REG0, MEM16, none }, +{ 0xE0000F0, 0x0000090, "???", 0, none, none, none, none }, + +{ 0xE1000F0, 0x00000B0, "str", H, REG12, MEMH, none, none }, +{ 0xE1010F0, 0x00000D0, "ldr", D, REG12, MEMH, none, none }, +{ 0xE1010F0, 0x00000F0, "str", D, REG12, MEMH, none, none }, +{ 0xE1000F0, 0x01000B0, "ldr", H, REG12, MEMH, none, none }, +{ 0xE1000F0, 0x01000D0, "ldr", H, REG12, MEMH, none, none }, +{ 0xE1000F0, 0x01000F0, "ldr", H, REG12, MEMH, none, none }, + +{ 0xFBF0FFF, 0x10F0000, "mrs", 0, REG12, PSR, none, none }, +{ 0xFB0FFF0, 0x120F000, "msr", 0, PSR, REG0, none, none }, +{ 0xFF00FF0, 0x1000050, "qadd", 0, REG12, REG0, REG16, none }, +{ 0xFF00FF0, 0x1200050, "qsub", 0, REG12, REG0, REG16, none }, +{ 0xFF00FF0, 0x1400050, "qdadd", 0, REG12, REG0, REG16, none }, +{ 0xFF00FF0, 0x1600050, "qdsub", 0, REG12, REG0, REG16, none }, +{0xFFF000F0,0xE1200070, "bkpt", 0, BKPT, none, none, none }, + +{ 0xFB0F000, 0x320F000, "msr", 0, PSR, IMMED, none, none }, + +{ 0xFF00090, 0x1000080, "smla", XY,REG16, REG0, REG8, REG12 }, +{ 0xFF000B0, 0x1200080, "smlaw", Y, REG16, REG0, REG8, REG12 }, +{ 0xFF0F0B0, 0x12000A0, "smulw", Y, REG16, REG0, REG8, none }, +{ 0xFF00090, 0x1400080, "smlal", XY,REG12, REG16, REG0, REG8 }, +{ 0xFF0F090, 0x1600080, "smul", XY,REG16, REG0, REG8, none }, + +{ 0xFFFFFF0, 0x12FFF10, "bx", 0, REG0, none, none, none }, +{ 0xFFFFFF0, 0x12FFF20, "bxj", 0, REG0, none, none, none }, +{ 0xFFFFFF0, 0x12FFF30, "blx", 0, REG0, none, none, none }, + +{ 0xFFF0FF0, 0x16F0F10, "clz", 0, REG12, REG0, none, none }, + +{ 0xDE00000, 0x0000000, "and", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0200000, "eor", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0400000, "sub", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0600000, "rsb", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0800000, "add", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0A00000, "adc", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0C00000, "sbc", S, REG12, REG16, SHFOP, none }, +{ 0xDE00000, 0x0E00000, "rsc", S, REG12, REG16, SHFOP, none }, +{ 0xDF0F000, 0x1100000, "tst", 0, REG16, SHFOP, none, none }, +{ 0xDF0F000, 0x1300000, "teq", 0, REG16, SHFOP, none, none }, +{ 0xDF0F000, 0x1500000, "cmp", 0, REG16, SHFOP, none, none }, +{ 0xDF0F000, 0x1700000, "cmn", 0, REG16, SHFOP, none, none }, +{ 0xDE00000, 0x1800000, "orr", S, REG12, REG16, SHFOP, none }, +{ 0xDEF0000, 0x1A00000, "mov", S, REG12, SHFOP, none, none }, +{ 0xDE00000, 0x1C00000, "bic", S, REG12, REG16, SHFOP, none }, +{ 0xDEF0000, 0x1E00000, "mvn", S, REG12, SHFOP, none, none }, + +/* 4000000-9FFFFFF: word-sized memory accesses */ +{ 0xD100000, 0x4000000, "str", BT,REG12, MEM, none, none }, +{ 0xD100000, 0x4100000, "ldr", BT,REG12, MEM, none, none }, +{ 0xD100000, 0x5000000, "str", B, REG12, MEM, none, none }, +{ 0xD100000, 0x5100000, "ldr", B, REG12, MEM, none, none }, +{ 0xE100000, 0x8000000, "stm", M, MULTI, none, none, none }, +{ 0xE100000, 0x8100000, "ldm", M, MULTI, none, none, none }, + +/* A000000-BFFFFFF: branches */ +{ 0xF000000, 0xA000000, "b", 0, BRCH, none, none, none }, +{ 0xF000000, 0xB000000, "bl", 0, BRCH, none, none, none }, + +/* F000000-FFFFFFF: software interrupt */ +{ 0xF000000, 0xF000000, "swi", 0, SWI, none, none, none }, + +/* Catch-all */ +{ 0x0000000, 0x0000000, "???", 0, none, none, none, none }, +}; + +static char *do_shift(char *out, uint32_t insn) { + static const char shifts[4][4] = { "lsl", "lsr", "asr", "ror" }; + int shift = insn >> 7 & 31; + int stype = insn >> 5 & 3; + + out = strcpy2(out, reg_name[insn & 15]); + if (insn & 0x10) { + // shift by register (for data processing only, not load/store) + if (shift & 1) { + *out++ = '?'; + return out; + } + out += sprintf(out, " %s %s", shifts[stype], reg_name[shift >> 1]); + } else { + // shift by immediate + int shift = insn >> 7 & 31; + int stype = insn >> 5 & 3; + if (shift == 0) { + if (stype == 0) { + // lsl #0 is a no-op + return out; + } else if (stype == 3) { + // ror #0 + return strcpy2(out, " rrx"); + } else { + // lsr #0 and asr #0 act like shift of 32 + shift = 32; + } + } + out += sprintf(out, " %s #%d", shifts[stype], shift); + } + return out; +} + +static char *do_reglist(char *out, int regs) { + int i; + *out++ = '{'; + for (i = 0; i < 16; i++) { + if (regs >> i & 1) { + out = strcpy2(out, reg_name[i]); + if (regs >> i & 2) { + *out++ = '-'; + while (regs >> ++i & 1); + out = strcpy2(out, reg_name[i-1]); + } + *out++ = ','; + } + } + out[-1] = '}'; + *out = '\0'; + return out; +} + +uint32_t disasm_arm_insn(uint32_t pc) { + uint32_t *pc_ptr = phys_mem_ptr(pc, 4); + if(!pc_ptr) + return 0; + + uint32_t insn = *pc_ptr; + char *out = disasmReturnBuf + sprintf(disasmReturnBuf, "%08X: %08X\t", pc, insn); + + int i; + + const struct arm_insn *t = table; + while ((insn & t->mask) != t->value) + t++; + + out = strcpy2(out, t->name); + + switch (t->suffix) { + case XY: + *out++ = (insn & (1 << 5)) ? 't' : 'b'; + /* fallthrough */ + case Y: + *out++ = (insn & (1 << 6)) ? 't' : 'b'; + } + + if (!(t->mask & 0xF0000000)) + out = strcpy2(out, condcode[insn >> 28]); + + switch (t->suffix) { + case S: + if (insn & (1 << 20)) *out++ = 's'; + break; + case B: + if (insn & (1 << 22)) *out++ = 'b'; + break; + case BT: + if (insn & (1 << 22)) *out++ = 'b'; + if (insn & (1 << 21)) *out++ = 't'; + break; + case M: + *out++ = (insn & (1 << 23)) ? 'i' : 'd'; + *out++ = (insn & (1 << 24)) ? 'b' : 'a'; + break; + case H: + if (insn & (1 << 6)) *out++ = 's'; + *out++ = (insn & (1 << 5)) ? 'h' : 'b'; + break; + case D: + *out++ = 'd'; + break; + case L: + if (insn & (1 << 22)) *out++ = 'l'; + break; + } + + for (i = 0; i < 4 && (&t->op1)[i] != none; i++) { + *out++ = i ? ',' : '\t'; + switch ((&t->op1)[i]) { + case REG0: out = strcpy2(out, reg_name[insn & 15]); break; + case REG8: out = strcpy2(out, reg_name[insn >> 8 & 15]); break; + case REG12: out = strcpy2(out, reg_name[insn >> 12 & 15]); break; + case REG16: out = strcpy2(out, reg_name[insn >> 16 & 15]); break; + case SHFOP: + if (!(insn & (1 << 25))) { + out = do_shift(out, insn); + break; + } + /* fallthrough */ + case IMMED: { + uint32_t imm = insn & 255, shift = insn >> 7 & 30; + out += sprintf(out, "%08X", imm >> shift | imm << (32 - shift)); + break; + } + case PSR: + *out++ = (insn & (1 << 22)) ? 's' : 'c'; + *out++ = 'p'; *out++ = 's'; *out++ = 'r'; + if (~insn >> 16 & 15) { + *out++ = '_'; + if (insn & (1 << 19)) *out++ = 'f'; + if (insn & (1 << 18)) *out++ = 's'; + if (insn & (1 << 17)) *out++ = 'x'; + if (insn & (1 << 16)) *out++ = 'c'; + } + break; + case MEM: + *out++ = '['; + out = strcpy2(out, reg_name[insn >> 16 & 15]); + if ((insn & 0x32F0000) == 0x10F0000) { + // immediate, offset mode, PC relative + int addr = insn & 0xFFF; + if (!(insn & (1 << 23))) addr = -addr; + addr += pc + 8; + out -= 2; + out += sprintf(out, "%08X]", addr); + uint32_t *ptr = phys_mem_ptr(addr, 4); + if (ptr) + out += sprintf(out, " = %08X", *ptr); + } else { + if (!(insn & (1 << 24))) // post-index + *out++ = ']'; + *out++ = ' '; + *out++ = (insn & (1 << 23)) ? '+' : '-'; + *out++ = ' '; + if (insn & (1 << 25)) { + // register offset + if (insn & 0x10) { + // register shifted by register not allowed + *out++ = '?'; + } else { + out = do_shift(out, insn); + } + } else { + // immediate offset + if ((insn & 0xFFF) || !(insn & (1 << 23))) + out += sprintf(out, "%03x", insn & 0xFFF); + else + // don't display an added offset of 0 + out -= 3; + } + if (insn & (1 << 24)) { // pre-index + *out++ = ']'; + if (insn & (1 << 21)) // writeback + *out++ = '!'; + } + } + break; + case MEMH: + *out++ = '['; + out = strcpy2(out, reg_name[insn >> 16 & 15]); + if (!(insn & (1 << 24))) // post-index + *out++ = ']'; + *out++ = ' '; + *out++ = (insn & (1 << 23)) ? '+' : '-'; + *out++ = ' '; + if (insn & (1 << 22)) { + // immediate offset + uint32_t imm = (insn & 0x0F) | (insn >> 4 & 0xF0); + if (imm || !(insn & (1 << 23))) + out += sprintf(out, "%03x", imm); + else + // don't display an added offset of 0 + out -= 3; + } else { + // register offset + out = strcpy2(out, reg_name[insn & 15]); + } + if (insn & (1 << 24)) { // pre-index + *out++ = ']'; + if (insn & (1 << 21)) // writeback + *out++ = '!'; + } else { // post-index + // writeback assumed, setting W bit is invalid. + if (insn & (1 << 21)) + *out++ = '?'; + } + break; + case MEM16: + out += sprintf(out, "[%s]", reg_name[insn >> 16 & 15]); + break; + case MULTI: + out = strcpy2(out, reg_name[insn >> 16 & 15]); + if (insn & (1 << 21)) // Writeback + *out++ = '!'; + *out++ = ','; + out = do_reglist(out, insn & 0xFFFF); + if (insn & (1 << 22)) // Load PSR or force user mode + *out++ = '^'; + break; + case BRCH: + out += sprintf(out, "%08X", pc + 8 + ((int)insn << 8 >> 6)); + break; + case BRCHT: + out += sprintf(out, "%08X", pc + 8 + ((int)insn << 8 >> 6 | (insn >> 23 & 2))); + break; + case COPR: + out += sprintf(out, "p%d", insn >> 8 & 15); + break; + case CDP: + out += sprintf(out, "%d,c%d,c%d,c%d,%d", insn >> 20 & 15, + insn >> 12 & 15, insn >> 16 & 15, insn & 15, insn >> 5 & 7); + break; + case MRC: + out += sprintf(out, "%d,%s,c%d,c%d,%d", insn >> 21 & 7, + reg_name[insn >> 12 & 15], insn >> 16 & 15, insn & 15, insn >> 5 & 7); + break; + case MRRC: + out += sprintf(out, "%d,%s,%s,c%d", insn >> 4 & 15, + reg_name[insn >> 12 & 15], reg_name[insn >> 16 & 15], insn & 15); + break; + case MEMC: + out += sprintf(out, "c%d,[%s", insn >> 12 & 15, + reg_name[insn >> 16 & 15]); + if (!(insn & (1 << 24))) { // Post-indexed or unindexed + *out++ = ']'; + if (!(insn & (1 << 21))) { + // Unindexed addressing + if (!(insn & (1 << 23))) + *out++ = '?'; + out += sprintf(out, ",{%02X}", insn & 0xFF); + break; + } + } + if (!(insn & (1 << 23)) || insn & 0xFF) + out += sprintf(out, " %c %03x", + (insn & (1 << 23)) ? '+' : '-', + (insn & 0xFF) << 2); + if (insn & (1 << 24)) { // Pre-indexed or offset + *out++ = ']'; + if (insn & (1 << 21)) // Writeback (pre-indexed) + *out++ = '!'; + } + break; + case BKPT: + out += sprintf(out, "%04X", (insn >> 4 & 0xFFF0) | (insn & 0x0F)); + break; + case SWI: + out += sprintf(out, "%06x", insn & 0xFFFFFF); + break; + } + } + *out = '\0'; + return 4; +} + +uint32_t disasm_thumb_insn(uint32_t pc) { + uint16_t *pc_ptr = phys_mem_ptr(pc, 2); + if (!pc_ptr) + return 0; + + uint16_t insn = *pc_ptr; + char *out = disasmReturnBuf + sprintf(disasmReturnBuf, "%08X: %04X \t", pc, insn); + + if (insn < 0x1800) { + static const char name[][4] = { "lsl", "lsr", "asr" }; + sprintf(out, "%s\tr%d,r%d,%02X", name[insn >> 11], + insn & 7, insn >> 3 & 7, insn >> 6 & 31); + } else if (insn < 0x2000) { + sprintf(out, "%s\tr%d,r%d,%s%d", + (insn & 0x0200) ? "sub" : "add", + insn & 7, insn >> 3 & 7, + (insn & 0x400) ? "" : "r", insn >> 6 & 7); + } else if (insn < 0x4000) { + static const char name[][4] = { "mov", "cmp", "add", "sub" }; + sprintf(out, "%s\tr%d,%02X", name[insn >> 11 & 3], + insn >> 8 & 7, insn & 0xFF); + } else if (insn < 0x4400) { + static const char name[][4] = { + "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", + "tst", "neg", "cmp", "cmn", "orr", "mul", "bic", "mvn" + }; + sprintf(out, "%s\tr%d,r%d", name[insn >> 6 & 15], insn & 7, insn >> 3 & 7); + } else if (insn < 0x4700) { + static const char name[][4] = { "add", "cmp", "mov" }; + int rd = (insn & 7) | (insn >> 4 & 8); + int rn = insn >> 3 & 15; + if (!((rd | rn) & 8)) + goto invalid; + sprintf(out, "%s\t%s,%s", name[insn >> 8 & 3], reg_name[rd], reg_name[rn]); + } else if (insn < 0x4800) { + if (insn & 7) + goto invalid; + sprintf(out, "%s\t%s", (insn & 0x80) ? "blx" : "bx", reg_name[insn >> 3 & 15]); + } else if (insn < 0x5000) { + int addr = ((pc + 4) & -4) + ((insn & 0xFF) << 2); + out += sprintf(out, "ldr\tr%d,[%08X]", insn >> 8 & 7, addr); + uint32_t *ptr = phys_mem_ptr(addr, 4); + if (ptr) + sprintf(out, " = %08X", *ptr); + } else if (insn < 0x6000) { + static const char name[][6] = { + "str", "strh", "strb", "ldrsb", + "ldr", "ldrh", "ldrb", "ldrsh" + }; + sprintf(out, "%s\tr%d,[r%d + r%d]", name[insn >> 9 & 7], + insn & 7, insn >> 3 & 7, insn >> 6 & 7); + } else if (insn < 0x9000) { + static const char name[][5] = { "str", "ldr", "strb", "ldrb", "strh", "ldrh" }; + int type = (insn - 0x6000) >> 11; + sprintf(out, "%s\tr%d,[r%d + %03x]", name[type], + insn & 7, insn >> 3 & 7, + (insn >> 6 & 31) << (0x12 >> (type & 6) & 3)); + } else if (insn < 0xA000) { + sprintf(out, "%s\tr%d,[sp + %03x]", + (insn & 0x800) ? "ldr" : "str", + insn >> 8 & 7, (insn & 0xFF) << 2); + } else if (insn < 0xB000) { + sprintf(out, "add\tr%d,%s,%03x", + insn >> 8 & 7, + (insn & 0x800) ? "sp" : "pc", (insn & 0xFF) << 2); + } else if (insn < 0xB100) { + sprintf(out, "%s\tsp,%03x", + (insn & 0x80) ? "sub" : "add", (insn & 0x7F) << 2); + } else if (insn < 0xB400) { + goto invalid; + } else if (insn < 0xB600) { + out = strcpy2(out, "push\t"); + do_reglist(out, (insn & 0xFF) | (insn & 0x100) << (14 - 8)); + } else if (insn < 0xBC00) { + goto invalid; + } else if (insn < 0xBE00) { + out = strcpy2(out, "pop\t"); + do_reglist(out, (insn & 0xFF) | (insn & 0x100) << (15 - 8)); + } else if (insn < 0xBF00) { + sprintf(out, "bkpt\t%02X", insn & 0xFF); + } else if (insn < 0xC000) { + goto invalid; + } else if (insn < 0xD000) { + out += sprintf(out, "%smia\tr%d!,", (insn & 0x800) ? "ld" : "st", insn >> 8 & 7); + do_reglist(out, insn & 0xFF); + } else if (insn < 0xDE00) { + sprintf(out, "b%s\t%08X", condcode[insn >> 8 & 15], pc + 4 + ((int8_t)insn << 1)); + } else if (insn < 0xDF00) { +invalid: + sprintf(out, "???"); + } else if (insn < 0xE000) { + sprintf(out, "swi\t%02X", insn & 0xFF); + } else if (insn < 0xE800) { + sprintf(out, "b\t%08X", pc + 4 + ((int32_t)insn << 21 >> 20)); + } else if (insn < 0xF000) { + sprintf(out, "(blx\tlr + %03x)", (insn & 0x7FF) << 1); + } else if (insn < 0xF800) { + int32_t target = (int32_t)insn << 21 >> 9; + /* Check next instruction to see if this is part of a BL or BLX pair */ + pc_ptr = phys_mem_ptr(pc + 2, 2); + if (pc_ptr && ((insn = *pc_ptr) & 0xE800) == 0xE800) { + /* It is; show both instructions combined as one */ + target += pc + 4 + ((insn & 0x7FF) << 1); + if (!(insn & 0x1000)) target &= ~3; + sprintf(out - 5, "%04X\t%s\t%08X", insn, + (insn & 0x1000) ? "bl" : "blx", target); + gui_debug_printf("%s\n", disasmReturnBuf); + return 4; + } + sprintf(out, "(add\tlr,pc,%08X)", target); + } else { + sprintf(out, "(bl\tlr + %03x)", (insn & 0x7FF) << 1); + } + return 2; +} diff --git a/src/armv5te/disasm.h b/src/armv5te/disasm.h new file mode 100644 index 0000000..0cdade5 --- /dev/null +++ b/src/armv5te/disasm.h @@ -0,0 +1,19 @@ +#ifndef H_DISASM +#define H_DISASM + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern char disasmReturnBuf[80]; + +uint32_t disasm_arm_insn(uint32_t pc); +uint32_t disasm_thumb_insn(uint32_t pc); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/armv5te/emu.h b/src/armv5te/emu.h index d4c056b..0d7fb1c 100644 --- a/src/armv5te/emu.h +++ b/src/armv5te/emu.h @@ -1,5 +1,5 @@ -#ifndef _H_EMU -#define _H_EMU +#ifndef H_EMU +#define H_EMU #include #include diff --git a/src/armv5te/mem.c b/src/armv5te/mem.c index 1d06aa5..2566701 100644 --- a/src/armv5te/mem.c +++ b/src/armv5te/mem.c @@ -16,12 +16,12 @@ void (*write_half_map[64])(uint32_t addr, uint16_t value); void (*write_word_map[64])(uint32_t addr, uint32_t value); /* For invalid/unknown physical addresses */ -uint8_t bad_read_byte(uint32_t addr) { warn("Bad read_byte: %08x", addr); return 0; } -uint16_t bad_read_half(uint32_t addr) { warn("Bad read_half: %08x", addr); return 0; } -uint32_t bad_read_word(uint32_t addr) { warn("Bad read_word: %08x", addr); return 0; } -void bad_write_byte(uint32_t addr, uint8_t value) { warn("Bad write_byte: %08x %02x", addr, value); } -void bad_write_half(uint32_t addr, uint16_t value) { warn("Bad write_half: %08x %04x", addr, value); } -void bad_write_word(uint32_t addr, uint32_t value) { warn("Bad write_word: %08x %08x", addr, value); } +uint8_t bad_read_byte(uint32_t addr) { warn("Bad read_byte: %08X", addr); return 0; } +uint16_t bad_read_half(uint32_t addr) { warn("Bad read_half: %08X", addr); return 0; } +uint32_t bad_read_word(uint32_t addr) { warn("Bad read_word: %08X", addr); return 0; } +void bad_write_byte(uint32_t addr, uint8_t value) { warn("Bad write_byte: %08X %02X", addr, value); } +void bad_write_half(uint32_t addr, uint16_t value) { warn("Bad write_half: %08X %04X", addr, value); } +void bad_write_word(uint32_t addr, uint32_t value) { warn("Bad write_word: %08X %08X", addr, value); } uint8_t *mem_and_flags = NULL; struct mem_area_desc mem_areas[2]; @@ -51,7 +51,7 @@ void read_action(void *ptr) { /* uint32_t addr = phys_mem_addr(ptr); if (!gdb_connected) - emuprintf("Hit read breakpoint at %08x. Entering debugger.\n", addr); + emuprintf("Hit read breakpoint at %08X. Entering debugger.\n", addr); debugger(DBG_READ_BREAKPOINT, addr); */ } @@ -64,13 +64,13 @@ void write_action(void *ptr) { // this is just debugging stuff if (*flags & RF_WRITE_BREAKPOINT) { if (!gdb_connected) - emuprintf("Hit write breakpoint at %08x. Entering debugger.\n", addr); + emuprintf("Hit write breakpoint at %08X. Entering debugger.\n", addr); debugger(DBG_WRITE_BREAKPOINT, addr); } */ #ifndef NO_TRANSLATION if (*flags & RF_CODE_TRANSLATED) { - logprintf(LOG_CPU, "Wrote to translated code at %08x. Deleting translations.\n", addr); + logprintf(LOG_CPU, "Wrote to translated code at %08X. Deleting translations.\n", addr); invalidate_translation(*flags >> RFS_TRANSLATION_INDEX); } else { *flags &= ~RF_CODE_NO_TRANSLATE; diff --git a/src/armv5te/mem.h b/src/armv5te/mem.h index b5b9005..6db69c9 100644 --- a/src/armv5te/mem.h +++ b/src/armv5te/mem.h @@ -1,7 +1,7 @@ /* Declarations for memory.c */ -#ifndef _H_MEM -#define _H_MEM +#ifndef H_MEM +#define H_MEM #include diff --git a/src/armv5te/mmu.c b/src/armv5te/mmu.c index 830b7f8..782a36c 100644 --- a/src/armv5te/mmu.c +++ b/src/armv5te/mmu.c @@ -68,7 +68,7 @@ void mmu_dump_tables(void) { page_type = "1kB"; } section:; - gui_debug_printf("%08x -> %08x (%s) (0x%8x)\n", virt_addr + j * (1 << virt_shift), l1_entry & -page_size, page_type, l1_entry); + gui_debug_printf("%08X -> %08X (%s) (0x%8x)\n", virt_addr + j * (1 << virt_shift), l1_entry & -page_size, page_type, l1_entry); } } } @@ -246,10 +246,10 @@ void *addr_cache_miss(uint32_t virt, bool writing, fault_proc *fault) { uint8_t *ptr = phys_mem_ptr(phys, 1); if (ptr && !(writing && (RAM_FLAGS((size_t)ptr & ~3) & RF_READ_ONLY))) { AC_SET_ENTRY_PTR(entry, virt, ptr) - //printf("addr_cache_miss VA=%08x ptr=%p entry=%p\n", virt, ptr, entry); + //printf("addr_cache_miss VA=%08X ptr=%p entry=%p\n", virt, ptr, entry); } else { AC_SET_ENTRY_PHYS(entry, virt, phys) - //printf("addr_cache_miss VA=%08x PA=%08x entry=%p\n", virt, phys, entry); + //printf("addr_cache_miss VA=%08X PA=%08X entry=%p\n", virt, phys, entry); } uint32_t oldoffset = ac_valid_list[ac_valid_index]; uint32_t offset = (virt >> 10) * 2 + writing; diff --git a/src/armv5te/mmu.h b/src/armv5te/mmu.h index 3680a96..15714f7 100644 --- a/src/armv5te/mmu.h +++ b/src/armv5te/mmu.h @@ -1,5 +1,5 @@ -#ifndef _H_MMU -#define _H_MMU +#ifndef H_MMU +#define H_MMU #include "cpu.h" #include "emu.h" diff --git a/src/armv5te/thumb_interpreter.cpp b/src/armv5te/thumb_interpreter.cpp index 8061aac..b9ec306 100644 --- a/src/armv5te/thumb_interpreter.cpp +++ b/src/armv5te/thumb_interpreter.cpp @@ -92,7 +92,7 @@ void cpu_thumb_loop() { if (flags & (RF_EXEC_BREAKPOINT | RF_EXEC_DEBUG_NEXT)) { if (flags & RF_EXEC_BREAKPOINT) - gui_debug_printf("Breakpoint at 0x%08x\n", arm.reg[15]); + gui_debug_printf("Breakpoint at 0x%08X\n", arm.reg[15]); enter_debugger: uint32_t pc = arm.reg[15]; debugger(DBG_EXEC_BREAKPOINT, 0); @@ -233,7 +233,7 @@ void cpu_thumb_loop() { break; } case 0xBE: - printf("Software breakpoint at %08x (%02x)\n", arm.reg[15], insn & 0xFF); + printf("Software breakpoint at %08X (%02X)\n", arm.reg[15], insn & 0xFF); debugger(DBG_EXEC_BREAKPOINT, 0); break; diff --git a/src/armv5te/translate.h b/src/armv5te/translate.h index 2536d1c..c16130a 100644 --- a/src/armv5te/translate.h +++ b/src/armv5te/translate.h @@ -1,7 +1,7 @@ /* Declarations for translate.c */ -#ifndef _H_TRANSLATE -#define _H_TRANSLATE +#ifndef H_TRANSLATE +#define H_TRANSLATE #include #include diff --git a/src/armv5te/translate_x86.c b/src/armv5te/translate_x86.c index 733bdb1..a242fc6 100644 --- a/src/armv5te/translate_x86.c +++ b/src/armv5te/translate_x86.c @@ -1026,7 +1026,7 @@ void translate_range(uint32_t range_start, uint32_t range_end, int dump) { for (index = 0; index < next_index; index++) { int start = translation_table[index].start_addr; int end = translation_table[index].end_addr; - fprintf(f, "%08x (%08x,%08x) %d\n", + fprintf(f, "%08X (%08X,%08X) %d\n", (uint8_t *)translation_table[index].code - insn_buffer, start, end, end - start); } diff --git a/src/flx68000.c b/src/flx68000.c index 0f41aac..33c72a7 100755 --- a/src/flx68000.c +++ b/src/flx68000.c @@ -84,9 +84,7 @@ void flx68000Reset(void){ if(!inited){ m68k_init(); - m68k_set_cpu_type(M68K_CPU_TYPE_68000); - - CPU_ADDRESS_MASK = 0xFFFFFFFF; + m68k_set_cpu_type(M68K_CPU_TYPE_DBVZ); inited = true; } diff --git a/src/m68k/m68k.h b/src/m68k/m68k.h index 0c7c777..9a9bb50 100755 --- a/src/m68k/m68k.h +++ b/src/m68k/m68k.h @@ -86,7 +86,8 @@ enum M68K_CPU_TYPE_68EC020, M68K_CPU_TYPE_68020, M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ - M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ + M68K_CPU_TYPE_68040, /* Supported by disassembler ONLY */ + M68K_CPU_TYPE_DBVZ }; /* Registers used by m68k_get_reg() and m68k_set_reg() */ @@ -338,7 +339,7 @@ void m68k_set_reg(m68k_register_t reg, uint32_t value); /* Check if an instruction is valid for the specified CPU type */ uint32_t m68k_is_valid_instruction(uint32_t instruction, uint32_t cpu_type); -/* Disassemble 1 instruction using the epecified CPU type at pc. Stores +/* Disassemble 1 instruction using the specified CPU type at pc. Stores * disassembly in str_buff and returns the size of the instruction in bytes. */ uint32_t m68k_disassemble(char* str_buff, uint32_t pc, uint32_t cpu_type); diff --git a/src/m68k/m68kconf.h b/src/m68k/m68kconf.h index 0bce4d3..364c21e 100755 --- a/src/m68k/m68kconf.h +++ b/src/m68k/m68kconf.h @@ -183,16 +183,6 @@ */ -/* Set to your compiler's static inline keyword to enable it, or - * set it to blank to disable it. - * If you define MUSASHI_INLINE in the makefile, it will override this value. - * NOTE: not enabling inline functions will SEVERELY slow down emulation. - */ -#ifndef MUSASHI_INLINE -#define MUSASHI_INLINE static inline -#endif /* MUSASHI_INLINE */ - - /* ======================================================================== */ /* ============================== END OF FILE ============================= */ /* ======================================================================== */ diff --git a/src/m68k/m68kcpu.c b/src/m68k/m68kcpu.c index 6b4adfb..8c2f3d7 100755 --- a/src/m68k/m68kcpu.c +++ b/src/m68k/m68kcpu.c @@ -471,7 +471,7 @@ uint32_t m68k_get_reg(void* context, m68k_register_t regnum) case M68K_REG_CPU_TYPE: switch(cpu->cpu_type) { - case CPU_TYPE_000: return (uint32_t)M68K_CPU_TYPE_68000; + case CPU_TYPE_000: return CPU_ADDRESS_MASK == 0xffffffff ? (uint32_t)M68K_CPU_TYPE_DBVZ : (uint32_t)M68K_CPU_TYPE_68000; case CPU_TYPE_010: return (uint32_t)M68K_CPU_TYPE_68010; case CPU_TYPE_EC020: return (uint32_t)M68K_CPU_TYPE_68EC020; case CPU_TYPE_020: return (uint32_t)M68K_CPU_TYPE_68020; @@ -632,6 +632,22 @@ void m68k_set_cpu_type(uint32_t cpu_type) CYC_SHIFT = 0; CYC_RESET = 518; return; + case M68K_CPU_TYPE_DBVZ: + CPU_TYPE = CPU_TYPE_000; + CPU_ADDRESS_MASK = 0xffffffff; + CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[0]; + CYC_EXCEPTION = m68ki_exception_cycle_table[0]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 2; + CYC_DBCC_F_NOEXP = -2; + CYC_DBCC_F_EXP = 2; + CYC_SCC_R_TRUE = 2; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 3; + CYC_SHIFT = 1; + CYC_RESET = 132; + return; } } diff --git a/src/m68k/m68kcpu.h b/src/m68k/m68kcpu.h index cb6cb62..8c0d80e 100755 --- a/src/m68k/m68kcpu.h +++ b/src/m68k/m68kcpu.h @@ -836,120 +836,120 @@ extern uint m68ki_aerr_write_mode; extern uint m68ki_aerr_fc; /* Read data immediately after the program counter */ -MUSASHI_INLINE uint m68ki_read_imm_16(void); -MUSASHI_INLINE uint m68ki_read_imm_32(void); +static inline uint m68ki_read_imm_16(void); +static inline uint m68ki_read_imm_32(void); /* Read data with specific function code */ -MUSASHI_INLINE uint m68ki_read_8_fc (uint address, uint fc); -MUSASHI_INLINE uint m68ki_read_16_fc (uint address, uint fc); -MUSASHI_INLINE uint m68ki_read_32_fc (uint address, uint fc); +static inline uint m68ki_read_8_fc (uint address, uint fc); +static inline uint m68ki_read_16_fc (uint address, uint fc); +static inline uint m68ki_read_32_fc (uint address, uint fc); /* Write data with specific function code */ -MUSASHI_INLINE void m68ki_write_8_fc (uint address, uint fc, uint value); -MUSASHI_INLINE void m68ki_write_16_fc(uint address, uint fc, uint value); -MUSASHI_INLINE void m68ki_write_32_fc(uint address, uint fc, uint value); +static inline void m68ki_write_8_fc (uint address, uint fc, uint value); +static inline void m68ki_write_16_fc(uint address, uint fc, uint value); +static inline void m68ki_write_32_fc(uint address, uint fc, uint value); #if M68K_SIMULATE_PD_WRITES -MUSASHI_INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value); +static inline void m68ki_write_32_pd_fc(uint address, uint fc, uint value); #endif /* M68K_SIMULATE_PD_WRITES */ /* Indexed and PC-relative ea fetching */ -MUSASHI_INLINE uint m68ki_get_ea_pcdi(void); -MUSASHI_INLINE uint m68ki_get_ea_pcix(void); -MUSASHI_INLINE uint m68ki_get_ea_ix(uint An); +static inline uint m68ki_get_ea_pcdi(void); +static inline uint m68ki_get_ea_pcix(void); +static inline uint m68ki_get_ea_ix(uint An); /* Operand fetching */ -MUSASHI_INLINE uint OPER_AY_AI_8(void); -MUSASHI_INLINE uint OPER_AY_AI_16(void); -MUSASHI_INLINE uint OPER_AY_AI_32(void); -MUSASHI_INLINE uint OPER_AY_PI_8(void); -MUSASHI_INLINE uint OPER_AY_PI_16(void); -MUSASHI_INLINE uint OPER_AY_PI_32(void); -MUSASHI_INLINE uint OPER_AY_PD_8(void); -MUSASHI_INLINE uint OPER_AY_PD_16(void); -MUSASHI_INLINE uint OPER_AY_PD_32(void); -MUSASHI_INLINE uint OPER_AY_DI_8(void); -MUSASHI_INLINE uint OPER_AY_DI_16(void); -MUSASHI_INLINE uint OPER_AY_DI_32(void); -MUSASHI_INLINE uint OPER_AY_IX_8(void); -MUSASHI_INLINE uint OPER_AY_IX_16(void); -MUSASHI_INLINE uint OPER_AY_IX_32(void); +static inline uint OPER_AY_AI_8(void); +static inline uint OPER_AY_AI_16(void); +static inline uint OPER_AY_AI_32(void); +static inline uint OPER_AY_PI_8(void); +static inline uint OPER_AY_PI_16(void); +static inline uint OPER_AY_PI_32(void); +static inline uint OPER_AY_PD_8(void); +static inline uint OPER_AY_PD_16(void); +static inline uint OPER_AY_PD_32(void); +static inline uint OPER_AY_DI_8(void); +static inline uint OPER_AY_DI_16(void); +static inline uint OPER_AY_DI_32(void); +static inline uint OPER_AY_IX_8(void); +static inline uint OPER_AY_IX_16(void); +static inline uint OPER_AY_IX_32(void); -MUSASHI_INLINE uint OPER_AX_AI_8(void); -MUSASHI_INLINE uint OPER_AX_AI_16(void); -MUSASHI_INLINE uint OPER_AX_AI_32(void); -MUSASHI_INLINE uint OPER_AX_PI_8(void); -MUSASHI_INLINE uint OPER_AX_PI_16(void); -MUSASHI_INLINE uint OPER_AX_PI_32(void); -MUSASHI_INLINE uint OPER_AX_PD_8(void); -MUSASHI_INLINE uint OPER_AX_PD_16(void); -MUSASHI_INLINE uint OPER_AX_PD_32(void); -MUSASHI_INLINE uint OPER_AX_DI_8(void); -MUSASHI_INLINE uint OPER_AX_DI_16(void); -MUSASHI_INLINE uint OPER_AX_DI_32(void); -MUSASHI_INLINE uint OPER_AX_IX_8(void); -MUSASHI_INLINE uint OPER_AX_IX_16(void); -MUSASHI_INLINE uint OPER_AX_IX_32(void); +static inline uint OPER_AX_AI_8(void); +static inline uint OPER_AX_AI_16(void); +static inline uint OPER_AX_AI_32(void); +static inline uint OPER_AX_PI_8(void); +static inline uint OPER_AX_PI_16(void); +static inline uint OPER_AX_PI_32(void); +static inline uint OPER_AX_PD_8(void); +static inline uint OPER_AX_PD_16(void); +static inline uint OPER_AX_PD_32(void); +static inline uint OPER_AX_DI_8(void); +static inline uint OPER_AX_DI_16(void); +static inline uint OPER_AX_DI_32(void); +static inline uint OPER_AX_IX_8(void); +static inline uint OPER_AX_IX_16(void); +static inline uint OPER_AX_IX_32(void); -MUSASHI_INLINE uint OPER_A7_PI_8(void); -MUSASHI_INLINE uint OPER_A7_PD_8(void); +static inline uint OPER_A7_PI_8(void); +static inline uint OPER_A7_PD_8(void); -MUSASHI_INLINE uint OPER_AW_8(void); -MUSASHI_INLINE uint OPER_AW_16(void); -MUSASHI_INLINE uint OPER_AW_32(void); -MUSASHI_INLINE uint OPER_AL_8(void); -MUSASHI_INLINE uint OPER_AL_16(void); -MUSASHI_INLINE uint OPER_AL_32(void); -MUSASHI_INLINE uint OPER_PCDI_8(void); -MUSASHI_INLINE uint OPER_PCDI_16(void); -MUSASHI_INLINE uint OPER_PCDI_32(void); -MUSASHI_INLINE uint OPER_PCIX_8(void); -MUSASHI_INLINE uint OPER_PCIX_16(void); -MUSASHI_INLINE uint OPER_PCIX_32(void); +static inline uint OPER_AW_8(void); +static inline uint OPER_AW_16(void); +static inline uint OPER_AW_32(void); +static inline uint OPER_AL_8(void); +static inline uint OPER_AL_16(void); +static inline uint OPER_AL_32(void); +static inline uint OPER_PCDI_8(void); +static inline uint OPER_PCDI_16(void); +static inline uint OPER_PCDI_32(void); +static inline uint OPER_PCIX_8(void); +static inline uint OPER_PCIX_16(void); +static inline uint OPER_PCIX_32(void); /* Stack operations */ -MUSASHI_INLINE void m68ki_push_16(uint value); -MUSASHI_INLINE void m68ki_push_32(uint value); -MUSASHI_INLINE uint m68ki_pull_16(void); -MUSASHI_INLINE uint m68ki_pull_32(void); +static inline void m68ki_push_16(uint value); +static inline void m68ki_push_32(uint value); +static inline uint m68ki_pull_16(void); +static inline uint m68ki_pull_32(void); /* Program flow operations */ -MUSASHI_INLINE void m68ki_jump(uint new_pc); -MUSASHI_INLINE void m68ki_jump_vector(uint vector); -MUSASHI_INLINE void m68ki_branch_8(uint offset); -MUSASHI_INLINE void m68ki_branch_16(uint offset); -MUSASHI_INLINE void m68ki_branch_32(uint offset); +static inline void m68ki_jump(uint new_pc); +static inline void m68ki_jump_vector(uint vector); +static inline void m68ki_branch_8(uint offset); +static inline void m68ki_branch_16(uint offset); +static inline void m68ki_branch_32(uint offset); /* Status register operations. */ -MUSASHI_INLINE void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ -MUSASHI_INLINE void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */ -MUSASHI_INLINE void m68ki_set_ccr(uint value); /* set the condition code register */ -MUSASHI_INLINE void m68ki_set_sr(uint value); /* set the status register */ -MUSASHI_INLINE void m68ki_set_sr_noint(uint value); /* set the status register */ +static inline void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ +static inline void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */ +static inline void m68ki_set_ccr(uint value); /* set the condition code register */ +static inline void m68ki_set_sr(uint value); /* set the status register */ +static inline void m68ki_set_sr_noint(uint value); /* set the status register */ /* Exception processing */ -MUSASHI_INLINE uint m68ki_init_exception(void); /* Initial exception processing */ +static inline uint m68ki_init_exception(void); /* Initial exception processing */ -MUSASHI_INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */ -MUSASHI_INLINE void m68ki_stack_frame_buserr(uint sr); +static inline void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */ +static inline void m68ki_stack_frame_buserr(uint sr); -MUSASHI_INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector); -MUSASHI_INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector); -MUSASHI_INLINE void m68ki_stack_frame_0010(uint sr, uint vector); -MUSASHI_INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector); -MUSASHI_INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc); -MUSASHI_INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc); +static inline void m68ki_stack_frame_0000(uint pc, uint sr, uint vector); +static inline void m68ki_stack_frame_0001(uint pc, uint sr, uint vector); +static inline void m68ki_stack_frame_0010(uint sr, uint vector); +static inline void m68ki_stack_frame_1000(uint pc, uint sr, uint vector); +static inline void m68ki_stack_frame_1010(uint sr, uint vector, uint pc); +static inline void m68ki_stack_frame_1011(uint sr, uint vector, uint pc); -MUSASHI_INLINE void m68ki_exception_trap(uint vector); -MUSASHI_INLINE void m68ki_exception_trapN(uint vector); -MUSASHI_INLINE void m68ki_exception_trace(void); -MUSASHI_INLINE void m68ki_exception_privilege_violation(void); -MUSASHI_INLINE void m68ki_exception_1010(void); -MUSASHI_INLINE void m68ki_exception_1111(void); -MUSASHI_INLINE void m68ki_exception_illegal(void); -MUSASHI_INLINE void m68ki_exception_format_error(void); -MUSASHI_INLINE void m68ki_exception_address_error(void); -MUSASHI_INLINE void m68ki_exception_interrupt(uint int_level); -MUSASHI_INLINE void m68ki_check_interrupts(void); /* ASG: check for interrupts */ +static inline void m68ki_exception_trap(uint vector); +static inline void m68ki_exception_trapN(uint vector); +static inline void m68ki_exception_trace(void); +static inline void m68ki_exception_privilege_violation(void); +static inline void m68ki_exception_1010(void); +static inline void m68ki_exception_1111(void); +static inline void m68ki_exception_illegal(void); +static inline void m68ki_exception_format_error(void); +static inline void m68ki_exception_address_error(void); +static inline void m68ki_exception_interrupt(uint int_level); +static inline void m68ki_check_interrupts(void); /* ASG: check for interrupts */ /* quick disassembly (used for logging) */ char* m68ki_disassemble_quick(uint32_t pc, uint32_t cpu_type); @@ -965,7 +965,7 @@ char* m68ki_disassemble_quick(uint32_t pc, uint32_t cpu_type); /* Handles all immediate reads, does address error check, function code setting, * and prefetching if they are enabled in m68kconf.h */ -MUSASHI_INLINE uint m68ki_read_imm_16(void) +static inline uint m68ki_read_imm_16(void) { m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ @@ -982,7 +982,7 @@ MUSASHI_INLINE uint m68ki_read_imm_16(void) return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2)); #endif /* M68K_EMULATE_PREFETCH */ } -MUSASHI_INLINE uint m68ki_read_imm_32(void) +static inline uint m68ki_read_imm_32(void) { #if M68K_EMULATE_PREFETCH uint temp_val; @@ -1023,36 +1023,36 @@ MUSASHI_INLINE uint m68ki_read_imm_32(void) * These functions will also check for address error and set the function * code if they are enabled in m68kconf.h. */ -MUSASHI_INLINE uint m68ki_read_8_fc(uint address, uint fc) +static inline uint m68ki_read_8_fc(uint address, uint fc) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ return m68k_read_memory_8(ADDRESS_68K(address)); } -MUSASHI_INLINE uint m68ki_read_16_fc(uint address, uint fc) +static inline uint m68ki_read_16_fc(uint address, uint fc) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ return m68k_read_memory_16(ADDRESS_68K(address)); } -MUSASHI_INLINE uint m68ki_read_32_fc(uint address, uint fc) +static inline uint m68ki_read_32_fc(uint address, uint fc) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ return m68k_read_memory_32(ADDRESS_68K(address)); } -MUSASHI_INLINE void m68ki_write_8_fc(uint address, uint fc, uint value) +static inline void m68ki_write_8_fc(uint address, uint fc, uint value) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68k_write_memory_8(ADDRESS_68K(address), value); } -MUSASHI_INLINE void m68ki_write_16_fc(uint address, uint fc, uint value) +static inline void m68ki_write_16_fc(uint address, uint fc, uint value) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ m68k_write_memory_16(ADDRESS_68K(address), value); } -MUSASHI_INLINE void m68ki_write_32_fc(uint address, uint fc, uint value) +static inline void m68ki_write_32_fc(uint address, uint fc, uint value) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ @@ -1060,7 +1060,7 @@ MUSASHI_INLINE void m68ki_write_32_fc(uint address, uint fc, uint value) } #if M68K_SIMULATE_PD_WRITES -MUSASHI_INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value) +static inline void m68ki_write_32_pd_fc(uint address, uint fc, uint value) { m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ @@ -1074,7 +1074,7 @@ MUSASHI_INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value) /* The program counter relative addressing modes cause operands to be * retrieved from program space, not data space. */ -MUSASHI_INLINE uint m68ki_get_ea_pcdi(void) +static inline uint m68ki_get_ea_pcdi(void) { uint old_pc = REG_PC; m68ki_use_program_space(); /* auto-disable */ @@ -1082,7 +1082,7 @@ MUSASHI_INLINE uint m68ki_get_ea_pcdi(void) } -MUSASHI_INLINE uint m68ki_get_ea_pcix(void) +static inline uint m68ki_get_ea_pcix(void) { m68ki_use_program_space(); /* auto-disable */ return m68ki_get_ea_ix(REG_PC); @@ -1130,7 +1130,7 @@ MUSASHI_INLINE uint m68ki_get_ea_pcix(void) * 1 011 mem indir with long outer * 1 100-111 reserved */ -MUSASHI_INLINE uint m68ki_get_ea_ix(uint An) +static inline uint m68ki_get_ea_ix(uint An) { /* An = base register */ uint extension = m68ki_read_imm_16(); @@ -1203,78 +1203,78 @@ MUSASHI_INLINE uint m68ki_get_ea_ix(uint An) /* Fetch operands */ -MUSASHI_INLINE uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } +static inline uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} +static inline uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} +static inline uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } +static inline uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} +static inline uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } +static inline uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } +static inline uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } -MUSASHI_INLINE uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} -MUSASHI_INLINE uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} -MUSASHI_INLINE uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } -MUSASHI_INLINE uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} -MUSASHI_INLINE uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} -MUSASHI_INLINE uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } -MUSASHI_INLINE uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} -MUSASHI_INLINE uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} +static inline uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } +static inline uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} +static inline uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} +static inline uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } +static inline uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} +static inline uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} +static inline uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } +static inline uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} +static inline uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} +static inline uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } +static inline uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} +static inline uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} /* ---------------------------- Stack Functions --------------------------- */ /* Push/pull data from the stack */ -MUSASHI_INLINE void m68ki_push_16(uint value) +static inline void m68ki_push_16(uint value) { REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); m68ki_write_16(REG_SP, value); } -MUSASHI_INLINE void m68ki_push_32(uint value) +static inline void m68ki_push_32(uint value) { REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); m68ki_write_32(REG_SP, value); } -MUSASHI_INLINE uint m68ki_pull_16(void) +static inline uint m68ki_pull_16(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); return m68ki_read_16(REG_SP-2); } -MUSASHI_INLINE uint m68ki_pull_32(void) +static inline uint m68ki_pull_32(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); return m68ki_read_32(REG_SP-4); @@ -1284,22 +1284,22 @@ MUSASHI_INLINE uint m68ki_pull_32(void) /* Increment/decrement the stack as if doing a push/pull but * don't do any memory access. */ -MUSASHI_INLINE void m68ki_fake_push_16(void) +static inline void m68ki_fake_push_16(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); } -MUSASHI_INLINE void m68ki_fake_push_32(void) +static inline void m68ki_fake_push_32(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); } -MUSASHI_INLINE void m68ki_fake_pull_16(void) +static inline void m68ki_fake_pull_16(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); } -MUSASHI_INLINE void m68ki_fake_pull_32(void) +static inline void m68ki_fake_pull_32(void) { REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); } @@ -1311,13 +1311,13 @@ MUSASHI_INLINE void m68ki_fake_pull_32(void) * These functions will also call the pc_changed callback if it was enabled * in m68kconf.h. */ -MUSASHI_INLINE void m68ki_jump(uint new_pc) +static inline void m68ki_jump(uint new_pc) { REG_PC = new_pc; m68ki_pc_changed(REG_PC); } -MUSASHI_INLINE void m68ki_jump_vector(uint vector) +static inline void m68ki_jump_vector(uint vector) { REG_PC = (vector<<2) + REG_VBR; REG_PC = m68ki_read_data_32(REG_PC); @@ -1330,17 +1330,17 @@ MUSASHI_INLINE void m68ki_jump_vector(uint vector) * So far I've found no problems with not calling pc_changed for 8 or 16 * bit branches. */ -MUSASHI_INLINE void m68ki_branch_8(uint offset) +static inline void m68ki_branch_8(uint offset) { REG_PC += MAKE_INT_8(offset); } -MUSASHI_INLINE void m68ki_branch_16(uint offset) +static inline void m68ki_branch_16(uint offset) { REG_PC += MAKE_INT_16(offset); } -MUSASHI_INLINE void m68ki_branch_32(uint offset) +static inline void m68ki_branch_32(uint offset) { REG_PC += offset; m68ki_pc_changed(REG_PC); @@ -1353,7 +1353,7 @@ MUSASHI_INLINE void m68ki_branch_32(uint offset) /* Set the S flag and change the active stack pointer. * Note that value MUST be 4 or 0. */ -MUSASHI_INLINE void m68ki_set_s_flag(uint value) +static inline void m68ki_set_s_flag(uint value) { /* Backup the old stack pointer */ REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; @@ -1366,7 +1366,7 @@ MUSASHI_INLINE void m68ki_set_s_flag(uint value) /* Set the S and M flags and change the active stack pointer. * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M). */ -MUSASHI_INLINE void m68ki_set_sm_flag(uint value) +static inline void m68ki_set_sm_flag(uint value) { /* Backup the old stack pointer */ REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; @@ -1378,7 +1378,7 @@ MUSASHI_INLINE void m68ki_set_sm_flag(uint value) } /* Set the S and M flags. Don't touch the stack pointer. */ -MUSASHI_INLINE void m68ki_set_sm_flag_nosp(uint value) +static inline void m68ki_set_sm_flag_nosp(uint value) { /* Set the S and M flags */ FLAG_S = value & SFLAG_SET; @@ -1387,7 +1387,7 @@ MUSASHI_INLINE void m68ki_set_sm_flag_nosp(uint value) /* Set the condition code register */ -MUSASHI_INLINE void m68ki_set_ccr(uint value) +static inline void m68ki_set_ccr(uint value) { FLAG_X = BIT_4(value) << 4; FLAG_N = BIT_3(value) << 4; @@ -1397,7 +1397,7 @@ MUSASHI_INLINE void m68ki_set_ccr(uint value) } /* Set the status register but don't check for interrupts */ -MUSASHI_INLINE void m68ki_set_sr_noint(uint value) +static inline void m68ki_set_sr_noint(uint value) { /* Mask out the "unimplemented" bits */ value &= CPU_SR_MASK; @@ -1413,7 +1413,7 @@ MUSASHI_INLINE void m68ki_set_sr_noint(uint value) /* Set the status register but don't check for interrupts nor * change the stack pointer */ -MUSASHI_INLINE void m68ki_set_sr_noint_nosp(uint value) +static inline void m68ki_set_sr_noint_nosp(uint value) { /* Mask out the "unimplemented" bits */ value &= CPU_SR_MASK; @@ -1427,7 +1427,7 @@ MUSASHI_INLINE void m68ki_set_sr_noint_nosp(uint value) } /* Set the status register and check for interrupts */ -MUSASHI_INLINE void m68ki_set_sr(uint value) +static inline void m68ki_set_sr(uint value) { m68ki_set_sr_noint(value); m68ki_check_interrupts(); @@ -1437,7 +1437,7 @@ MUSASHI_INLINE void m68ki_set_sr(uint value) /* ------------------------- Exception Processing ------------------------- */ /* Initiate exception processing */ -MUSASHI_INLINE uint m68ki_init_exception(void) +static inline uint m68ki_init_exception(void) { /* Save the old status register */ uint sr = m68ki_get_sr(); @@ -1452,7 +1452,7 @@ MUSASHI_INLINE uint m68ki_init_exception(void) } /* 3 word stack frame (68000 only) */ -MUSASHI_INLINE void m68ki_stack_frame_3word(uint pc, uint sr) +static inline void m68ki_stack_frame_3word(uint pc, uint sr) { m68ki_push_32(pc); m68ki_push_16(sr); @@ -1461,7 +1461,7 @@ MUSASHI_INLINE void m68ki_stack_frame_3word(uint pc, uint sr) /* Format 0 stack frame. * This is the standard stack frame for 68010+. */ -MUSASHI_INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) +static inline void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) { /* Stack a 3-word frame if we are 68000 */ if(CPU_TYPE == CPU_TYPE_000) @@ -1477,7 +1477,7 @@ MUSASHI_INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) /* Format 1 stack frame (68020). * For 68020, this is the 4 word throwaway frame. */ -MUSASHI_INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) +static inline void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) { m68ki_push_16(0x1000 | (vector<<2)); m68ki_push_32(pc); @@ -1487,7 +1487,7 @@ MUSASHI_INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) /* Format 2 stack frame. * This is used only by 68020 for trap exceptions. */ -MUSASHI_INLINE void m68ki_stack_frame_0010(uint sr, uint vector) +static inline void m68ki_stack_frame_0010(uint sr, uint vector) { m68ki_push_32(REG_PPC); m68ki_push_16(0x2000 | (vector<<2)); @@ -1498,7 +1498,7 @@ MUSASHI_INLINE void m68ki_stack_frame_0010(uint sr, uint vector) /* Bus error stack frame (68000 only). */ -MUSASHI_INLINE void m68ki_stack_frame_buserr(uint sr) +static inline void m68ki_stack_frame_buserr(uint sr) { m68ki_push_32(REG_PC); m68ki_push_16(sr); @@ -1687,7 +1687,7 @@ void m68ki_stack_frame_1011(uint sr, uint vector, uint pc) /* Used for Group 2 exceptions. * These stack a type 2 frame on the 020. */ -MUSASHI_INLINE void m68ki_exception_trap(uint vector) +static inline void m68ki_exception_trap(uint vector) { uint sr = m68ki_init_exception(); @@ -1703,7 +1703,7 @@ MUSASHI_INLINE void m68ki_exception_trap(uint vector) } /* Trap#n stacks a 0 frame but behaves like group2 otherwise */ -MUSASHI_INLINE void m68ki_exception_trapN(uint vector) +static inline void m68ki_exception_trapN(uint vector) { uint sr = m68ki_init_exception(); m68ki_stack_frame_0000(REG_PC, sr, vector); @@ -1714,7 +1714,7 @@ MUSASHI_INLINE void m68ki_exception_trapN(uint vector) } /* Exception for trace mode */ -MUSASHI_INLINE void m68ki_exception_trace(void) +static inline void m68ki_exception_trace(void) { uint sr = m68ki_init_exception(); @@ -1741,7 +1741,7 @@ MUSASHI_INLINE void m68ki_exception_trace(void) } /* Exception for privilege violation */ -MUSASHI_INLINE void m68ki_exception_privilege_violation(void) +static inline void m68ki_exception_privilege_violation(void) { uint sr = m68ki_init_exception(); @@ -1760,11 +1760,11 @@ MUSASHI_INLINE void m68ki_exception_privilege_violation(void) } /* Exception for A-Line instructions */ -MUSASHI_INLINE void m68ki_exception_1010(void) +static inline void m68ki_exception_1010(void) { uint sr; #if M68K_LOG_1010_1111 == OPT_ON - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n", + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08X: called 1010 instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); #endif @@ -1778,12 +1778,12 @@ MUSASHI_INLINE void m68ki_exception_1010(void) } /* Exception for F-Line instructions */ -MUSASHI_INLINE void m68ki_exception_1111(void) +static inline void m68ki_exception_1111(void) { uint sr; #if M68K_LOG_1010_1111 == OPT_ON - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n", + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08X: called 1111 instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); #endif @@ -1797,11 +1797,11 @@ MUSASHI_INLINE void m68ki_exception_1111(void) } /* Exception for illegal instructions */ -MUSASHI_INLINE void m68ki_exception_illegal(void) +static inline void m68ki_exception_illegal(void) { uint sr; - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: illegal instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); @@ -1822,7 +1822,7 @@ MUSASHI_INLINE void m68ki_exception_illegal(void) } /* Exception for format errror in RTE */ -MUSASHI_INLINE void m68ki_exception_format_error(void) +static inline void m68ki_exception_format_error(void) { uint sr = m68ki_init_exception(); m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR); @@ -1833,7 +1833,7 @@ MUSASHI_INLINE void m68ki_exception_format_error(void) } /* Exception for address error */ -MUSASHI_INLINE void m68ki_exception_address_error(void) +static inline void m68ki_exception_address_error(void) { uint sr = m68ki_init_exception(); @@ -1895,7 +1895,7 @@ void m68ki_exception_interrupt(uint int_level) vector = EXCEPTION_SPURIOUS_INTERRUPT; else if(vector > 255) { - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08X: Interrupt acknowledge returned invalid vector $%x\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); return; } @@ -1936,7 +1936,7 @@ void m68ki_exception_interrupt(uint int_level) /* ASG: Check for interrupts */ -MUSASHI_INLINE void m68ki_check_interrupts(void) +static inline void m68ki_check_interrupts(void) { if(CPU_INT_LEVEL > FLAG_INT_MASK) m68ki_exception_interrupt(CPU_INT_LEVEL>>8); diff --git a/src/m68k/m68kdasm.c b/src/m68k/m68kdasm.c index b69ab69..0c87c44 100755 --- a/src/m68k/m68kdasm.c +++ b/src/m68k/m68kdasm.c @@ -615,18 +615,18 @@ static char* get_ea_mode_str(uint instruction, uint size) static void d68000_illegal(void) { - sprintf(g_dasm_str, "dc.w $%04x; ILLEGAL", g_cpu_ir); + sprintf(g_dasm_str, "dc.w $%04X; ILLEGAL", g_cpu_ir); } static void d68000_1010(void) { - sprintf(g_dasm_str, "dc.w $%04x; opcode 1010", g_cpu_ir); + sprintf(g_dasm_str, "dc.w $%04X; opcode 1010", g_cpu_ir); } static void d68000_1111(void) { - sprintf(g_dasm_str, "dc.w $%04x; opcode 1111", g_cpu_ir); + sprintf(g_dasm_str, "dc.w $%04X; opcode 1111", g_cpu_ir); } @@ -3274,6 +3274,10 @@ uint32_t m68k_disassemble(char* str_buff, uint32_t pc, uint32_t cpu_type) g_cpu_type = TYPE_68040; g_address_mask = 0xffffffff; break; + case M68K_CPU_TYPE_DBVZ: + g_cpu_type = TYPE_68000; + g_address_mask = 0xffffffff; + break; default: return 0; } diff --git a/src/m68k/m68kopac.c b/src/m68k/m68kopac.c index df1fde3..a527b71 100755 --- a/src/m68k/m68kopac.c +++ b/src/m68k/m68kopac.c @@ -8372,7 +8372,7 @@ void m68k_op_callm_32_ai(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8391,7 +8391,7 @@ void m68k_op_callm_32_di(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8410,7 +8410,7 @@ void m68k_op_callm_32_ix(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8429,7 +8429,7 @@ void m68k_op_callm_32_aw(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8448,7 +8448,7 @@ void m68k_op_callm_32_al(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8467,7 +8467,7 @@ void m68k_op_callm_32_pcdi(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -8486,7 +8486,7 @@ void m68k_op_callm_32_pcix(void) m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ REG_PC += 2; (void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -11994,7 +11994,7 @@ void m68k_op_cpbcc_32(void) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -12007,7 +12007,7 @@ void m68k_op_cpdbcc_32(void) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -12020,7 +12020,7 @@ void m68k_op_cpgen_32(void) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -12033,7 +12033,7 @@ void m68k_op_cpscc_32(void) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; @@ -12046,7 +12046,7 @@ void m68k_op_cptrapcc_32(void) { if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; diff --git a/src/m68k/m68kopnz.c b/src/m68k/m68kopnz.c index 07b6953..a5c379a 100755 --- a/src/m68k/m68kopnz.c +++ b/src/m68k/m68kopnz.c @@ -4004,7 +4004,7 @@ void m68k_op_rtm_32(void) if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) { m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08X: called unimplemented instruction %04X (%s)\n", m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); return; diff --git a/src/makefile.all b/src/makefile.all index 2c567e6..3adea19 100644 --- a/src/makefile.all +++ b/src/makefile.all @@ -14,7 +14,6 @@ EMU_SOURCES_C := $(EMU_PATH)/emulator.c \ $(EMU_PATH)/m68k/m68kopnz.c \ $(EMU_PATH)/m68k/m68kopdm.c \ $(EMU_PATH)/m68k/m68kopac.c \ - $(EMU_PATH)/m68k/m68kdasm.c \ $(EMU_PATH)/m68k/m68kcpu.c EMU_SOURCES_CXX := EMU_SOURCES_ASM := diff --git a/src/pxa260/pxa260_CPU.h b/src/pxa260/pxa260_CPU.h index 49ac4af..93ee6e5 100644 --- a/src/pxa260/pxa260_CPU.h +++ b/src/pxa260/pxa260_CPU.h @@ -1,5 +1,5 @@ -#ifndef _CPU_H_ -#define _CPU_H_ +#ifndef PXA260_CPU_H +#define PXA260_CPU_H #include "pxa260_types.h" #include "../armv5te/emu.h" diff --git a/src/pxa260/pxa260_DMA.h b/src/pxa260/pxa260_DMA.h index de14fc2..e793867 100644 --- a/src/pxa260/pxa260_DMA.h +++ b/src/pxa260/pxa260_DMA.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_DMA_H_ -#define _PXA260_DMA_H_ +#ifndef PXA260_DMA_H +#define PXA260_DMA_H #include "pxa260_CPU.h" #include "pxa260_IC.h" diff --git a/src/pxa260/pxa260_DSP.h b/src/pxa260/pxa260_DSP.h index 88b0363..9b59480 100644 --- a/src/pxa260/pxa260_DSP.h +++ b/src/pxa260/pxa260_DSP.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_DSP_H_ -#define _PXA260_DSP_H_ +#ifndef PXA260_DSP_H +#define PXA260_DSP_H #include "pxa260_types.h" diff --git a/src/pxa260/pxa260_GPIO.h b/src/pxa260/pxa260_GPIO.h index 9227041..bf31fd7 100644 --- a/src/pxa260/pxa260_GPIO.h +++ b/src/pxa260/pxa260_GPIO.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_GPIO_H_ -#define _PXA260_GPIO_H_ +#ifndef PXA260_GPIO_H +#define PXA260_GPIO_H #include "pxa260_CPU.h" #include "pxa260_IC.h" diff --git a/src/pxa260/pxa260_IC.h b/src/pxa260/pxa260_IC.h index 8c1dfef..2b0f1b9 100644 --- a/src/pxa260/pxa260_IC.h +++ b/src/pxa260/pxa260_IC.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_IC_H_ -#define _PXA260_IC_H_ +#ifndef PXA260_IC_H +#define PXA260_IC_H #include "pxa260_CPU.h" #include diff --git a/src/pxa260/pxa260_LCD.h b/src/pxa260/pxa260_LCD.h index 10ceef9..9cc8627 100644 --- a/src/pxa260/pxa260_LCD.h +++ b/src/pxa260/pxa260_LCD.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_LCD_H_ -#define _PXA260_LCD_H_ +#ifndef PXA260_LCD_H +#define PXA260_LCD_H #include "pxa260_CPU.h" #include "pxa260_IC.h" diff --git a/src/pxa260/pxa260_PwrClk.h b/src/pxa260/pxa260_PwrClk.h index ad489a2..681f36b 100644 --- a/src/pxa260/pxa260_PwrClk.h +++ b/src/pxa260/pxa260_PwrClk.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_PWR_CLK_H_ -#define _PXA260_PWR_CLK_H_ +#ifndef PXA260_PWR_CLK_H +#define PXA260_PWR_CLK_H #include "pxa260_CPU.h" diff --git a/src/pxa260/pxa260_RTC.h b/src/pxa260/pxa260_RTC.h index c1d1582..77f352a 100644 --- a/src/pxa260/pxa260_RTC.h +++ b/src/pxa260/pxa260_RTC.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_RTC_H_ -#define _PXA260_RTC_H_ +#ifndef PXA260_RTC_H +#define PXA260_RTC_H #include "pxa260_CPU.h" #include "pxa260_IC.h" diff --git a/src/pxa260/pxa260_TIMR.h b/src/pxa260/pxa260_TIMR.h index 98fabc1..d8fcb4b 100644 --- a/src/pxa260/pxa260_TIMR.h +++ b/src/pxa260/pxa260_TIMR.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_TIMR_H_ -#define _PXA260_TIMR_H_ +#ifndef PXA260_TIMR_H +#define PXA260_TIMR_H #include "pxa260_CPU.h" #include "pxa260_IC.h" diff --git a/src/pxa260/pxa260_UART.h b/src/pxa260/pxa260_UART.h index 36969c8..9875290 100644 --- a/src/pxa260/pxa260_UART.h +++ b/src/pxa260/pxa260_UART.h @@ -1,5 +1,5 @@ -#ifndef _PXA260_UART_H_ -#define _PXA260_UART_H_ +#ifndef PXA260_UART_H +#define PXA260_UART_H #include "pxa260_CPU.h" #include "pxa260_IC.h"