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CPU/Recompiler/RISCV64: Replace lwu with lw in a couple of places
Consistency.
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@@ -277,9 +277,9 @@ u32 CPU::CodeCache::EmitASMFunctions(void* code, u32 code_size)
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rvAsm->Bind(&dispatch);
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// x9 <- s_fast_map[pc >> 16]
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rvAsm->LWU(RARG1, PTR(&g_state.pc));
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rvAsm->LW(RARG1, PTR(&g_state.pc));
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rvMoveAddressToReg(rvAsm, RARG3, g_code_lut.data());
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rvAsm->SRLI(RARG2, RARG1, 16);
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rvAsm->SRLIW(RARG2, RARG1, 16);
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rvAsm->SLLI(RARG2, RARG2, 3);
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rvAsm->ADD(RARG2, RARG2, RARG3);
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rvAsm->LD(RARG2, 0, RARG2);
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@@ -541,8 +541,8 @@ void CPU::RISCV64Recompiler::GenerateBlockProtectCheck(const u8* ram_ptr, const
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while (size >= 4)
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{
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rvAsm->LWU(RARG3, offset, RARG1);
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rvAsm->LWU(RSCRATCH, offset, RARG2);
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rvAsm->LW(RARG3, offset, RARG1);
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rvAsm->LW(RSCRATCH, offset, RARG2);
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rvAsm->BNE(RARG3, RSCRATCH, &block_changed);
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offset += 4;
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size -= 4;
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@@ -564,7 +564,7 @@ void CPU::RISCV64Recompiler::GenerateICacheCheckAndUpdate()
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if (m_block->HasFlag(CodeCache::BlockFlags::NeedsDynamicFetchTicks))
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{
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rvEmitFarLoad(rvAsm, RARG2, GetFetchMemoryAccessTimePtr());
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rvAsm->LWU(RARG1, PTR(&g_state.pending_ticks));
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rvAsm->LW(RARG1, PTR(&g_state.pending_ticks));
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rvEmitMov(rvAsm, RARG3, m_block->size);
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rvAsm->MULW(RARG2, RARG2, RARG3);
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rvAsm->ADD(RARG1, RARG1, RARG2);
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@@ -572,7 +572,7 @@ void CPU::RISCV64Recompiler::GenerateICacheCheckAndUpdate()
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}
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else
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{
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rvAsm->LWU(RARG1, PTR(&g_state.pending_ticks));
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rvAsm->LW(RARG1, PTR(&g_state.pending_ticks));
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SafeADDIW(RARG1, RARG1, static_cast<u32>(m_block->uncached_fetch_ticks));
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rvAsm->SW(RARG1, PTR(&g_state.pending_ticks));
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}
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@@ -588,7 +588,7 @@ void CPU::RISCV64Recompiler::GenerateICacheCheckAndUpdate()
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DebugAssert(!IsHostRegAllocated(maddr_reg.Index()));
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VirtualMemoryAddress current_pc = m_block->pc & ICACHE_TAG_ADDRESS_MASK;
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rvAsm->LWU(ticks_reg, PTR(&g_state.pending_ticks));
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rvAsm->LW(ticks_reg, PTR(&g_state.pending_ticks));
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rvEmitMov(rvAsm, current_tag_reg, current_pc);
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for (u32 i = 0; i < m_block->icache_line_count; i++, current_pc += ICACHE_LINE_SIZE)
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