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CPU/PGXP: Make register writes more readable
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@@ -61,6 +61,8 @@ enum : u32
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#define SET_LOWORD(val, loword) ((static_cast<u32>(val) & 0xFFFF0000u) | static_cast<u32>(static_cast<u16>(loword)))
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#define SET_HIWORD(val, hiword) ((static_cast<u32>(val) & 0x0000FFFFu) | (static_cast<u32>(hiword) << 16))
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#define PGXP_GTE_REGISTER(field) g_state.pgxp_gte[offsetof(GTE::Regs, field) / sizeof(u32)]
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static bool ShouldSavePGXPState();
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static double f16Sign(double val);
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@@ -79,9 +81,6 @@ static PGXPValue& ValidateAndGetRtValue(Instruction instr, u32 rtVal);
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static PGXPValue& ValidateAndGetRsValue(Instruction instr, u32 rsVal);
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static void SetRtValue(Instruction instr, const PGXPValue& val);
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static void SetRtValue(Instruction instr, const PGXPValue& val, u32 rtVal);
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static PGXPValue& GetSXY0();
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static PGXPValue& GetSXY1();
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static PGXPValue& GetSXY2();
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static void PushScreenXYFIFO();
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static PGXPValue* GetPtr(u32 addr);
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@@ -133,6 +132,12 @@ static std::FILE* s_log;
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void CPU::PGXP::Initialize()
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{
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// Just in case due to memory layout...
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static_assert(&PGXP_GTE_REGISTER(SXY0) == &g_state.pgxp_gte[12]);
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static_assert(&PGXP_GTE_REGISTER(SXY1) == &g_state.pgxp_gte[13]);
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static_assert(&PGXP_GTE_REGISTER(SXY2) == &g_state.pgxp_gte[14]);
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static_assert(&PGXP_GTE_REGISTER(SXYP) == &g_state.pgxp_gte[15]);
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std::memset(g_state.pgxp_gpr, 0, sizeof(g_state.pgxp_gpr));
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std::memset(g_state.pgxp_cop0, 0, sizeof(g_state.pgxp_cop0));
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std::memset(g_state.pgxp_gte, 0, sizeof(g_state.pgxp_gte));
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@@ -277,26 +282,11 @@ ALWAYS_INLINE void CPU::PGXP::SetRtValue(Instruction instr, const PGXPValue& val
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prtVal.value = rtVal;
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}
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ALWAYS_INLINE CPU::PGXPValue& CPU::PGXP::GetSXY0()
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{
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return g_state.pgxp_gte[12];
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}
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ALWAYS_INLINE CPU::PGXPValue& CPU::PGXP::GetSXY1()
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{
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return g_state.pgxp_gte[13];
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}
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ALWAYS_INLINE CPU::PGXPValue& CPU::PGXP::GetSXY2()
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{
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return g_state.pgxp_gte[14];
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}
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ALWAYS_INLINE void CPU::PGXP::PushScreenXYFIFO()
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{
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g_state.pgxp_gte[12] = g_state.pgxp_gte[13]; // SXY0 = SXY1
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g_state.pgxp_gte[13] = g_state.pgxp_gte[14]; // SXY1 = SXY2
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g_state.pgxp_gte[14] = g_state.pgxp_gte[15]; // SXY2 = SXYP
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PGXP_GTE_REGISTER(SXY0) = PGXP_GTE_REGISTER(SXY1); // SXY0 = SXY1
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PGXP_GTE_REGISTER(SXY1) = PGXP_GTE_REGISTER(SXY2); // SXY1 = SXY2
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PGXP_GTE_REGISTER(SXY2) = PGXP_GTE_REGISTER(SXYP); // SXY2 = SXYP
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}
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ALWAYS_INLINE_RELEASE CPU::PGXPValue* CPU::PGXP::GetPtr(u32 addr)
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@@ -498,25 +488,25 @@ void CPU::PGXP::LogValueStr(SmallStringBase& str, const char* name, u32 rval, co
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void CPU::PGXP::GTE_RTPS(float x, float y, float z, u32 value)
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{
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PGXPValue& pvalue = g_state.pgxp_gte[15];
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pvalue.x = x;
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pvalue.y = y;
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pvalue.z = z;
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pvalue.value = value;
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pvalue.flags = VALID_ALL;
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PGXPValue& SXYP = PGXP_GTE_REGISTER(SXYP);
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SXYP.x = x;
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SXYP.y = y;
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SXYP.z = z;
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SXYP.value = value;
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SXYP.flags = VALID_ALL;
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PushScreenXYFIFO();
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if (g_settings.gpu_pgxp_vertex_cache)
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CacheVertex(value, pvalue);
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CacheVertex(value, SXYP);
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}
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bool CPU::PGXP::GTE_HasPreciseVertices(u32 sxy0, u32 sxy1, u32 sxy2)
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{
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PGXPValue& SXY0 = GetSXY0();
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PGXPValue& SXY0 = PGXP_GTE_REGISTER(SXY0);
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SXY0.Validate(sxy0);
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PGXPValue& SXY1 = GetSXY1();
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PGXPValue& SXY1 = PGXP_GTE_REGISTER(SXY1);
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SXY1.Validate(sxy1);
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PGXPValue& SXY2 = GetSXY2();
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PGXPValue& SXY2 = PGXP_GTE_REGISTER(SXY2);
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SXY2.Validate(sxy2);
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// Don't use accurate clipping for game-constructed values, which don't have a valid Z.
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@@ -525,9 +515,9 @@ bool CPU::PGXP::GTE_HasPreciseVertices(u32 sxy0, u32 sxy1, u32 sxy2)
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float CPU::PGXP::GTE_NCLIP()
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{
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const PGXPValue& SXY0 = GetSXY0();
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const PGXPValue& SXY1 = GetSXY1();
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const PGXPValue& SXY2 = GetSXY2();
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const PGXPValue& SXY0 = PGXP_GTE_REGISTER(SXY0);
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const PGXPValue& SXY1 = PGXP_GTE_REGISTER(SXY1);
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const PGXPValue& SXY2 = PGXP_GTE_REGISTER(SXY2);
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float nclip = ((SXY0.x * SXY1.y) + (SXY1.x * SXY2.y) + (SXY2.x * SXY0.y) - (SXY0.x * SXY2.y) - (SXY1.x * SXY0.y) -
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(SXY2.x * SXY1.y));
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@@ -546,7 +536,7 @@ ALWAYS_INLINE_RELEASE void CPU::PGXP::CPU_MTC2(u32 reg, const PGXPValue& value,
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case 15:
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{
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// push FIFO
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g_state.pgxp_gte[15] = value;
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PGXP_GTE_REGISTER(SXYP) = value;
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PushScreenXYFIFO();
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return;
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}
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