Matt Sealey a460028c64 ipu: backport of IPU clock handling ...

* improve clock accuracy check from 1/16 to 1/200 of intended clock rate
* properly round pixel clock to the parent and not against a hardcoded 150MHz max rate
* properly fix di external clock divisor to a maximum of 8

2012-02-20 09:29:48 -06:00

..

ipu_calc_stripes_sizes.c

ENGR00139321 ipuv3: add YV12 format support

2011-04-20 10:01:16 -05:00

ipu_capture.c

ENGR00133318-1 IPUv3 CSI:Support SMFC channel interlaced scan order

2011-01-22 00:47:22 -06:00

ipu_common.c

ENGR00143575 IPUv3:Align IDMAC BS with DMFC FIFO BS

2011-06-28 17:47:56 -05:00

ipu_device.c

match the latest BSP caching policy for IPU - it seems that the Flash performance update actually causes some subtle artefacts which are not acceptable to users. Go from writecombine (wrong) to a custom writethrough (weird) to the standard writethrough (correct but lower performance) and remove the define that swaps it on or off

2011-07-12 11:29:11 -05:00

ipu_disp.c

ipu: backport of IPU clock handling

2012-02-20 09:29:48 -06:00

ipu_ic.c

IPU updates from latest FSL BSP, seemingly all related to burst sizes and so on. New pixel format.

2011-01-21 21:43:30 -06:00

ipu_param_mem.h

ENGR00142683 IPUv3:Increase IDMAC BS for RGBP and DMFC BS

2011-06-28 17:20:37 -05:00

ipu_prv.h

ENGR00143575 IPUv3:Align IDMAC BS with DMFC FIFO BS

2011-06-28 17:47:56 -05:00

ipu_regs.h

IPU Triple Buffering support

2011-06-28 17:20:21 -05:00

Kconfig

…

Makefile

ENGR00115576 ipuv3: support for 720P upsizing

2010-08-10 11:44:54 -05:00