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be0524d38f
This is i.MX BSP 5.0.0 release ported to 2.6.31 Signed-off-by: Rob Herring <r.herring@freescale.com> Signed-off-by: Alan Tull <r80115@freescale.com> Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
428 lines
13 KiB
C
428 lines
13 KiB
C
/*
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file dam.c
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* @brief This is the brief documentation for this dam.c file.
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*
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* This file contains the implementation of the DAM driver main services
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*
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* @ingroup DAM
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/uaccess.h>
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#include "dam.h"
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/*!
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* This include to define bool type, false and true definitions.
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*/
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#include <mach/hardware.h>
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#define ModifyRegister32(a,b,c) (c = ( ( (c)&(~(a)) ) | (b) ))
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#define DAM_VIRT_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR)
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#ifndef _reg_DAM_PTCR1
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#define _reg_DAM_PTCR1 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x00)))
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#endif
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#ifndef _reg_DAM_PDCR1
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#define _reg_DAM_PDCR1 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x04)))
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#endif
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#ifndef _reg_DAM_PTCR2
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#define _reg_DAM_PTCR2 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x08)))
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#endif
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#ifndef _reg_DAM_PDCR2
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#define _reg_DAM_PDCR2 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x0C)))
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#endif
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#ifndef _reg_DAM_PTCR3
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#define _reg_DAM_PTCR3 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x10)))
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#endif
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#ifndef _reg_DAM_PDCR3
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#define _reg_DAM_PDCR3 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x14)))
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#endif
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#ifndef _reg_DAM_PTCR4
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#define _reg_DAM_PTCR4 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x18)))
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#endif
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#ifndef _reg_DAM_PDCR4
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#define _reg_DAM_PDCR4 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x1C)))
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#endif
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#ifndef _reg_DAM_PTCR5
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#define _reg_DAM_PTCR5 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x20)))
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#endif
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#ifndef _reg_DAM_PDCR5
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#define _reg_DAM_PDCR5 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x24)))
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#endif
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#ifndef _reg_DAM_PTCR6
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#define _reg_DAM_PTCR6 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x28)))
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#endif
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#ifndef _reg_DAM_PDCR6
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#define _reg_DAM_PDCR6 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x2C)))
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#endif
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#ifndef _reg_DAM_PTCR7
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#define _reg_DAM_PTCR7 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x30)))
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#endif
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#ifndef _reg_DAM_PDCR7
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#define _reg_DAM_PDCR7 (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x34)))
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#endif
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#ifndef _reg_DAM_CNMCR
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#define _reg_DAM_CNMCR (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 0x38)))
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#endif
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#ifndef _reg_DAM_PTCR
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#define _reg_DAM_PTCR(a) (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + a*8)))
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#endif
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#ifndef _reg_DAM_PDCR
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#define _reg_DAM_PDCR(a) (*((volatile unsigned long *) \
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(DAM_VIRT_BASE_ADDR + 4 + a*8)))
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#endif
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/*!
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* PTCR Registers bit shift definitions
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*/
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#define dam_synchronous_mode_shift 11
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#define dam_receive_clock_select_shift 12
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#define dam_receive_clock_direction_shift 16
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#define dam_receive_frame_sync_select_shift 17
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#define dam_receive_frame_sync_direction_shift 21
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#define dam_transmit_clock_select_shift 22
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#define dam_transmit_clock_direction_shift 26
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#define dam_transmit_frame_sync_select_shift 27
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#define dam_transmit_frame_sync_direction_shift 31
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#define dam_selection_mask 0xF
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/*!
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* HPDCR Register bit shift definitions
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*/
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#define dam_internal_network_mode_shift 0
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#define dam_mode_shift 8
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#define dam_transmit_receive_switch_shift 12
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#define dam_receive_data_select_shift 13
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/*!
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* HPDCR Register bit masq definitions
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*/
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#define dam_mode_masq 0x03
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#define dam_internal_network_mode_mask 0xFF
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/*!
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* CNMCR Register bit shift definitions
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*/
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#define dam_ce_bus_port_cntlow_shift 0
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#define dam_ce_bus_port_cnthigh_shift 8
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#define dam_ce_bus_port_clkpol_shift 16
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#define dam_ce_bus_port_fspol_shift 17
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#define dam_ce_bus_port_enable_shift 18
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#define DAM_NAME "dam"
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EXPORT_SYMBOL(dam_select_mode);
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EXPORT_SYMBOL(dam_select_RxClk_direction);
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EXPORT_SYMBOL(dam_select_RxClk_source);
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EXPORT_SYMBOL(dam_select_RxD_source);
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EXPORT_SYMBOL(dam_select_RxFS_direction);
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EXPORT_SYMBOL(dam_select_RxFS_source);
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EXPORT_SYMBOL(dam_select_TxClk_direction);
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EXPORT_SYMBOL(dam_select_TxClk_source);
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EXPORT_SYMBOL(dam_select_TxFS_direction);
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EXPORT_SYMBOL(dam_select_TxFS_source);
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EXPORT_SYMBOL(dam_set_internal_network_mode_mask);
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EXPORT_SYMBOL(dam_set_synchronous);
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EXPORT_SYMBOL(dam_switch_Tx_Rx);
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EXPORT_SYMBOL(dam_reset_register);
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/*!
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* This function selects the operation mode of the port.
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*
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* @param port the DAM port to configure
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* @param the_mode the operation mode of the port
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*
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* @return This function returns the result of the operation
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* (0 if successful, -1 otherwise).
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*/
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int dam_select_mode(dam_port port, dam_mode the_mode)
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{
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int result;
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result = 0;
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ModifyRegister32(dam_mode_masq << dam_mode_shift,
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the_mode << dam_mode_shift, _reg_DAM_PDCR(port));
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return result;
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}
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/*!
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* This function controls Receive clock signal direction for the port.
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*
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* @param port the DAM port to configure
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* @param direction the Rx clock signal direction
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*/
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void dam_select_RxClk_direction(dam_port port, signal_direction direction)
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{
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ModifyRegister32(1 << dam_receive_clock_direction_shift,
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direction << dam_receive_clock_direction_shift,
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_reg_DAM_PTCR(port));
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}
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/*!
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* This function controls Receive clock signal source for the port.
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*
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* @param p_config the DAM port to configure
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* @param from_RxClk the signal comes from RxClk or TxClk of
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* the source port
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* @param p_source the source port
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*/
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void dam_select_RxClk_source(dam_port p_config,
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bool from_RxClk, dam_port p_source)
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{
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ModifyRegister32(dam_selection_mask << dam_receive_clock_select_shift,
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((from_RxClk << 3) | p_source) <<
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dam_receive_clock_select_shift,
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_reg_DAM_PTCR(p_config));
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}
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/*!
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* This function selects the source port for the RxD data.
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*
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* @param p_config the DAM port to configure
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* @param p_source the source port
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*/
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void dam_select_RxD_source(dam_port p_config, dam_port p_source)
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{
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ModifyRegister32(dam_selection_mask << dam_receive_data_select_shift,
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p_source << dam_receive_data_select_shift,
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_reg_DAM_PDCR(p_config));
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}
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/*!
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* This function controls Receive Frame Sync signal direction for the port.
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*
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* @param port the DAM port to configure
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* @param direction the Rx Frame Sync signal direction
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*/
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void dam_select_RxFS_direction(dam_port port, signal_direction direction)
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{
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ModifyRegister32(1 << dam_receive_frame_sync_direction_shift,
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direction << dam_receive_frame_sync_direction_shift,
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_reg_DAM_PTCR(port));
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}
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/*!
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* This function controls Receive Frame Sync signal source for the port.
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*
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* @param p_config the DAM port to configure
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* @param from_RxFS the signal comes from RxFS or TxFS of
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* the source port
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* @param p_source the source port
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*/
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void dam_select_RxFS_source(dam_port p_config,
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bool from_RxFS, dam_port p_source)
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{
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ModifyRegister32(dam_selection_mask <<
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dam_receive_frame_sync_select_shift,
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((from_RxFS << 3) | p_source) <<
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dam_receive_frame_sync_select_shift,
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_reg_DAM_PTCR(p_config));
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}
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/*!
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* This function controls Transmit clock signal direction for the port.
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*
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* @param port the DAM port to configure
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* @param direction the Tx clock signal direction
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*/
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void dam_select_TxClk_direction(dam_port port, signal_direction direction)
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{
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ModifyRegister32(1 << dam_transmit_clock_direction_shift,
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direction << dam_transmit_clock_direction_shift,
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_reg_DAM_PTCR(port));
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}
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/*!
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* This function controls Transmit clock signal source for the port.
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*
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* @param p_config the DAM port to configure
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* @param from_RxClk the signal comes from RxClk or TxClk of
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* the source port
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* @param p_source the source port
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*/
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void dam_select_TxClk_source(dam_port p_config,
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bool from_RxClk, dam_port p_source)
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{
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ModifyRegister32(dam_selection_mask << dam_transmit_clock_select_shift,
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((from_RxClk << 3) | p_source) <<
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dam_transmit_clock_select_shift,
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_reg_DAM_PTCR(p_config));
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}
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/*!
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* This function controls Transmit Frame Sync signal direction for the port.
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*
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* @param port the DAM port to configure
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* @param direction the Tx Frame Sync signal direction
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*/
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void dam_select_TxFS_direction(dam_port port, signal_direction direction)
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{
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ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift,
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direction << dam_transmit_frame_sync_direction_shift,
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_reg_DAM_PTCR(port));
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}
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/*!
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* This function controls Transmit Frame Sync signal source for the port.
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*
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* @param p_config the DAM port to configure
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* @param from_RxFS the signal comes from RxFS or TxFS of
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* the source port
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* @param p_source the source port
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*/
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void dam_select_TxFS_source(dam_port p_config,
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bool from_RxFS, dam_port p_source)
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{
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ModifyRegister32(dam_selection_mask <<
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dam_transmit_frame_sync_select_shift,
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((from_RxFS << 3) | p_source) <<
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dam_transmit_frame_sync_select_shift,
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_reg_DAM_PTCR(p_config));
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}
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/*!
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* This function sets a bit mask that selects the port from which of the RxD
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* signals are to be ANDed together for internal network mode.
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* Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1.
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* 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing.
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*
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* @param port the DAM port to configure
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* @param bit_mask the bit mask
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*
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* @return This function returns the result of the operation
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* (0 if successful, -1 otherwise).
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*/
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int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask)
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{
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int result;
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result = 0;
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ModifyRegister32(dam_internal_network_mode_mask <<
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dam_internal_network_mode_shift,
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bit_mask << dam_internal_network_mode_shift,
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_reg_DAM_PDCR(port));
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return result;
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}
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/*!
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* This function controls whether or not the port is in synchronous mode.
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* When the synchronous mode is selected, the receive and the transmit sections
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* use common clock and frame sync signals.
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* When the synchronous mode is not selected, separate clock and frame sync
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* signals are used for the transmit and the receive sections.
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* The defaut value is the synchronous mode selected.
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*
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* @param port the DAM port to configure
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* @param synchronous the state to assign
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*/
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void dam_set_synchronous(dam_port port, bool synchronous)
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{
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ModifyRegister32(1 << dam_synchronous_mode_shift,
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synchronous << dam_synchronous_mode_shift,
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_reg_DAM_PTCR(port));
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}
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/*!
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* This function swaps the transmit and receive signals from (Da-TxD, Db-RxD)
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* to (Da-RxD, Db-TxD).
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* This default signal configuration is Da-TxD, Db-RxD.
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*
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* @param port the DAM port to configure
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* @param value the switch state
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*/
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void dam_switch_Tx_Rx(dam_port port, bool value)
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{
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ModifyRegister32(1 << dam_transmit_receive_switch_shift,
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value << dam_transmit_receive_switch_shift,
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_reg_DAM_PDCR(port));
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}
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/*!
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* This function resets the two registers of the selected port.
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*
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* @param port the DAM port to reset
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*/
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void dam_reset_register(dam_port port)
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{
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ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PTCR(port));
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ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PDCR(port));
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}
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/*!
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* This function implements the init function of the DAM device.
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* This function is called when the module is loaded.
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*
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* @return This function returns 0.
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*/
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static int __init dam_init(void)
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{
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return 0;
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}
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/*!
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* This function implements the exit function of the SPI device.
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* This function is called when the module is unloaded.
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*
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*/
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static void __exit dam_exit(void)
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{
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}
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module_init(dam_init);
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module_exit(dam_exit);
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MODULE_DESCRIPTION("DAM char device driver");
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MODULE_AUTHOR("Freescale Semiconductor, Inc.");
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MODULE_LICENSE("GPL");
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