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7f6076dd6d
Integrate atheros driver package from atheros company. It's mainly for AR6003. Signed-off-by: Nathan Cheng <Nathan.Cheng@Atheros.com> Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
237 lines
9.7 KiB
C
237 lines
9.7 KiB
C
//------------------------------------------------------------------------------
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// <copyright file="target_reg_table.h" company="Atheros">
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// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License version 2 as
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// published by the Free Software Foundation;
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//
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// Software distributed under the License is distributed on an "AS
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// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// rights and limitations under the License.
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//
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//
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//------------------------------------------------------------------------------
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//==============================================================================
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// Target register table macros and structure definitions
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//
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// Author(s): ="Atheros"
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//==============================================================================
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#ifndef TARGET_REG_TABLE_H_
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#define TARGET_REG_TABLE_H_
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#include "targaddrs.h"
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/*** WARNING : Add to the end of the TABLE! do not change the order ****/
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typedef struct targetdef_s {
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A_UINT32 d_RTC_BASE_ADDRESS;
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A_UINT32 d_SYSTEM_SLEEP_OFFSET;
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A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB;
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A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK;
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A_UINT32 d_CLOCK_CONTROL_OFFSET;
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A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK;
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A_UINT32 d_RESET_CONTROL_OFFSET;
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A_UINT32 d_RESET_CONTROL_SI0_RST_MASK;
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A_UINT32 d_GPIO_BASE_ADDRESS;
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A_UINT32 d_GPIO_PIN0_OFFSET;
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A_UINT32 d_GPIO_PIN1_OFFSET;
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A_UINT32 d_GPIO_PIN0_CONFIG_MASK;
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A_UINT32 d_GPIO_PIN1_CONFIG_MASK;
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A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
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A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
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A_UINT32 d_SI_CONFIG_I2C_LSB;
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A_UINT32 d_SI_CONFIG_I2C_MASK;
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A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB;
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A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK;
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A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB;
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A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK;
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A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB;
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A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK;
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A_UINT32 d_SI_CONFIG_DIVIDER_LSB;
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A_UINT32 d_SI_CONFIG_DIVIDER_MASK;
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A_UINT32 d_SI_BASE_ADDRESS;
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A_UINT32 d_SI_CONFIG_OFFSET;
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A_UINT32 d_SI_TX_DATA0_OFFSET;
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A_UINT32 d_SI_TX_DATA1_OFFSET;
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A_UINT32 d_SI_RX_DATA0_OFFSET;
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A_UINT32 d_SI_RX_DATA1_OFFSET;
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A_UINT32 d_SI_CS_OFFSET;
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A_UINT32 d_SI_CS_DONE_ERR_MASK;
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A_UINT32 d_SI_CS_DONE_INT_MASK;
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A_UINT32 d_SI_CS_START_LSB;
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A_UINT32 d_SI_CS_START_MASK;
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A_UINT32 d_SI_CS_RX_CNT_LSB;
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A_UINT32 d_SI_CS_RX_CNT_MASK;
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A_UINT32 d_SI_CS_TX_CNT_LSB;
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A_UINT32 d_SI_CS_TX_CNT_MASK;
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A_UINT32 d_BOARD_DATA_SZ;
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} TARGET_REGISTER_TABLE;
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#define BOARD_DATA_SZ_MAX 2048
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#if defined(MY_TARGET_DEF) /* { */
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#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
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static struct targetdef_s my_target_def = {
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RTC_BASE_ADDRESS,
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SYSTEM_SLEEP_OFFSET,
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SYSTEM_SLEEP_DISABLE_LSB,
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SYSTEM_SLEEP_DISABLE_MASK,
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CLOCK_CONTROL_OFFSET,
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CLOCK_CONTROL_SI0_CLK_MASK,
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RESET_CONTROL_OFFSET,
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RESET_CONTROL_SI0_RST_MASK,
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GPIO_BASE_ADDRESS,
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GPIO_PIN0_OFFSET,
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GPIO_PIN0_CONFIG_MASK,
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GPIO_PIN1_OFFSET,
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GPIO_PIN1_CONFIG_MASK,
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SI_CONFIG_BIDIR_OD_DATA_LSB,
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SI_CONFIG_BIDIR_OD_DATA_MASK,
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SI_CONFIG_I2C_LSB,
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SI_CONFIG_I2C_MASK,
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SI_CONFIG_POS_SAMPLE_LSB,
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SI_CONFIG_POS_SAMPLE_MASK,
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SI_CONFIG_INACTIVE_CLK_LSB,
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SI_CONFIG_INACTIVE_CLK_MASK,
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SI_CONFIG_INACTIVE_DATA_LSB,
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SI_CONFIG_INACTIVE_DATA_MASK,
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SI_CONFIG_DIVIDER_LSB,
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SI_CONFIG_DIVIDER_MASK,
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SI_BASE_ADDRESS,
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SI_CONFIG_OFFSET,
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SI_TX_DATA0_OFFSET,
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SI_TX_DATA1_OFFSET,
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SI_RX_DATA0_OFFSET,
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SI_RX_DATA1_OFFSET,
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SI_CS_OFFSET,
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SI_CS_DONE_ERR_MASK,
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SI_CS_DONE_INT_MASK,
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SI_CS_START_LSB,
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SI_CS_START_MASK,
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SI_CS_RX_CNT_LSB,
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SI_CS_RX_CNT_MASK,
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SI_CS_TX_CNT_LSB,
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SI_CS_TX_CNT_MASK,
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MY_TARGET_BOARD_DATA_SZ,
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};
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#else
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static struct targetdef_s my_target_def = {
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.d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
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.d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
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.d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
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.d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
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.d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
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.d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
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.d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
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.d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
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.d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
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.d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
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.d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
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.d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
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.d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
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.d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
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.d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
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.d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
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.d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
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.d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
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.d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
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.d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
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.d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
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.d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
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.d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
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.d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
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.d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
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.d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
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.d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
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.d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
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.d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
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.d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
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.d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
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.d_SI_CS_OFFSET = SI_CS_OFFSET,
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.d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
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.d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
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.d_SI_CS_START_LSB = SI_CS_START_LSB,
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.d_SI_CS_START_MASK = SI_CS_START_MASK,
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.d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
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.d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
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.d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
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.d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
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.d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
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};
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#endif
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#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
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#error "BOARD_DATA_SZ_MAX is too small"
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#endif
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struct targetdef_s *MY_TARGET_DEF = &my_target_def;
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#else /* } { */
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#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
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#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
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#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
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#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
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#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
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#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
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#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
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#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
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#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
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#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
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#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
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#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
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#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
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#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
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#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
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#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
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#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
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#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
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#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
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#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
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#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
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#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
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#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
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#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
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#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
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#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
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#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
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#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
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#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
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#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
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#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
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#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
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#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
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#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
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#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
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/* SET macros */
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#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
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#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
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#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
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#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
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#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
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#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
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#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
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#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
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#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
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#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
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#endif /* } */
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#endif /*TARGET_REG_TABLE_H_*/
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