/*
 * ASPEED SoC 27x0 family
 *
 * Copyright (C) 2024 ASPEED Technology Inc.
 *
 * This code is licensed under the GPL version 2 or later.  See
 * the COPYING file in the top-level directory.
 *
 * Implementation extracted from the AST2600 and adapted for AST27x0.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/bsa.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "system/qtest.h"
#include "system/system.h"
#include "hw/intc/arm_gicv3.h"
#include "qobject/qlist.h"
#include "qemu/log.h"

#define AST2700_SOC_IO_SIZE          0x00FE0000
#define AST2700_SOC_IOMEM_SIZE       0x01000000
#define AST2700_SOC_DPMCU_SIZE       0x00040000

static const hwaddr aspeed_soc_ast2700_memmap[] = {
    [ASPEED_DEV_VBOOTROM]  =  0x00000000,
    [ASPEED_DEV_IOMEM]     =  0x00020000,
    [ASPEED_DEV_SRAM0]     =  0x10000000,
    [ASPEED_DEV_DPMCU]     =  0x11000000,
    [ASPEED_DEV_IOMEM0]    =  0x12000000,
    [ASPEED_DEV_EHCI1]     =  0x12061000,
    [ASPEED_DEV_EHCI2]     =  0x12063000,
    [ASPEED_DEV_HACE]      =  0x12070000,
    [ASPEED_DEV_EMMC]      =  0x12090000,
    [ASPEED_DEV_PCIE0]     =  0x120E0000,
    [ASPEED_DEV_PCIE1]     =  0x120F0000,
    [ASPEED_DEV_INTC]      =  0x12100000,
    [ASPEED_GIC_DIST]      =  0x12200000,
    [ASPEED_GIC_REDIST]    =  0x12280000,
    [ASPEED_DEV_SDMC]      =  0x12C00000,
    [ASPEED_DEV_SCU]       =  0x12C02000,
    [ASPEED_DEV_RTC]       =  0x12C0F000,
    [ASPEED_DEV_TIMER1]    =  0x12C10000,
    [ASPEED_DEV_PCIE_PHY0] =  0x12C15000,
    [ASPEED_DEV_PCIE_PHY1] =  0x12C15800,
    [ASPEED_DEV_SLI]       =  0x12C17000,
    [ASPEED_DEV_UART4]     =  0x12C1A000,
    [ASPEED_DEV_IOMEM1]    =  0x14000000,
    [ASPEED_DEV_FMC]       =  0x14000000,
    [ASPEED_DEV_SPI0]      =  0x14010000,
    [ASPEED_DEV_SPI1]      =  0x14020000,
    [ASPEED_DEV_SPI2]      =  0x14030000,
    [ASPEED_DEV_MII1]      =  0x14040000,
    [ASPEED_DEV_MII2]      =  0x14040008,
    [ASPEED_DEV_MII3]      =  0x14040010,
    [ASPEED_DEV_ETH1]      =  0x14050000,
    [ASPEED_DEV_ETH2]      =  0x14060000,
    [ASPEED_DEV_ETH3]      =  0x14070000,
    [ASPEED_DEV_SDHCI]     =  0x14080000,
    [ASPEED_DEV_PCIE2]     =  0x140D0000,
    [ASPEED_DEV_EHCI3]     =  0x14121000,
    [ASPEED_DEV_EHCI4]     =  0x14123000,
    [ASPEED_DEV_ADC]       =  0x14C00000,
    [ASPEED_DEV_SCUIO]     =  0x14C02000,
    [ASPEED_DEV_GPIO]      =  0x14C0B000,
    [ASPEED_DEV_SGPIOM0]   =  0x14C0C000,
    [ASPEED_DEV_SGPIOM1]   =  0x14C0D000,
    [ASPEED_DEV_I2C]       =  0x14C0F000,
    [ASPEED_DEV_INTCIO]    =  0x14C18000,
    [ASPEED_DEV_PCIE_PHY2] =  0x14C1C000,
    [ASPEED_DEV_SLIIO]     =  0x14C1E000,
    [ASPEED_DEV_VUART]     =  0x14C30000,
    [ASPEED_DEV_UART0]     =  0x14C33000,
    [ASPEED_DEV_UART1]     =  0x14C33100,
    [ASPEED_DEV_UART2]     =  0x14C33200,
    [ASPEED_DEV_UART3]     =  0x14C33300,
    [ASPEED_DEV_UART5]     =  0x14C33400,
    [ASPEED_DEV_UART6]     =  0x14C33500,
    [ASPEED_DEV_UART7]     =  0x14C33600,
    [ASPEED_DEV_UART8]     =  0x14C33700,
    [ASPEED_DEV_UART9]     =  0x14C33800,
    [ASPEED_DEV_UART10]    =  0x14C33900,
    [ASPEED_DEV_UART11]    =  0x14C33A00,
    [ASPEED_DEV_UART12]    =  0x14C33B00,
    [ASPEED_DEV_LTPI_CTRL1] =  0x14C34000,
    [ASPEED_DEV_LTPI_CTRL2] =  0x14C35000,
    [ASPEED_DEV_WDT]       =  0x14C37000,
    [ASPEED_DEV_LTPI_IO0]  =  0x30000000,
    [ASPEED_DEV_IOEXP0_INTCIO] = 0x30C18000,
    [ASPEED_DEV_LTPI_IO1]  =  0x50000000,
    [ASPEED_DEV_IOEXP1_INTCIO] = 0x50C18000,
    [ASPEED_DEV_PCIE_MMIO0] = 0x60000000,
    [ASPEED_DEV_PCIE_MMIO1] = 0x80000000,
    [ASPEED_DEV_PCIE_MMIO2] = 0xA0000000,
    [ASPEED_DEV_SPI_BOOT]  =  0x100000000,
    [ASPEED_DEV_SDRAM]     =  0x400000000,
};

#define AST2700_MAX_IRQ 256

/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2700a1_irqmap[] = {
    [ASPEED_DEV_SDMC]      = 0,
    [ASPEED_DEV_HACE]      = 4,
    [ASPEED_DEV_XDMA]      = 5,
    [ASPEED_DEV_UART4]     = 8,
    [ASPEED_DEV_SCU]       = 12,
    [ASPEED_DEV_RTC]       = 13,
    [ASPEED_DEV_EMMC]      = 15,
    [ASPEED_DEV_TIMER1]    = 16,
    [ASPEED_DEV_TIMER2]    = 17,
    [ASPEED_DEV_TIMER3]    = 18,
    [ASPEED_DEV_TIMER4]    = 19,
    [ASPEED_DEV_TIMER5]    = 20,
    [ASPEED_DEV_TIMER6]    = 21,
    [ASPEED_DEV_TIMER7]    = 22,
    [ASPEED_DEV_TIMER8]    = 23,
    [ASPEED_DEV_DP]        = 28,
    [ASPEED_DEV_EHCI1]     = 33,
    [ASPEED_DEV_EHCI2]     = 37,
    [ASPEED_DEV_PCIE0]     = 56,
    [ASPEED_DEV_PCIE1]     = 57,
    [ASPEED_DEV_LPC]       = 192,
    [ASPEED_DEV_IBT]       = 192,
    [ASPEED_DEV_KCS]       = 192,
    [ASPEED_DEV_I2C]       = 194,
    [ASPEED_DEV_ADC]       = 194,
    [ASPEED_DEV_GPIO]      = 194,
    [ASPEED_DEV_SGPIOM0]   = 194,
    [ASPEED_DEV_SGPIOM1]   = 194,
    [ASPEED_DEV_FMC]       = 195,
    [ASPEED_DEV_WDT]       = 195,
    [ASPEED_DEV_PWM]       = 195,
    [ASPEED_DEV_I3C]       = 195,
    [ASPEED_DEV_PCIE2]     = 196,
    [ASPEED_DEV_UART0]     = 196,
    [ASPEED_DEV_UART1]     = 196,
    [ASPEED_DEV_UART2]     = 196,
    [ASPEED_DEV_UART3]     = 196,
    [ASPEED_DEV_UART5]     = 196,
    [ASPEED_DEV_UART6]     = 196,
    [ASPEED_DEV_UART7]     = 196,
    [ASPEED_DEV_UART8]     = 196,
    [ASPEED_DEV_UART9]     = 196,
    [ASPEED_DEV_UART10]    = 196,
    [ASPEED_DEV_UART11]    = 196,
    [ASPEED_DEV_UART12]    = 196,
    [ASPEED_DEV_ETH1]      = 196,
    [ASPEED_DEV_ETH2]      = 196,
    [ASPEED_DEV_ETH3]      = 196,
    [ASPEED_DEV_EHCI3]     = 196,
    [ASPEED_DEV_EHCI4]     = 196,
    [ASPEED_DEV_PECI]      = 197,
    [ASPEED_DEV_SDHCI]     = 197,
    [ASPEED_DEV_IOEXP0_I2C] = 198,
    [ASPEED_DEV_IOEXP0_I3C] = 199,
    [ASPEED_DEV_IOEXP1_I2C] = 200,
    [ASPEED_DEV_IOEXP1_I3C] = 201,
};

/* GICINT 192 */
static const int ast2700_gic192_intcmap[] = {
    [ASPEED_DEV_LPC]       = 0,
    [ASPEED_DEV_IBT]       = 2,
    [ASPEED_DEV_KCS]       = 4,
};

/* GICINT 193 */

/* GICINT 194 */
static const int ast2700_gic194_intcmap[] = {
    [ASPEED_DEV_I2C]        = 0,
    [ASPEED_DEV_ADC]        = 16,
    [ASPEED_DEV_GPIO]       = 18,
    [ASPEED_DEV_SGPIOM0]    = 21,
    [ASPEED_DEV_SGPIOM1]    = 24,
};

/* GICINT 195 */
static const int ast2700_gic195_intcmap[] = {
    [ASPEED_DEV_I3C]       = 0,
    [ASPEED_DEV_WDT]       = 16,
    [ASPEED_DEV_FMC]       = 25,
    [ASPEED_DEV_PWM]       = 29,
};

/* GICINT 196 */
static const int ast2700_gic196_intcmap[] = {
    [ASPEED_DEV_ETH1]      = 0,
    [ASPEED_DEV_ETH2]      = 1,
    [ASPEED_DEV_ETH3]      = 2,
    [ASPEED_DEV_UART0]     = 7,
    [ASPEED_DEV_UART1]     = 8,
    [ASPEED_DEV_UART2]     = 9,
    [ASPEED_DEV_UART3]     = 10,
    [ASPEED_DEV_UART5]     = 11,
    [ASPEED_DEV_UART6]     = 12,
    [ASPEED_DEV_UART7]     = 13,
    [ASPEED_DEV_UART8]     = 14,
    [ASPEED_DEV_UART9]     = 15,
    [ASPEED_DEV_UART10]    = 16,
    [ASPEED_DEV_UART11]    = 17,
    [ASPEED_DEV_UART12]    = 18,
    [ASPEED_DEV_EHCI3]     = 28,
    [ASPEED_DEV_EHCI4]     = 29,
    [ASPEED_DEV_PCIE2]     = 31,
};

/* GICINT 197 */
static const int ast2700_gic197_intcmap[] = {
    [ASPEED_DEV_SDHCI]     = 1,
    [ASPEED_DEV_PECI]      = 4,
};

/* Primary AST1700 Interrupts */
/* A1: GICINT 198 */
static const int ast2700_gic198_intcmap[] = {
    [ASPEED_DEV_IOEXP0_I2C]       = 0, /* 0 - 15 */
};

/* Primary AST1700 Interrupts */
/* A1: GINTC 199 */
static const int ast2700_gic199_intcmap[] = {
    [ASPEED_DEV_IOEXP0_I3C]       = 0, /* 0 - 15 */
};

/* Secondary AST1700 Interrupts */
/* A1: GINTC 200 */
static const int ast2700_gic200_intcmap[] = {
    [ASPEED_DEV_IOEXP1_I2C]       = 0, /* 0 - 15 */
};

/* Secondary AST1700 Interrupts */
/* A1: GINTC 201 */
static const int ast2700_gic201_intcmap[] = {
    [ASPEED_DEV_IOEXP1_I3C]       = 0, /* 0 - 15 */
};

/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
    int irq;
    int intc_idx;
    int orgate_idx;
    const int *ptr;
};

static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
    {192, 1, 0, ast2700_gic192_intcmap},
    {193, 1, 1, NULL},
    {194, 1, 2, ast2700_gic194_intcmap},
    {195, 1, 3, ast2700_gic195_intcmap},
    {196, 1, 4, ast2700_gic196_intcmap},
    {197, 1, 5, ast2700_gic197_intcmap},
    {198, 2, 0, ast2700_gic198_intcmap},
    {199, 2, 1, ast2700_gic199_intcmap},
    {200, 3, 0, ast2700_gic200_intcmap},
    {201, 3, 1, ast2700_gic201_intcmap},
};

static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
{
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int or_idx;
    int idx;
    int i;

    for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
        if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
            assert(ast2700_gic_intcmap[i].ptr);
            or_idx = ast2700_gic_intcmap[i].orgate_idx;
            idx = ast2700_gic_intcmap[i].intc_idx;
            return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
                                    ast2700_gic_intcmap[i].ptr[dev]);
        }
    }

    return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
}

static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
                                                 int index)
{
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int or_idx;
    int idx;
    int i;
    OrIRQState *porgates;

    for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
        if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
            assert(ast2700_gic_intcmap[i].ptr);
            or_idx = ast2700_gic_intcmap[i].orgate_idx;
            idx = ast2700_gic_intcmap[i].intc_idx;
            if (idx < ASPEED_INTC_NUM) {
                porgates = &a->intc[idx].orgates[or_idx];
                return qdev_get_gpio_in(DEVICE(porgates),
                                    ast2700_gic_intcmap[i].ptr[dev] + index);
            } else {
                idx -= ASPEED_INTC_NUM;
                porgates = &a->intcioexp[idx].orgates[or_idx];
                return qdev_get_gpio_in(DEVICE(porgates),
                                    ast2700_gic_intcmap[i].ptr[dev] + index);
            }
        }
    }

    /*
     * Invalid OR gate index, device IRQ should be between 192 to 201.
     */
    g_assert_not_reached();
}

static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
                                                    unsigned int size)
{
    qemu_log_mask(LOG_GUEST_ERROR,
                  "%s: DRAM read out of ram size, addr:0x%" PRIx64 "\n",
                   __func__, addr);
    return 0;
}

static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
                                                unsigned int size)
{
    AspeedSoCState *s = ASPEED_SOC(opaque);
    ram_addr_t ram_size;
    MemTxResult result;

    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
                                        &error_abort);

    assert(ram_size > 0);

    /*
     * Emulate ddr capacity hardware behavior.
     * If writes the data to the address which is beyond the ram size,
     * it would write the data to the "address % ram_size".
     */
    address_space_stl_le(&s->dram_as, addr % ram_size, data,
                         MEMTXATTRS_UNSPECIFIED, &result);

    if (result != MEMTX_OK) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: DRAM write failed, addr:0x%" HWADDR_PRIx
                      ", data :0x%" PRIx64  "\n",
                      __func__, addr % ram_size, data);
    }
}

static const MemoryRegionOps aspeed_ram_capacity_ops = {
    .read = aspeed_ram_capacity_read,
    .write = aspeed_ram_capacity_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .impl.min_access_size = 4,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

/*
 * SDMC should be realized first to get correct RAM size and max size
 * values
 */
static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
{
    ram_addr_t ram_size, max_ram_size;
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
                                        &error_abort);
    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
                                            &error_abort);

    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
                       ram_size);
    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
    address_space_init(&s->dram_as, s->dram_mr, "dram");

    /*
     * Add a memory region beyond the RAM region to emulate
     * ddr capacity hardware behavior.
     */
    if (ram_size < max_ram_size) {
        memory_region_init_io(&a->dram_empty, OBJECT(s),
                              &aspeed_ram_capacity_ops, s,
                              "ram-empty", max_ram_size - ram_size);

        memory_region_add_subregion(s->memory,
                                    sc->memmap[ASPEED_DEV_SDRAM] + ram_size,
                                    &a->dram_empty);
    }

    memory_region_add_subregion(s->memory,
                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
    return true;
}

static void aspeed_soc_ast2700_init(Object *obj)
{
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
    AspeedSoCState *s = ASPEED_SOC(obj);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    int i;
    char socname[8];
    char typename[64];

    if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
        g_assert_not_reached();
    }

    for (i = 0; i < sc->num_cpus; i++) {
        if (qtest_enabled() && !target_aarch64()) {
            /*
             * Introspection qtest just want to create this object
             * without realizing it. ARM_CPU_TYPE_NAME("cortex-a35")
             * is not available on 32-bit binary: skip it since we
             * won't even realize it.
             */
            continue;
        }
        object_initialize_child(obj, "cpu[*]", &a->cpu[i],
                                aspeed_soc_cpu_type(sc->valid_cpu_types));
    }

    object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());

    object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
    qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
                         sc->silicon_rev);
    object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
                              "hw-strap1");
    object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                              "hw-prot-key");

    object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
    qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
                         sc->silicon_rev);
    /*
     * There is one hw-strap1 register in the SCU (CPU DIE) and another
     * hw-strap1 register in the SCUIO (IO DIE). To reuse the current design
     * of hw-strap, hw-strap1 is assigned to the SCU and sets the value in the
     * SCU hw-strap1 register, while hw-strap2 is assigned to the SCUIO and
     * sets the value in the SCUIO hw-strap1 register.
     */
    object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scuio),
                                  "hw-strap1");

    snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
    object_initialize_child(obj, "fmc", &s->fmc, typename);

    for (i = 0; i < sc->spis_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i, socname);
        object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
    }

    for (i = 0; i < sc->ehcis_num; i++) {
        object_initialize_child(obj, "ehci[*]", &s->ehci[i],
                                TYPE_PLATFORM_EHCI);
    }

    snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
    object_initialize_child(obj, "sdmc", &s->sdmc, typename);
    object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                              "ram-size");

    for (i = 0; i < sc->wdts_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
        object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
    }

    for (i = 0; i < sc->macs_num; i++) {
        object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
                                TYPE_FTGMAC100);

        object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
    }

    for (i = 0; i < sc->uarts_num; i++) {
        object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
    }

    object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
    object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
    object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
    object_initialize_child(obj, "intcio", &a->intc[1],
                            TYPE_ASPEED_2700_INTCIO);
    object_initialize_child(obj, "intc-ioexp0", &a->intcioexp[0],
                            TYPE_ASPEED_2700_INTCIOEXP1);
    object_initialize_child(obj, "intc-ioexp1", &a->intcioexp[1],
                            TYPE_ASPEED_2700_INTCIOEXP2);

    snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
    object_initialize_child(obj, "adc", &s->adc, typename);

    snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
    object_initialize_child(obj, "i2c", &s->i2c, typename);

    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
    object_initialize_child(obj, "gpio", &s->gpio, typename);

    snprintf(typename, sizeof(typename), "aspeed.sgpio-%s", socname);
    for (i = 0; i < sc->sgpio_num; i++) {
        object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i], typename);
    }

    object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);

    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
    object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
    object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort);

    /* Init sd card slot class here so that they're under the correct parent */
    object_initialize_child(obj, "sd-controller.sdhci",
                            &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);

    object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
    object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);

    object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
                            TYPE_SYSBUS_SDHCI);

    snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
    object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);

    snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
    object_initialize_child(obj, "hace", &s->hace, typename);

    for (i = 0; i < sc->pcie_num; i++) {
        snprintf(typename, sizeof(typename), "aspeed.pcie-phy-%s", socname);
        object_initialize_child(obj, "pcie-phy[*]", &s->pcie_phy[i], typename);
        object_property_set_int(OBJECT(&s->pcie_phy[i]), "id", i, &error_abort);

        snprintf(typename, sizeof(typename), "aspeed.pcie-cfg-%s", socname);
        object_initialize_child(obj, "pcie-cfg[*]", &s->pcie[i], typename);
        object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort);
    }

    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
        object_initialize_child(obj, "ltpi-ctrl[*]",
                                &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI);
    }

    for (i = 0; i < sc->ioexp_num; i++) {
        /* AST1700 IOEXP */
        object_initialize_child(obj, "ioexp[*]", &s->ioexp[i],
                                TYPE_ASPEED_AST1700);
        qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev",
                             sc->silicon_rev);
    }

    object_initialize_child(obj, "dpmcu", &s->dpmcu,
                            TYPE_UNIMPLEMENTED_DEVICE);
    object_initialize_child(obj, "iomem", &s->iomem,
                            TYPE_UNIMPLEMENTED_DEVICE);
    object_initialize_child(obj, "iomem0", &s->iomem0,
                            TYPE_UNIMPLEMENTED_DEVICE);
    object_initialize_child(obj, "iomem1", &s->iomem1,
                            TYPE_UNIMPLEMENTED_DEVICE);
}

/*
 * ASPEED ast2700 has 0x0 as cluster ID
 *
 * https://developer.arm.com/documentation/100236/0100/register-descriptions/aarch64-system-registers/multiprocessor-affinity-register--el1
 */
static uint64_t aspeed_calc_affinity(int cpu)
{
    return (0x0 << ARM_AFF1_SHIFT) | cpu;
}

static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
{
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    SysBusDevice *gicbusdev;
    DeviceState *gicdev;
    QList *redist_region_count;
    int i;

    gicbusdev = SYS_BUS_DEVICE(&a->gic);
    gicdev = DEVICE(&a->gic);
    qdev_prop_set_uint32(gicdev, "revision", 3);
    qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus);
    qdev_prop_set_uint32(gicdev, "num-irq", AST2700_MAX_IRQ + GIC_INTERNAL);

    redist_region_count = qlist_new();
    qlist_append_int(redist_region_count, sc->num_cpus);
    qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);

    if (!sysbus_realize(gicbusdev, errp)) {
        return false;
    }

    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 0,
                    sc->memmap[ASPEED_GIC_DIST]);
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->gic), 1,
                    sc->memmap[ASPEED_GIC_REDIST]);

    for (i = 0; i < sc->num_cpus; i++) {
        DeviceState *cpudev = DEVICE(&a->cpu[i]);
        int intidbase = AST2700_MAX_IRQ + i * GIC_INTERNAL;

        const int timer_irq[] = {
            [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
            [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
            [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
            [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
        };
        int j;

        for (j = 0; j < ARRAY_SIZE(timer_irq); j++) {
            qdev_connect_gpio_out(cpudev, j,
                    qdev_get_gpio_in(gicdev, intidbase + timer_irq[j]));
        }

        qemu_irq irq = qdev_get_gpio_in(gicdev,
                                        intidbase + ARCH_GIC_MAINT_IRQ);
        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
                                    0, irq);
        qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
                qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ));

        sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
        sysbus_connect_irq(gicbusdev, i + sc->num_cpus,
                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
        sysbus_connect_irq(gicbusdev, i + 2 * sc->num_cpus,
                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
        sysbus_connect_irq(gicbusdev, i + 3 * sc->num_cpus,
                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
        sysbus_connect_irq(gicbusdev, i + 4 * sc->num_cpus,
                           qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
        sysbus_connect_irq(gicbusdev, i + 5 * sc->num_cpus,
                           qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
    }

    return true;
}

static bool aspeed_soc_ast2700_pcie_realize(DeviceState *dev, Error **errp)
{
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    MemoryRegion *mmio_mr = NULL;
    char name[64];
    qemu_irq irq;
    int i;

    for (i = 0; i < sc->pcie_num; i++) {
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy[i]), errp)) {
            return false;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie_phy[i]), 0,
                        sc->memmap[ASPEED_DEV_PCIE_PHY0 + i]);

        object_property_set_int(OBJECT(&s->pcie[i]), "dram-base",
                                sc->memmap[ASPEED_DEV_SDRAM],
                                &error_abort);
        object_property_set_link(OBJECT(&s->pcie[i]), "dram",
                                 OBJECT(s->dram_mr), &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie[i]), errp)) {
            return false;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->pcie[i]), 0,
                        sc->memmap[ASPEED_DEV_PCIE0 + i]);
        irq = aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_PCIE0 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie[i].rc), 0, irq);

        mmio_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pcie[i].rc), 1);
        snprintf(name, sizeof(name), "aspeed.pcie-mmio.%d", i);
        memory_region_init_alias(&s->pcie_mmio_alias[i], OBJECT(&s->pcie[i].rc),
                                 name, mmio_mr,
                                 sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i],
                                 0x20000000);
        memory_region_add_subregion(s->memory,
                                    sc->memmap[ASPEED_DEV_PCIE_MMIO0 + i],
                                    &s->pcie_mmio_alias[i]);
    }

    return true;
}

static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
{
    int i;
    Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
    AspeedSoCState *s = ASPEED_SOC(dev);
    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
    AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]);
    AspeedINTCClass *icio = ASPEED_INTC_GET_CLASS(&a->intc[1]);
    g_autofree char *name = NULL;
    qemu_irq irq;
    int uart;

    if (qtest_enabled() && !target_aarch64()) {
        g_assert_not_reached();
    }

    /* Default boot region (SPI memory or ROMs) */
    memory_region_init(&s->spi_boot_container, OBJECT(s),
                       "aspeed.spi_boot_container", 0x400000000);
    memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
                                &s->spi_boot_container);

    /* CPU */
    for (i = 0; i < sc->num_cpus; i++) {
        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                aspeed_calc_affinity(i), &error_abort);

        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                &error_abort);
        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                 OBJECT(s->memory), &error_abort);

        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
            return;
        }
    }

    /* GIC */
    if (!aspeed_soc_ast2700_gic_realize(dev, errp)) {
        return;
    }

    /* INTC */
    if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
        return;
    }

    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[0]), 0,
                    sc->memmap[ASPEED_DEV_INTC]);

    /* INTCIO */
    if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
        return;
    }

    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0,
                    sc->memmap[ASPEED_DEV_INTCIO]);

    /* INTCIOEXP0 */
    if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) {
        return;
    }

    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0,
                    sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]);

    /* INTCIOEXP1 */
    if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) {
        return;
    }

    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0,
                    sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]);

    /* irq sources -> orgates -> INTC */
    for (i = 0; i < ic->num_inpins; i++) {
        qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
                              qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
    }

    /* INTC -> GIC192 - GIC201 */
    for (i = 0; i < ic->num_outpins; i++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
                           qdev_get_gpio_in(DEVICE(&a->gic),
                                            ast2700_gic_intcmap[i].irq));
    }

    /* irq source -> orgates -> INTCIO */
    for (i = 0; i < icio->num_inpins; i++) {
        qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
                              qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
    }

    /* INTCIO -> INTC */
    for (i = 0; i < icio->num_outpins; i++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
                           qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
    }

    /* SRAM */
    name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
    if (!memory_region_init_ram(&s->sram[0], OBJECT(s), name,
                                sc->sram_size[0], errp)) {
        return;
    }
    memory_region_add_subregion(s->memory,
                                sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);

    /* VBOOTROM */
    if (!memory_region_init_ram(&s->vbootrom, OBJECT(s), "aspeed.vbootrom",
                                0x20000, errp)) {
        return;
    }
    memory_region_add_subregion(s->memory,
                                sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);

    /* SCU */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
                    sc->memmap[ASPEED_DEV_SCU]);

    /* SCU1 */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->scuio), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scuio), 0,
                    sc->memmap[ASPEED_DEV_SCUIO]);

    /* UART */
    for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
        if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
                                     sc->memmap[uart], errp)) {
            return;
        }
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           aspeed_soc_ast2700_get_irq(s, uart));
    }

    /* FMC, The number of CS is set at the board level */
    object_property_set_int(OBJECT(&s->fmc), "dram-base",
                            sc->memmap[ASPEED_DEV_SDRAM],
                            &error_abort);
    object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0,
                    sc->memmap[ASPEED_DEV_FMC]);
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 1,
                    ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_FMC));

    /* Set up an alias on the FMC CE0 region (boot default) */
    MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
    memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
                             fmc0_mmio, 0, memory_region_size(fmc0_mmio));
    memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);

    /* SPI */
    for (i = 0; i < sc->spis_num; i++) {
        object_property_set_link(OBJECT(&s->spi[i]), "dram",
                                 OBJECT(s->dram_mr), &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0,
                        sc->memmap[ASPEED_DEV_SPI0 + i]);
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
                        ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i));
    }

    /* EHCI */
    for (i = 0; i < sc->ehcis_num; i++) {
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ehci[i]), 0,
                        sc->memmap[ASPEED_DEV_EHCI1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
                           aspeed_soc_ast2700_get_irq(s,
                                                      ASPEED_DEV_EHCI1 + i));
    }

    /*
     * SDMC - SDRAM Memory Controller
     * The SDMC controller is unlocked at SPL stage.
     * At present, only supports to emulate booting
     * start from u-boot stage. Set SDMC controller
     * unlocked by default. It is a temporarily solution.
     */
    object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
                                 &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
                    sc->memmap[ASPEED_DEV_SDMC]);

    /* RAM */
    if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
        return;
    }

    /* Net */
    for (i = 0; i < sc->macs_num; i++) {
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
                                 &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                        sc->memmap[ASPEED_DEV_ETH1 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
                           aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ETH1 + i));

        object_property_set_link(OBJECT(&s->mii[i]), "nic",
                                 OBJECT(&s->ftgmac100[i]), &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
            return;
        }

        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->mii[i]), 0,
                        sc->memmap[ASPEED_DEV_MII1 + i]);
    }

    /* Watch dog */
    for (i = 0; i < sc->wdts_num; i++) {
        AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;

        object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                 &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
    }

    /* SLI */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sli), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sli), 0,
                    sc->memmap[ASPEED_DEV_SLI]);

    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sliio), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sliio), 0,
                    sc->memmap[ASPEED_DEV_SLIIO]);

    /* ADC */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0,
                    sc->memmap[ASPEED_DEV_ADC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));

    /* I2C */
    object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0,
                    sc->memmap[ASPEED_DEV_I2C]);
    for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
        /*
         * The AST2700 I2C controller has one source INTC per bus.
         *
         * I2C bus interrupts are connected to the OR gate from bit 0 to bit
         * 15, and the OR gate output pin is connected to the input pin of
         * GICINT194 of INTCIO (IO Die). Then, the output pin is connected
         * to the INTC (CPU Die) input pin, and its output pin is connected
         * to the GIC.
         *
         * I2C bus 0 is connected to the OR gate at bit 0.
         * I2C bus 15 is connected to the OR gate at bit 15.
         */
        irq = aspeed_soc_ast2700_get_irq_index(s, ASPEED_DEV_I2C, i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
    }

    /* GPIO */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0,
                    sc->memmap[ASPEED_DEV_GPIO]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));

    /* SGPIO */
    for (i = 0; i < sc->sgpio_num; i++) {
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0,
                        sc->memmap[ASPEED_DEV_SGPIOM0 + i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sgpiom[i]), 0,
                        aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SGPIOM0 + i));
    }

    /* RTC */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->rtc), 0,
                    sc->memmap[ASPEED_DEV_RTC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_RTC));

    /* SDHCI */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdhci), 0,
                    sc->memmap[ASPEED_DEV_SDHCI]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SDHCI));

    /* eMMC */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->emmc), 0,
                    sc->memmap[ASPEED_DEV_EMMC]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_EMMC));

    /* Timer */
    object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0,
                    sc->memmap[ASPEED_DEV_TIMER1]);
    for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
        irq = aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_TIMER1 + i);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
    }

    /* HACE */
    object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
                             &error_abort);
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
        return;
    }
    aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0,
                    sc->memmap[ASPEED_DEV_HACE]);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                       aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_HACE));

    /* PCIe Root Complex (RC) */
    if (!aspeed_soc_ast2700_pcie_realize(dev, errp)) {
        return;
    }

    /* LTPI controller */
    for (i = 0; i < ASPEED_IOEXP_NUM; i++) {
        AspeedLTPIState *ltpi_ctrl;
        hwaddr ltpi_base;

        ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[i]);
        ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i];

        if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) {
            return;
        }
        aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base);
    }

    /* IO Expander */
    for (i = 0; i < sc->ioexp_num; i++) {
        AspeedI2CClass *i2c_ctl;

        qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i);
        object_property_set_link(OBJECT(&s->ioexp[i]), "dram",
                                 OBJECT(s->dram_mr), &error_abort);
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) {
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0,
                        sc->memmap[ASPEED_DEV_LTPI_IO0 + i]);

        icio = ASPEED_INTC_GET_CLASS(&a->intcioexp[i]);
        /* INTC_IOEXP internal: orgate[i] -> input[i] */
        for (int j = 0; j < icio->num_inpins; j++) {
            irq = qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j);
            qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0,
                                  irq);
        }

        /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */
        for (int j = 0; j < icio->num_outpins; j++) {
            irq = qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j);
            sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j,
                               irq);
        }

        /* ADC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0,
                           aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC));

        /* GPIO */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0,
                           aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));

        /* I2C */
        i2c_ctl = ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c);
        for (int j = 0; j < i2c_ctl->num_busses; j++) {
            /*
             * For I2C on AST1700:
             * I2C bus interrupts are connected to the OR gate from bit 0 to bit
             * 15, and the OR gate output pin is connected to the input pin of
             * GICINT192 of IO expander Interrupt controller (INTC2/3). Then,
             * the output pin is connected to the INTC (CPU Die) input pin, and
             * its output pin is connected to the GIC.
             *
             * I2C bus 0 is connected to the OR gate at bit 0.
             * I2C bus 15 is connected to the OR gate at bit 15.
             */
            irq = aspeed_soc_ast2700_get_irq_index(s,
                                                   ASPEED_DEV_IOEXP0_I2C + i,
                                                   j);
            sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]),
                               0, irq);
        }
    }

    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
                                  "aspeed.dpmcu",
                                  sc->memmap[ASPEED_DEV_DPMCU],
                                  AST2700_SOC_DPMCU_SIZE);
    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem),
                                  "aspeed.io",
                                  sc->memmap[ASPEED_DEV_IOMEM],
                                  AST2700_SOC_IO_SIZE);
    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem0),
                                  "aspeed.iomem0",
                                  sc->memmap[ASPEED_DEV_IOMEM0],
                                  AST2700_SOC_IOMEM_SIZE);
    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem1),
                                  "aspeed.iomem1",
                                  sc->memmap[ASPEED_DEV_IOMEM1],
                                  AST2700_SOC_IOMEM_SIZE);
}

static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data)
{
    static const char * const valid_cpu_types[] = {
        ARM_CPU_TYPE_NAME("cortex-a35"),
        NULL
    };
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    /* Reason: The Aspeed SoC can only be instantiated from a board */
    dc->user_creatable = false;
    dc->realize      = aspeed_soc_ast2700_realize;

    sc->valid_cpu_types = valid_cpu_types;
    sc->silicon_rev  = AST2700_A1_SILICON_REV;
    sc->sram_size[0] = 0x20000;
    sc->pcie_num     = 3;
    sc->spis_num     = 3;
    sc->sgpio_num    = 2;
    sc->ehcis_num    = 4;
    sc->wdts_num     = 8;
    sc->macs_num     = 3;
    sc->uarts_num    = 13;
    sc->num_cpus     = 4;
    sc->ioexp_num    = 2;
    sc->uarts_base   = ASPEED_DEV_UART0;
    sc->irqmap       = aspeed_soc_ast2700a1_irqmap;
    sc->memmap       = aspeed_soc_ast2700_memmap;
}

static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data)
{
    static const char * const valid_cpu_types[] = {
        ARM_CPU_TYPE_NAME("cortex-a35"),
        NULL
    };
    DeviceClass *dc = DEVICE_CLASS(oc);
    AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);

    /* Reason: The Aspeed SoC can only be instantiated from a board */
    dc->user_creatable = false;
    dc->realize      = aspeed_soc_ast2700_realize;

    sc->valid_cpu_types = valid_cpu_types;
    sc->silicon_rev  = AST2700_A2_SILICON_REV;
    sc->sram_size[0] = 0x20000;
    sc->pcie_num     = 3;
    sc->spis_num     = 3;
    sc->sgpio_num    = 2;
    sc->ehcis_num    = 4;
    sc->wdts_num     = 8;
    sc->macs_num     = 3;
    sc->uarts_num    = 13;
    sc->num_cpus     = 4;
    sc->ioexp_num    = 2;
    sc->uarts_base   = ASPEED_DEV_UART0;
    sc->irqmap       = aspeed_soc_ast2700a1_irqmap;
    sc->memmap       = aspeed_soc_ast2700_memmap;
}

static const TypeInfo aspeed_soc_ast27x0_types[] = {
    {
        .name           = TYPE_ASPEED27X0_SOC,
        .parent         = TYPE_ASPEED_SOC,
        .instance_size  = sizeof(Aspeed27x0SoCState),
        .abstract       = true,
    },
    {
        .name           = "ast2700-a1",
        .parent         = TYPE_ASPEED27X0_SOC,
        .instance_init  = aspeed_soc_ast2700_init,
        .class_init     = aspeed_soc_ast2700a1_class_init,
    },
    {
        .name           = "ast2700-a2",
        .parent         = TYPE_ASPEED27X0_SOC,
        .instance_init  = aspeed_soc_ast2700_init,
        .class_init     = aspeed_soc_ast2700a2_class_init,
    },
};

DEFINE_TYPES(aspeed_soc_ast27x0_types)
