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bbea2f1a6d
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
317 lines
9.8 KiB
C
317 lines
9.8 KiB
C
/*
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* Hexagon Global Registers
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*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "hw/hexagon/hexagon.h"
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#include "hw/hexagon/hexagon_globalreg.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/core/sysbus.h"
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#include "hw/core/resettable.h"
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#include "migration/vmstate.h"
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#include "qom/object.h"
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#include "target/hexagon/cpu.h"
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#include "target/hexagon/hex_regs.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "qapi/error.h"
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#define IMMUTABLE (~0)
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#define INVALID_REG_VAL 0xdeadbeef
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static const char *hex_sreg_names[] = {
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[HEX_SREG_SGP0] = "sgp0",
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[HEX_SREG_SGP1] = "sgp1",
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[HEX_SREG_STID] = "stid",
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[HEX_SREG_ELR] = "elr",
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[HEX_SREG_BADVA0] = "badva0",
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[HEX_SREG_BADVA1] = "badva1",
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[HEX_SREG_SSR] = "ssr",
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[HEX_SREG_CCR] = "ccr",
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[HEX_SREG_HTID] = "htid",
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[HEX_SREG_BADVA] = "badva",
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[HEX_SREG_IMASK] = "imask",
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[HEX_SREG_GEVB] = "gevb",
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[HEX_SREG_EVB] = "evb",
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[HEX_SREG_MODECTL] = "modectl",
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[HEX_SREG_SYSCFG] = "syscfg",
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[HEX_SREG_IPENDAD] = "ipendad",
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[HEX_SREG_VID] = "vid",
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[HEX_SREG_VID1] = "vid1",
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[HEX_SREG_BESTWAIT] = "bestwait",
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[HEX_SREG_IEL] = "iel",
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[HEX_SREG_SCHEDCFG] = "schedcfg",
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[HEX_SREG_IAHL] = "iahl",
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[HEX_SREG_CFGBASE] = "cfgbase",
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[HEX_SREG_DIAG] = "diag",
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[HEX_SREG_REV] = "rev",
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[HEX_SREG_PCYCLELO] = "pcyclelo",
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[HEX_SREG_PCYCLEHI] = "pcyclehi",
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[HEX_SREG_ISDBST] = "isdbst",
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[HEX_SREG_ISDBCFG0] = "isdbcfg0",
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[HEX_SREG_ISDBCFG1] = "isdbcfg1",
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[HEX_SREG_LIVELOCK] = "livelock",
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[HEX_SREG_BRKPTPC0] = "brkptpc0",
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[HEX_SREG_BRKPTCFG0] = "brkptcfg0",
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[HEX_SREG_BRKPTPC1] = "brkptpc1",
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[HEX_SREG_BRKPTCFG1] = "brkptcfg1",
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[HEX_SREG_ISDBMBXIN] = "isdbmbxin",
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[HEX_SREG_ISDBMBXOUT] = "isdbmbxout",
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[HEX_SREG_ISDBEN] = "isdben",
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[HEX_SREG_ISDBGPR] = "isdbgpr",
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[HEX_SREG_PMUCNT4] = "pmucnt4",
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[HEX_SREG_PMUCNT5] = "pmucnt5",
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[HEX_SREG_PMUCNT6] = "pmucnt6",
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[HEX_SREG_PMUCNT7] = "pmucnt7",
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[HEX_SREG_PMUCNT0] = "pmucnt0",
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[HEX_SREG_PMUCNT1] = "pmucnt1",
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[HEX_SREG_PMUCNT2] = "pmucnt2",
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[HEX_SREG_PMUCNT3] = "pmucnt3",
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[HEX_SREG_PMUEVTCFG] = "pmuevtcfg",
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[HEX_SREG_PMUSTID0] = "pmustid0",
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[HEX_SREG_PMUEVTCFG1] = "pmuevtcfg1",
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[HEX_SREG_PMUSTID1] = "pmustid1",
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[HEX_SREG_TIMERLO] = "timerlo",
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[HEX_SREG_TIMERHI] = "timerhi",
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[HEX_SREG_PMUCFG] = "pmucfg",
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[HEX_SREG_S59] = "s59",
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[HEX_SREG_S60] = "s60",
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[HEX_SREG_S61] = "s61",
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[HEX_SREG_S62] = "s62",
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[HEX_SREG_S63] = "s63",
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};
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static const char *get_sreg_name(uint32_t reg)
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{
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if (reg < ARRAY_SIZE(hex_sreg_names) && hex_sreg_names[reg]) {
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return hex_sreg_names[reg];
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}
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return "UNKNOWN";
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}
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/* Global system register mutability masks */
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static const uint32_t global_sreg_immut_masks[NUM_SREGS] = {
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[HEX_SREG_EVB] = 0x000000ff,
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[HEX_SREG_MODECTL] = IMMUTABLE,
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[HEX_SREG_SYSCFG] = 0x80001c00,
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[HEX_SREG_IPENDAD] = IMMUTABLE,
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[HEX_SREG_VID] = 0xfc00fc00,
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[HEX_SREG_VID1] = 0xfc00fc00,
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[HEX_SREG_BESTWAIT] = 0xfffffe00,
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[HEX_SREG_IAHL] = 0x00000000,
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[HEX_SREG_SCHEDCFG] = 0xfffffee0,
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[HEX_SREG_CFGBASE] = IMMUTABLE,
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[HEX_SREG_DIAG] = 0x00000000,
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[HEX_SREG_REV] = IMMUTABLE,
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[HEX_SREG_ISDBST] = IMMUTABLE,
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[HEX_SREG_ISDBCFG0] = 0xe0000000,
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[HEX_SREG_BRKPTPC0] = 0x00000003,
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[HEX_SREG_BRKPTCFG0] = 0xfc007000,
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[HEX_SREG_BRKPTPC1] = 0x00000003,
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[HEX_SREG_BRKPTCFG1] = 0xfc007000,
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[HEX_SREG_ISDBMBXIN] = IMMUTABLE,
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[HEX_SREG_ISDBMBXOUT] = 0x00000000,
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[HEX_SREG_ISDBEN] = 0xfffffffe,
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[HEX_SREG_TIMERLO] = IMMUTABLE,
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[HEX_SREG_TIMERHI] = IMMUTABLE,
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};
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static void hexagon_globalreg_init(Object *obj)
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{
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HexagonGlobalRegState *s = HEXAGON_GLOBALREG(obj);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static inline uint32_t apply_write_mask(uint32_t new_val, uint32_t cur_val,
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uint32_t reg_mask)
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{
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if (reg_mask) {
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return (new_val & ~reg_mask) | (cur_val & reg_mask);
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}
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return new_val;
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}
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uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t htid)
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{
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uint32_t value;
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if (!s) {
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return 0;
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}
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g_assert(reg < NUM_SREGS);
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g_assert(reg >= HEX_SREG_GLB_START);
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value = s->regs[reg];
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trace_hexagon_globalreg_read(htid, get_sreg_name(reg), value);
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return value;
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}
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void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value, uint32_t htid)
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{
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if (!s) {
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return;
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}
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g_assert(reg < NUM_SREGS);
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g_assert(reg >= HEX_SREG_GLB_START);
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s->regs[reg] = value;
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trace_hexagon_globalreg_write(htid, get_sreg_name(reg), value);
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}
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uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value)
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{
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uint32_t reg_mask;
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if (!s) {
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return value;
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}
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g_assert(reg < NUM_SREGS);
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g_assert(reg >= HEX_SREG_GLB_START);
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reg_mask = global_sreg_immut_masks[reg];
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return reg_mask == IMMUTABLE ?
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s->regs[reg] :
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apply_write_mask(value, s->regs[reg], reg_mask);
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}
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void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg,
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uint32_t value)
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{
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if (!s) {
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return;
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}
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s->regs[reg] = hexagon_globalreg_masked_value(s, reg, value);
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}
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uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s)
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{
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g_assert(s);
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return s->g_pcycle_base;
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}
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void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s,
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uint64_t value)
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{
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g_assert(s);
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s->g_pcycle_base = value;
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}
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static void do_hexagon_globalreg_reset(HexagonGlobalRegState *s)
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{
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uint32_t isdben_val = 0;
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g_assert(s);
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memset(s->regs, 0, sizeof(s->regs));
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s->g_pcycle_base = 0;
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s->regs[HEX_SREG_EVB] = s->boot_evb;
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s->regs[HEX_SREG_CFGBASE] = HEXAGON_CFG_ADDR_BASE(s->config_table_addr);
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s->regs[HEX_SREG_REV] = s->dsp_rev;
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if (s->isdben_etm_enable) {
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isdben_val |= (1 << 0); /* ETM enable bit */
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}
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if (s->isdben_dfd_enable) {
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isdben_val |= (1 << 1); /* DFD enable bit */
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}
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if (s->isdben_trusted) {
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isdben_val |= (1 << 2); /* Trusted bit */
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}
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if (s->isdben_secure) {
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isdben_val |= (1 << 3); /* Secure bit */
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}
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s->regs[HEX_SREG_ISDBEN] = isdben_val;
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s->regs[HEX_SREG_MODECTL] = 0x1;
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/*
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* These register indices are placeholders in these arrays
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* and their actual values are synthesized from state elsewhere.
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* We can initialize these with invalid values so that if we
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* mistakenly generate reads, they will look obviously wrong.
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*/
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s->regs[HEX_SREG_PCYCLELO] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PCYCLEHI] = INVALID_REG_VAL;
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s->regs[HEX_SREG_TIMERLO] = INVALID_REG_VAL;
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s->regs[HEX_SREG_TIMERHI] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT0] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT1] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT2] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT3] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT4] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT5] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT6] = INVALID_REG_VAL;
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s->regs[HEX_SREG_PMUCNT7] = INVALID_REG_VAL;
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}
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static void hexagon_globalreg_reset_hold(Object *obj, ResetType type)
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{
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HexagonGlobalRegState *s = HEXAGON_GLOBALREG(obj);
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do_hexagon_globalreg_reset(s);
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}
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static const VMStateDescription vmstate_hexagon_globalreg = {
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.name = "hexagon_globalreg",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]){
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VMSTATE_UINT32_ARRAY(regs, HexagonGlobalRegState, NUM_SREGS),
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VMSTATE_UINT64(g_pcycle_base, HexagonGlobalRegState),
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VMSTATE_UINT32(boot_evb, HexagonGlobalRegState),
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VMSTATE_UINT64(config_table_addr, HexagonGlobalRegState),
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VMSTATE_UINT32(dsp_rev, HexagonGlobalRegState),
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VMSTATE_BOOL(isdben_etm_enable, HexagonGlobalRegState),
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VMSTATE_BOOL(isdben_dfd_enable, HexagonGlobalRegState),
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VMSTATE_BOOL(isdben_trusted, HexagonGlobalRegState),
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VMSTATE_BOOL(isdben_secure, HexagonGlobalRegState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const Property hexagon_globalreg_properties[] = {
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DEFINE_PROP_UINT32("boot-evb", HexagonGlobalRegState, boot_evb, 0x0),
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DEFINE_PROP_UINT64("config-table-addr", HexagonGlobalRegState,
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config_table_addr, 0xffffffffULL),
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DEFINE_PROP_UINT32("dsp-rev", HexagonGlobalRegState, dsp_rev, 0),
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DEFINE_PROP_BOOL("isdben-etm-enable", HexagonGlobalRegState,
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isdben_etm_enable, false),
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DEFINE_PROP_BOOL("isdben-dfd-enable", HexagonGlobalRegState,
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isdben_dfd_enable, false),
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DEFINE_PROP_BOOL("isdben-trusted", HexagonGlobalRegState,
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isdben_trusted, false),
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DEFINE_PROP_BOOL("isdben-secure", HexagonGlobalRegState,
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isdben_secure, false),
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};
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static void hexagon_globalreg_class_init(ObjectClass *klass, const void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = hexagon_globalreg_reset_hold;
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dc->vmsd = &vmstate_hexagon_globalreg;
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dc->user_creatable = false;
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device_class_set_props(dc, hexagon_globalreg_properties);
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}
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static const TypeInfo hexagon_globalreg_info = {
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.name = TYPE_HEXAGON_GLOBALREG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(HexagonGlobalRegState),
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.instance_init = hexagon_globalreg_init,
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.class_init = hexagon_globalreg_class_init,
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};
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static void hexagon_globalreg_register_types(void)
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{
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type_register_static(&hexagon_globalreg_info);
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}
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type_init(hexagon_globalreg_register_types)
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