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cbf62eef84
As a part of GSOC 2025 I have done a massive rewrite of what was the 82596 NIC. This has been done to add the missing functionality according to the 82596 Manual and making the code production ready. This patch adds: - comprehensive 82596 constants and configuration macros - address translation for segmented/linear memory modes - error recording and statistics tracking infrastructure - CRC-16/32 calculation and appending functions - CSMA/CD collision detection and backoff logic - bus throttle timer framework - enhanced reset with full state initialization - receive_iov and polling support functions - updated VMState for migration of all new fields Note: This patch primarily includes placeholder code. To achieve full 82596 emulation, the complete 82596 patch series is required. Nevertheless, QEMU is able to load and boot successfully with this patch. Signed-off-by: Soumyajyotii Ssarkar <soumyajyotisarkar23@gmail.com> Tested-by: Helge Deller <deller@gmx.de> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Helge Deller <deller@gmx.de>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
#ifndef HW_I82596_H
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#define HW_I82596_H
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#define I82596_IOPORT_SIZE 0x20
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#include "system/memory.h"
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#include "system/address-spaces.h"
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#define PACKET_QUEUE_SIZE 64
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#define RX_RING_SIZE 16
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#define PKT_BUF_SZ 1536
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#define PORT_RESET 0x00
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#define PORT_SELFTEST 0x01
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#define PORT_ALTSCP 0x02
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#define PORT_ALTDUMP 0x03
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#define PORT_CA 0x10
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typedef struct I82596State_st I82596State;
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struct I82596State_st {
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MemoryRegion mmio;
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MemoryRegion *as;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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QEMUTimer *flush_queue_timer;
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uint8_t mode;
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QEMUTimer *throttle_timer;
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uint16_t t_on;
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uint16_t t_off;
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bool throttle_state;
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hwaddr scp;
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uint32_t iscp;
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uint8_t sysbus;
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uint32_t scb;
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uint32_t scb_base;
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uint16_t scb_status;
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uint8_t cu_status, rx_status;
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uint16_t lnkst;
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uint32_t last_tx_len;
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uint32_t collision_events;
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uint32_t total_collisions;
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uint32_t tx_retry_addr;
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int tx_retry_count;
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uint32_t tx_good_frames;
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uint32_t tx_collisions;
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uint32_t tx_aborted_errors;
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uint32_t cmd_p;
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int ca;
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int ca_active;
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int send_irq;
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uint8_t mult[8];
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uint8_t config[14];
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uint32_t crc_err;
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uint32_t align_err;
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uint32_t resource_err;
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uint32_t over_err;
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uint32_t rcvdt_err;
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uint32_t short_fr_error;
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uint32_t total_frames;
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uint32_t total_good_frames;
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uint8_t tx_buffer[PKT_BUF_SZ];
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uint8_t rx_buffer[PKT_BUF_SZ];
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uint16_t tx_frame_len;
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uint16_t rx_frame_len;
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hwaddr current_tx_desc;
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hwaddr current_rx_desc;
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uint32_t last_good_rfa;
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uint8_t packet_queue[PACKET_QUEUE_SIZE][PKT_BUF_SZ];
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size_t packet_queue_len[PACKET_QUEUE_SIZE];
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int queue_head;
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int queue_tail;
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int queue_count;
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bool rnr_signaled;
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bool flushing_queue;
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};
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void i82596_h_reset(void *opaque);
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void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
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uint32_t i82596_ioport_readw(void *opaque, uint32_t addr);
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ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
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ssize_t i82596_receive_iov(NetClientState *nc, const struct iovec *iov,
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int iovcnt);
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bool i82596_can_receive(NetClientState *nc);
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void i82596_set_link_status(NetClientState *nc);
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void i82596_poll(NetClientState *nc, bool enable);
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void i82596_common_init(DeviceState *dev, I82596State *s,
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NetClientInfo *info);
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extern const VMStateDescription vmstate_i82596;
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#endif
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