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b254e48624
First RISC-V PR for 11. * Remove unused import statement from sifive_u test * Free allocated memory in core/loader * Add all available CSRs to 'info registers' * Add 'riscv-aia' accel prop info to documentation * Fix IOMMU MemoryRegion owner * Make riscv cpu.h target partially independent * Expand AIA target[i] source handling and refactor related code * Don't look up DDT cache in Off and Bare modes * Add Zilsd and Zclsd extension support * Add RISCV ZALASR extension * Add support for MIPS P8700 CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmlgmt8ACgkQr3yVEwxT # gBMxsRAAsdrRs8jrvjJqA60vt6Q/YZRCZFTeRfGlq92zVV4cmkUIkZdCESQsbToV # lGmbdLXXeC8huxh27zjQuoO9JZzPlg6tBzxCpuNXnrTQB57UKjLJoQ4rKJ9F6wT+ # iakZ3ky6iN9N64p1lDRwfph7hjxodb6Vxgi/iBTsWdj1p4OsJgL2kOPSVBZLdkoL # fTngoy0bmnV83o2eXIBx09YMxCaT3zjrhIf5lZ3zIeML8wJiq9RKUTs9pDlVO5Z1 # UEeBC8SHNj6siZ5EkCk3IQf7hIq77UITR4wHMQmNLqXY25pSexzqgAKiQt5bbU38 # VyUcXZglXKyvWDPLR36kKQeSSQFaToyVYmw2pr4oZXtEwAUrh8KqprlL+o/V1kFk # 726i03xtqpPn/HN49kzvfOatlq5qUkeLPWI5RN/q9jjE4RdNxPeSBeyy47yNoR6t # i9jPV+Z9XhNk7OpTmFKyEEBrf2cyGBubddpDgjDlzBohaICk24pIZgUpHs5WyIkF # 8/mz9nruUHNXYwasQ5zjHoEaNfoCAgmAMY8klNK6t7Ty5AhT5x0c/5c5WxJ4L0BC # z0WMZrK4r3uoFeXxRqQZnaWxx0ySCQkPyCuRNGqCx8J/bFhx9VUz5xgR1fZpkfNG # NdDCueZI3mtdULz2JFe+wwan5XPapEKArFW0RQdR4QYBHiZTrpE= # =gVkC # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 Jan 2026 05:06:23 PM AEDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260109' of https://github.com/alistair23/qemu: (34 commits) test/functional: Add test for boston-aia board riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 hw/riscv: Add support for MIPS Boston-aia board mode hw/riscv: Add support for RISCV CPS hw/misc: Add RISC-V CPC device implementation hw/misc: Add RISC-V CMGCR device implementation target/riscv: Add Xmipslsp instructions target/riscv: Add mips.pref instruction target/riscv: Add mips.ccmov instruction target/riscv: Add MIPS P8700 CSRs target/riscv: Add MIPS P8700 CPU target/riscv: Add cpu_set_exception_base Add RISCV ZALASR extension target/riscv: Add Zilsd and Zclsd extension support hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes hw/intc/riscv_aplic: Factor out source_active() and remove duplicate checks hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i] target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val target/riscv: Combine mhpmcounter and mhpmcounterh target/riscv: Combine minstretcfg and minstretcfgh ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>