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4a84032a26
All 64-bit PA-RISC machines split the memory into (up to 3) different memory ranges, which are mapped at specific addresses. This patch mimics the mapping as it's done on physical machines, which includes the 3.75 GB split for C3700, and 1 GB split for newer 64-bit PAT machines like the A400. SeaBIOS-hppa needs to know how the memory split is done, so add a new memsplit_addr variable which stores the specific split address and hand this over to SeaBIOS-hppa via fwcfg. Signed-off-by: Helge Deller <deller@gmx.de>
79 lines
2.7 KiB
C
79 lines
2.7 KiB
C
/* HPPA cores and system support chips. */
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/* Be aware: QEMU and seabios-hppa repositories share this file as-is. */
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#ifndef HW_HPPA_HPPA_HARDWARE_H
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#define HW_HPPA_HPPA_HARDWARE_H
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#define FIRMWARE_START 0xf0000000
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#define FIRMWARE_END 0xf0100000
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#define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */
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#define RAM_MAP_HIGH1 0x0100000000 /* memory above 4 GB */
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#define RAM_MAP_HIGH2 0x4040000000 /* memory between 1 G and 3.75 GB */
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#define MEM_PDC_ENTRY 0x4800 /* PDC entry address */
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#define DEVICE_HPA_LEN 0x00100000
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#define GSC_HPA 0xffc00000
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#define DINO_HPA 0xfff80000
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#define DINO_UART_HPA 0xfff83000
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#define DINO_UART_BASE 0xfff83800
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#define DINO_SCSI_HPA 0xfff8c000
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#define LASI_HPA_715 0xf0100000
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#define LASI_HPA 0xffd00000
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#define LASI_GFX_HPA 0xf8000000
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#define ARTIST_FB_ADDR 0xf9000000
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#define CPU_HPA 0xfffb0000
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#define MEMORY_HPA 0xfffff000
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#define IDE_HPA 0xf9000000 /* Boot disc controller */
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#define ASTRO_HPA 0xfed00000
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#define ELROY0_HPA 0xfed30000
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#define ELROY2_HPA 0xfed32000
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#define ELROY8_HPA 0xfed38000
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#define ELROYc_HPA 0xfed3c000
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#define ASTRO_MEMORY_HPA 0xfed10200
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#define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */
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#define HPA_DISABLED_DEVICE 1 /* add to HPA to disable */
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/* offsets to DINO HPA: */
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#define DINO_PCI_ADDR 0x064
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#define DINO_CONFIG_DATA 0x068
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#define DINO_IO_DATA 0x06c
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#define PORT_PCI_CMD hppa_port_pci_cmd
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#define PORT_PCI_DATA hppa_port_pci_data
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#define FW_CFG_IO_BASE 0xfffa0000
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#define PORT_SERIAL1 (LASI_UART_HPA + 0x800)
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#define PORT_SERIAL2 (DINO_UART_HPA + 0x800)
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#define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */
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#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
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#define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */
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#define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */
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#define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */
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#define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */
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/* ASTRO Memory and I/O regions */
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#define ASTRO_BASE_HPA 0xffffed00000
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#define ELROY0_BASE_HPA 0xffffed30000 /* ELROY0_HPA */
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#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
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#define LMMIO_DIRECT0_BASE 0x300
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#define LMMIO_DIRECT0_MASK 0x308
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#define LMMIO_DIRECT0_ROUTE 0x310
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/* space register hashing */
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#define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */
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#define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */
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#endif
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