mirror of
https://github.com/qemu/qemu.git
synced 2026-07-08 17:46:17 +00:00
buildsys: Remove MIPS TCG backend
We removed support for MIPS host. Remove the now unreachable TCG host code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20260511135312.38705-6-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
@@ -4148,15 +4148,6 @@ M: WANG Xuerui <git@xen0n.name>
|
|||||||
S: Maintained
|
S: Maintained
|
||||||
F: tcg/loongarch64/
|
F: tcg/loongarch64/
|
||||||
|
|
||||||
MIPS TCG target
|
|
||||||
M: Philippe Mathieu-Daudé <philmd@linaro.org>
|
|
||||||
R: Aurelien Jarno <aurelien@aurel32.net>
|
|
||||||
R: Huacai Chen <chenhuacai@kernel.org>
|
|
||||||
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
|
|
||||||
R: Aleksandar Rikalo <arikalo@gmail.com>
|
|
||||||
S: Odd Fixes
|
|
||||||
F: tcg/mips64/
|
|
||||||
|
|
||||||
PPC TCG target
|
PPC TCG target
|
||||||
M: Richard Henderson <richard.henderson@linaro.org>
|
M: Richard Henderson <richard.henderson@linaro.org>
|
||||||
S: Odd Fixes
|
S: Odd Fixes
|
||||||
|
|||||||
@@ -1,114 +0,0 @@
|
|||||||
/*
|
|
||||||
* safe-syscall.inc.S : host-specific assembly fragment
|
|
||||||
* to handle signals occurring at the same time as system calls.
|
|
||||||
* This is intended to be included by common-user/safe-syscall.S
|
|
||||||
*
|
|
||||||
* Written by Richard Henderson <richard.henderson@linaro.org>
|
|
||||||
* Copyright (C) 2021 Linaro, Inc.
|
|
||||||
*
|
|
||||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
|
||||||
* See the COPYING file in the top-level directory.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "sys/regdef.h"
|
|
||||||
#include "sys/asm.h"
|
|
||||||
|
|
||||||
.text
|
|
||||||
.set nomips16
|
|
||||||
.set reorder
|
|
||||||
|
|
||||||
.global safe_syscall_start
|
|
||||||
.global safe_syscall_end
|
|
||||||
.type safe_syscall_start, @function
|
|
||||||
.type safe_syscall_end, @function
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This is the entry point for making a system call. The calling
|
|
||||||
* convention here is that of a C varargs function with the
|
|
||||||
* first argument an 'int *' to the signal_pending flag, the
|
|
||||||
* second one the system call number (as a 'long'), and all further
|
|
||||||
* arguments being syscall arguments (also 'long').
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* 1 * 8 for s0 save; 1 * 8 for align. */
|
|
||||||
#define FRAME 16
|
|
||||||
#define OFS_S0 0
|
|
||||||
|
|
||||||
|
|
||||||
NESTED(safe_syscall_base, FRAME, ra)
|
|
||||||
.cfi_startproc
|
|
||||||
PTR_ADDIU sp, sp, -FRAME
|
|
||||||
.cfi_adjust_cfa_offset FRAME
|
|
||||||
REG_S s0, OFS_S0(sp)
|
|
||||||
.cfi_rel_offset s0, OFS_S0
|
|
||||||
/*
|
|
||||||
* The syscall calling convention is nearly the same as C:
|
|
||||||
* we enter with a0 == &signal_pending
|
|
||||||
* a1 == syscall number
|
|
||||||
* a2 ... a7 == syscall arguments
|
|
||||||
* and return the result in a0
|
|
||||||
* and the syscall instruction needs
|
|
||||||
* v0 == syscall number
|
|
||||||
* a0 ... a5 == syscall arguments
|
|
||||||
* and returns the result in v0
|
|
||||||
* Shuffle everything around appropriately.
|
|
||||||
*/
|
|
||||||
move s0, a0 /* signal_pending pointer */
|
|
||||||
move v0, a1 /* syscall number */
|
|
||||||
move a0, a2 /* syscall arguments */
|
|
||||||
move a1, a3
|
|
||||||
move a2, a4
|
|
||||||
move a3, a5
|
|
||||||
move a4, a6
|
|
||||||
move a5, a7
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This next sequence of code works in conjunction with the
|
|
||||||
* rewind_if_safe_syscall_function(). If a signal is taken
|
|
||||||
* and the interrupted PC is anywhere between 'safe_syscall_start'
|
|
||||||
* and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'.
|
|
||||||
* The code sequence must therefore be able to cope with this, and
|
|
||||||
* the syscall instruction must be the final one in the sequence.
|
|
||||||
*/
|
|
||||||
safe_syscall_start:
|
|
||||||
/* If signal_pending is non-zero, don't do the call */
|
|
||||||
lw t1, 0(s0)
|
|
||||||
bnez t1, 2f
|
|
||||||
syscall
|
|
||||||
safe_syscall_end:
|
|
||||||
|
|
||||||
/* code path for having successfully executed the syscall */
|
|
||||||
REG_L s0, OFS_S0(sp)
|
|
||||||
PTR_ADDIU sp, sp, FRAME
|
|
||||||
.cfi_remember_state
|
|
||||||
.cfi_adjust_cfa_offset -FRAME
|
|
||||||
.cfi_restore s0
|
|
||||||
bnez a3, 1f
|
|
||||||
jr ra
|
|
||||||
.cfi_restore_state
|
|
||||||
|
|
||||||
/* code path when we didn't execute the syscall */
|
|
||||||
2: REG_L s0, OFS_S0(sp)
|
|
||||||
PTR_ADDIU sp, sp, FRAME
|
|
||||||
.cfi_adjust_cfa_offset -FRAME
|
|
||||||
.cfi_restore s0
|
|
||||||
li v0, QEMU_ERESTARTSYS
|
|
||||||
|
|
||||||
/* code path setting errno */
|
|
||||||
/*
|
|
||||||
* We didn't setup GP on entry, optimistic of the syscall success.
|
|
||||||
* We must do so now to load the address of the helper, as required
|
|
||||||
* by the ABI, into t9.
|
|
||||||
*
|
|
||||||
* Note that SETUP_GPX and SETUP_GPX64 are themselves conditional,
|
|
||||||
* so we can simply let the one that's not empty succeed.
|
|
||||||
*/
|
|
||||||
1: USE_ALT_CP(t0)
|
|
||||||
SETUP_GPX(t1)
|
|
||||||
SETUP_GPX64(t0, t1)
|
|
||||||
move a0, v0
|
|
||||||
PTR_LA t9, safe_syscall_set_errno_tail
|
|
||||||
jr t9
|
|
||||||
|
|
||||||
.cfi_endproc
|
|
||||||
END(safe_syscall_base)
|
|
||||||
@@ -115,7 +115,7 @@ static inline int thunk_type_size(const argtype *type_ptr, int is_host)
|
|||||||
if (is_host) {
|
if (is_host) {
|
||||||
#if defined(HOST_X86_64)
|
#if defined(HOST_X86_64)
|
||||||
return 8;
|
return 8;
|
||||||
#elif defined(HOST_MIPS) || defined(HOST_SPARC64)
|
#elif defined(HOST_SPARC64)
|
||||||
return 4;
|
return 4;
|
||||||
#elif defined(HOST_PPC)
|
#elif defined(HOST_PPC)
|
||||||
return sizeof(void *);
|
return sizeof(void *);
|
||||||
|
|||||||
@@ -1,75 +0,0 @@
|
|||||||
/*
|
|
||||||
* host-signal.h: signal info dependent on the host architecture
|
|
||||||
*
|
|
||||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
|
||||||
* Copyright (c) 2021 Linaro Limited
|
|
||||||
*
|
|
||||||
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
|
|
||||||
* See the COPYING file in the top-level directory.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MIPS_HOST_SIGNAL_H
|
|
||||||
#define MIPS_HOST_SIGNAL_H
|
|
||||||
|
|
||||||
/* The third argument to a SA_SIGINFO handler is ucontext_t. */
|
|
||||||
typedef ucontext_t host_sigcontext;
|
|
||||||
|
|
||||||
static inline uintptr_t host_signal_pc(host_sigcontext *uc)
|
|
||||||
{
|
|
||||||
return uc->uc_mcontext.pc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
|
|
||||||
{
|
|
||||||
uc->uc_mcontext.pc = pc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void *host_signal_mask(host_sigcontext *uc)
|
|
||||||
{
|
|
||||||
return &uc->uc_sigmask;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(__misp16) || defined(__mips_micromips)
|
|
||||||
#error "Unsupported encoding"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
|
|
||||||
{
|
|
||||||
uint32_t insn = *(uint32_t *)host_signal_pc(uc);
|
|
||||||
|
|
||||||
/* Detect all store instructions at program counter. */
|
|
||||||
switch ((insn >> 26) & 077) {
|
|
||||||
case 050: /* SB */
|
|
||||||
case 051: /* SH */
|
|
||||||
case 052: /* SWL */
|
|
||||||
case 053: /* SW */
|
|
||||||
case 054: /* SDL */
|
|
||||||
case 055: /* SDR */
|
|
||||||
case 056: /* SWR */
|
|
||||||
case 070: /* SC */
|
|
||||||
case 071: /* SWC1 */
|
|
||||||
case 074: /* SCD */
|
|
||||||
case 075: /* SDC1 */
|
|
||||||
case 077: /* SD */
|
|
||||||
#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
|
|
||||||
case 072: /* SWC2 */
|
|
||||||
case 076: /* SDC2 */
|
|
||||||
#endif
|
|
||||||
return true;
|
|
||||||
case 023: /* COP1X */
|
|
||||||
/*
|
|
||||||
* Required in all versions of MIPS64 since
|
|
||||||
* MIPS64r1 and subsequent versions of MIPS32r2.
|
|
||||||
*/
|
|
||||||
switch (insn & 077) {
|
|
||||||
case 010: /* SWXC1 */
|
|
||||||
case 011: /* SDXC1 */
|
|
||||||
case 015: /* SUXC1 */
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@@ -1351,7 +1351,7 @@ static inline abi_ulong target_shmlba(CPUArchState *cpu_env)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(__mips__) || defined(__sparc__)
|
#if defined(__sparc__)
|
||||||
#define HOST_FORCE_SHMLBA 1
|
#define HOST_FORCE_SHMLBA 1
|
||||||
#else
|
#else
|
||||||
#define HOST_FORCE_SHMLBA 0
|
#define HOST_FORCE_SHMLBA 0
|
||||||
|
|||||||
@@ -1,30 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: MIT */
|
|
||||||
/*
|
|
||||||
* Define MIPS target-specific constraint sets.
|
|
||||||
* Copyright (c) 2021 Linaro
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
|
|
||||||
* Each operand should be a sequence of constraint letters as defined by
|
|
||||||
* tcg-target-con-str.h; the constraint combination is inclusive or.
|
|
||||||
*/
|
|
||||||
C_O0_I1(r)
|
|
||||||
C_O0_I2(r, rz)
|
|
||||||
C_O0_I2(rz, r)
|
|
||||||
C_O0_I3(rz, rz, r)
|
|
||||||
C_O0_I4(r, r, rz, rz)
|
|
||||||
C_O1_I1(r, r)
|
|
||||||
C_O1_I2(r, 0, rz)
|
|
||||||
C_O1_I2(r, r, r)
|
|
||||||
C_O1_I2(r, r, ri)
|
|
||||||
C_O1_I2(r, r, rI)
|
|
||||||
C_O1_I2(r, r, rIK)
|
|
||||||
C_O1_I2(r, r, rJ)
|
|
||||||
C_O1_I2(r, r, rz)
|
|
||||||
C_O1_I2(r, r, rzW)
|
|
||||||
C_O1_I4(r, r, rz, rz, 0)
|
|
||||||
C_O1_I4(r, r, rz, rz, rz)
|
|
||||||
C_O1_I4(r, r, r, rz, rz)
|
|
||||||
C_O2_I1(r, r, r)
|
|
||||||
C_O2_I2(r, r, r, r)
|
|
||||||
@@ -1,20 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: MIT */
|
|
||||||
/*
|
|
||||||
* Define MIPS target-specific operand constraints.
|
|
||||||
* Copyright (c) 2021 Linaro
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Define constraint letters for register sets:
|
|
||||||
* REGS(letter, register_mask)
|
|
||||||
*/
|
|
||||||
REGS('r', ALL_GENERAL_REGS)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Define constraint letters for constants:
|
|
||||||
* CONST(letter, TCG_CT_CONST_* bit set)
|
|
||||||
*/
|
|
||||||
CONST('I', TCG_CT_CONST_U16)
|
|
||||||
CONST('J', TCG_CT_CONST_S16)
|
|
||||||
CONST('K', TCG_CT_CONST_P2M1)
|
|
||||||
CONST('W', TCG_CT_CONST_WSZ)
|
|
||||||
@@ -1,69 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: MIT */
|
|
||||||
/*
|
|
||||||
* Define target-specific opcode support
|
|
||||||
* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
|
|
||||||
* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef TCG_TARGET_HAS_H
|
|
||||||
#define TCG_TARGET_HAS_H
|
|
||||||
|
|
||||||
/* MOVN/MOVZ instructions detection */
|
|
||||||
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
|
|
||||||
defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
|
|
||||||
defined(_MIPS_ARCH_MIPS4)
|
|
||||||
#define use_movnz_instructions 1
|
|
||||||
#else
|
|
||||||
extern bool use_movnz_instructions;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* MIPS32 instruction set detection */
|
|
||||||
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
|
|
||||||
#define use_mips32_instructions 1
|
|
||||||
#else
|
|
||||||
extern bool use_mips32_instructions;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* MIPS32R2 instruction set detection */
|
|
||||||
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
|
||||||
#define use_mips32r2_instructions 1
|
|
||||||
#else
|
|
||||||
extern bool use_mips32r2_instructions;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* MIPS32R6 instruction set detection */
|
|
||||||
#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
|
|
||||||
#define use_mips32r6_instructions 1
|
|
||||||
#else
|
|
||||||
#define use_mips32r6_instructions 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* optional instructions */
|
|
||||||
#define TCG_TARGET_HAS_extr_i64_i32 1
|
|
||||||
#define TCG_TARGET_HAS_ext32s_i64 1
|
|
||||||
#define TCG_TARGET_HAS_ext32u_i64 1
|
|
||||||
|
|
||||||
/* optional instructions detected at runtime */
|
|
||||||
#define TCG_TARGET_HAS_qemu_ldst_i128 0
|
|
||||||
#define TCG_TARGET_HAS_tst 0
|
|
||||||
|
|
||||||
#define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions
|
|
||||||
#define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions
|
|
||||||
|
|
||||||
static inline bool
|
|
||||||
tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
|
|
||||||
{
|
|
||||||
if (ofs == 0) {
|
|
||||||
switch (len) {
|
|
||||||
case 8:
|
|
||||||
case 16:
|
|
||||||
return use_mips32r2_instructions;
|
|
||||||
case 32:
|
|
||||||
return type == TCG_TYPE_I64;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@@ -1,13 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: MIT */
|
|
||||||
/*
|
|
||||||
* Define target-specific memory model
|
|
||||||
* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
|
|
||||||
* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef TCG_TARGET_MO_H
|
|
||||||
#define TCG_TARGET_MO_H
|
|
||||||
|
|
||||||
#define TCG_TARGET_DEFAULT_MO 0
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@@ -1 +0,0 @@
|
|||||||
/* No target specific opcodes. */
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,75 +0,0 @@
|
|||||||
/*
|
|
||||||
* Tiny Code Generator for QEMU
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
|
|
||||||
* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
|
|
||||||
* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
|
|
||||||
*
|
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
||||||
* of this software and associated documentation files (the "Software"), to deal
|
|
||||||
* in the Software without restriction, including without limitation the rights
|
|
||||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
||||||
* copies of the Software, and to permit persons to whom the Software is
|
|
||||||
* furnished to do so, subject to the following conditions:
|
|
||||||
*
|
|
||||||
* The above copyright notice and this permission notice shall be included in
|
|
||||||
* all copies or substantial portions of the Software.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
||||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
||||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
||||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
||||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
||||||
* THE SOFTWARE.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MIPS_TCG_TARGET_H
|
|
||||||
#define MIPS_TCG_TARGET_H
|
|
||||||
|
|
||||||
#define TCG_TARGET_INSN_UNIT_SIZE 4
|
|
||||||
#define TCG_TARGET_NB_REGS 32
|
|
||||||
|
|
||||||
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
|
|
||||||
|
|
||||||
typedef enum {
|
|
||||||
TCG_REG_ZERO = 0,
|
|
||||||
TCG_REG_AT,
|
|
||||||
TCG_REG_V0,
|
|
||||||
TCG_REG_V1,
|
|
||||||
TCG_REG_A0,
|
|
||||||
TCG_REG_A1,
|
|
||||||
TCG_REG_A2,
|
|
||||||
TCG_REG_A3,
|
|
||||||
TCG_REG_T0,
|
|
||||||
TCG_REG_T1,
|
|
||||||
TCG_REG_T2,
|
|
||||||
TCG_REG_T3,
|
|
||||||
TCG_REG_T4,
|
|
||||||
TCG_REG_T5,
|
|
||||||
TCG_REG_T6,
|
|
||||||
TCG_REG_T7,
|
|
||||||
TCG_REG_S0,
|
|
||||||
TCG_REG_S1,
|
|
||||||
TCG_REG_S2,
|
|
||||||
TCG_REG_S3,
|
|
||||||
TCG_REG_S4,
|
|
||||||
TCG_REG_S5,
|
|
||||||
TCG_REG_S6,
|
|
||||||
TCG_REG_S7,
|
|
||||||
TCG_REG_T8,
|
|
||||||
TCG_REG_T9,
|
|
||||||
TCG_REG_K0,
|
|
||||||
TCG_REG_K1,
|
|
||||||
TCG_REG_GP,
|
|
||||||
TCG_REG_SP,
|
|
||||||
TCG_REG_S8,
|
|
||||||
TCG_REG_RA,
|
|
||||||
|
|
||||||
TCG_REG_CALL_STACK = TCG_REG_SP,
|
|
||||||
TCG_AREG0 = TCG_REG_S8,
|
|
||||||
} TCGReg;
|
|
||||||
|
|
||||||
#define TCG_REG_ZERO TCG_REG_ZERO
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Reference in New Issue
Block a user