From 9067113cdf0e4e0b4c34308692dcec483dfd9ef4 Mon Sep 17 00:00:00 2001 From: Anton Johansson Date: Wed, 7 May 2025 12:46:51 +0200 Subject: [PATCH] target-info: Add target_riscv64() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds a helper function to tell if the binary is targeting riscv64 or not. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Reviewed-by: Chao Liu Acked-by: Alistair Francis Reviewed-by: Alistair Francis Message-Id: <20260520-hw-riscv-cpu-int-v3-7-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 23c997de54..6c5b714288 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -99,4 +99,11 @@ bool target_ppc64(void); */ bool target_s390x(void); +/** + * target_riscv64: + * + * Returns whether the target architecture is riscv64 + */ +bool target_riscv64(void); + #endif diff --git a/target-info.c b/target-info.c index 28c458fc7a..04c69c41f8 100644 --- a/target-info.c +++ b/target-info.c @@ -93,3 +93,8 @@ bool target_s390x(void) { return target_arch() == SYS_EMU_TARGET_S390X; } + +bool target_riscv64(void) +{ + return target_arch() == SYS_EMU_TARGET_RISCV64; +}