From a045f6a8e819dcc0e80d13fbd1cedf60c85cef79 Mon Sep 17 00:00:00 2001 From: Anton Johansson Date: Wed, 30 Apr 2025 13:34:40 +0200 Subject: [PATCH] hw/riscv: Register generic riscv[32|64] QOM interfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/hw/riscv/machines-qom.h diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h new file mode 100644 index 0000000000..69fcf61fd7 --- /dev/null +++ b/include/hw/riscv/machines-qom.h @@ -0,0 +1,20 @@ +/* + * QOM type definitions for riscv32 / riscv64 machines + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RISCV_MACHINES_QOM_H +#define HW_RISCV_MACHINES_QOM_H + +#include "hw/core/boards.h" + +#define TYPE_TARGET_RISCV32_MACHINE \ + "target-info-riscv32-machine" + +#define TYPE_TARGET_RISCV64_MACHINE \ + "target-info-riscv64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index b48714cc77..7958a5cc68 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -13,6 +13,7 @@ #include "qemu/target-info-init.h" #include "qemu/target-info-qom.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" static const TypeInfo target_info_types[] = { { @@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] = { .name = TYPE_TARGET_AARCH64_MACHINE, .parent = TYPE_INTERFACE, }, + { + .name = TYPE_TARGET_RISCV32_MACHINE, + .parent = TYPE_INTERFACE, + }, + { + .name = TYPE_TARGET_RISCV64_MACHINE, + .parent = TYPE_INTERFACE, + }, }; DEFINE_TYPES(target_info_types)