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ee693c9a1d
Call TargetInfo::target_aarch64() at runtime, allowing to remove the target-specific TARGET_AARCH64 definition and build cpu-max.c once as common object. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20260526203722.79463-18-philmd@linaro.org>
242 lines
8.3 KiB
C
242 lines
8.3 KiB
C
/*
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* QEMU ARM 'max' CPU
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*
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* Copyright (c) 2018 Linaro Ltd
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/target-info.h"
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#include "system/hw_accel.h"
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#include "system/kvm.h"
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#include "system/qtest.h"
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#include "system/tcg.h"
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#include "target/arm/internals.h"
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#include "target/arm/cpregs.h"
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void aarch64_aa32_a57_init(Object *obj, bool aa32_only)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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ARMISARegisters *isar = &cpu->isar;
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const bool aarch64_enabled = !aa32_only;
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
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if (aarch64_enabled) {
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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}
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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if (kvm_enabled()) {
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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}
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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SET_IDREG(isar, ID_PFR0, 0x00000131);
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SET_IDREG(isar, ID_PFR1, 0x00011011);
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SET_IDREG(isar, ID_DFR0, 0x03010066);
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SET_IDREG(isar, ID_AFR0, 0x00000000);
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SET_IDREG(isar, ID_MMFR0, 0x10101105);
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SET_IDREG(isar, ID_MMFR1, 0x40000000);
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SET_IDREG(isar, ID_MMFR2, 0x01260000);
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SET_IDREG(isar, ID_MMFR3, 0x02102211);
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SET_IDREG(isar, ID_ISAR0, 0x02101110);
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SET_IDREG(isar, ID_ISAR1, 0x13112111);
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SET_IDREG(isar, ID_ISAR2, 0x21232042);
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SET_IDREG(isar, ID_ISAR3, 0x01112131);
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SET_IDREG(isar, ID_ISAR4, 0x00011142);
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SET_IDREG(isar, ID_ISAR5, 0x00011121);
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SET_IDREG(isar, ID_ISAR6, 0);
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if (aarch64_enabled) {
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SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
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SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
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SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
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SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
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}
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cpu->isar.dbgdidr = 0x3516d000;
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cpu->isar.dbgdevid = 0x01110f13;
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cpu->isar.dbgdevid1 = 0x2;
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cpu->isar.reset_pmcr_el0 = 0x41013000;
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SET_IDREG(isar, CLIDR, 0x0a200023);
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/* 32KB L1 dcache */
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cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
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/* 48KB L1 icache */
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cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
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/* 2048KB L2 cache */
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cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
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if (aarch64_enabled) {
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set_dczid_bs(cpu, 4); /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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}
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define_cortex_a72_a57_a53_cp_reginfo(cpu);
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}
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/* Share AArch32 -cpu max features with AArch64. */
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void aa32_max_features(ARMCPU *cpu)
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{
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uint32_t t;
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ARMISARegisters *isar = &cpu->isar;
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/* Add additional features supported by QEMU */
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t = GET_IDREG(isar, ID_ISAR5);
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t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
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t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
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t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
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t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
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t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
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t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
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SET_IDREG(isar, ID_ISAR5, t);
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t = GET_IDREG(isar, ID_ISAR6);
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t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
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t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
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t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
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t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
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t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
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t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
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t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
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SET_IDREG(isar, ID_ISAR6, t);
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t = cpu->isar.mvfr1;
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t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
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t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
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cpu->isar.mvfr1 = t;
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t = cpu->isar.mvfr2;
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t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
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t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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cpu->isar.mvfr2 = t;
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FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
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t = GET_IDREG(isar, ID_MMFR4);
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t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
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t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
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t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
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t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
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SET_IDREG(isar, ID_MMFR4, t);
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FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
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t = GET_IDREG(isar, ID_PFR0);
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t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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SET_IDREG(isar, ID_PFR0, t);
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t = GET_IDREG(isar, ID_PFR2);
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t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
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t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
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SET_IDREG(isar, ID_PFR2, t);
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t = GET_IDREG(isar, ID_DFR0);
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t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
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t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
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t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
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SET_IDREG(isar, ID_DFR0, t);
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/* Debug ID registers. */
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/* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
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t = 0x00008000;
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t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
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t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
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t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
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t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
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t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
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t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
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cpu->isar.dbgdidr = t;
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t = 0;
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t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
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t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
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t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
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t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
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t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
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t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
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t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
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t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
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cpu->isar.dbgdevid = t;
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/* Bits[31:4] are RES0. */
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t = 0;
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t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
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cpu->isar.dbgdevid1 = t;
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FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
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}
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/*
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* -cpu max: a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
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* this only needs to handle 32 bits, and need not care about KVM.
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*/
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static void cpu_max_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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const bool aarch64_enabled = target_aarch64();
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if (hwaccel_enabled()) {
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assert(aarch64_enabled);
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/*
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* When hardware acceleration enabled, '-cpu max' is
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* identical to '-cpu host'
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*/
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aarch64_host_initfn(obj);
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return;
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}
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if (tcg_enabled() || qtest_enabled()) {
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aarch64_aa32_a57_init(obj, !aarch64_enabled);
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}
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if (!aarch64_enabled) {
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aa32_max_features(cpu);
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#ifdef CONFIG_USER_ONLY
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/*
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* Break with true ARMv8 and add back old-style VFP short-vector
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* support. Only do this for user-mode, where -cpu max is the default,
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* so that older v6 and v7 programs are more likely to work without
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* adjustment.
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*/
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cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
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#endif
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} else if (tcg_enabled()) {
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assert(aarch64_enabled);
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/*
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* '-cpu max' for TCG: we currently do this as
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* "A57 with extra things"
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*/
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aarch64_max_tcg_initfn(obj);
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}
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}
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static const ARMCPUInfo arm_max_cpu = {
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.name = "max",
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.initfn = cpu_max_initfn,
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};
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static void arm_max_cpu_register_types(void)
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{
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arm_cpu_register(&arm_max_cpu);
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}
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type_init(arm_max_cpu_register_types)
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