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RISC-V PR for 11.1 * Disable svpbmt if satp_mode is less then sv39 * Fix PMP address alignment * Mstatus write bug fixes * Add 'cbo' insns to disassembler * Do not hide Sstc CSRs from gdbstub * Reject Svinval instructions in U-mode * Save opcode before zicbo helpers * Fault with reserved PTE.PBMT val * Allow LOAD_ADDR_MIS promotion to AMO fault * Make riscv cpu.h target independent * Add PMA access fault * Disable svnapot if satp_mode is less then sv39 * Fix disassembler inst_length calculation * Add RISC-V big-endian target support * Add the implied rules for G and B extensions * Print privilege level and ELP in riscv_cpu_dump_state * Improve alignment in riscv_cpu_dump_state * Mask vxrm csrw write to the low 2 bits * Reorder Smrnmi CPU fields above CPU reset line * Supplement cpu topology arguments * Don't insert DDT cache in Bare mode * Fix 'iommu-map' FDT entry * Fix mstatus.FS dirty tracking for FP exception-raising instructions * Enable `mnret` disassembly * Add support for K230 board * FDT creation helpers # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmoxH8EACgkQr3yVEwxT # gBOA0A/9EoqSh73fuWzBwOANN7sXBDRJwOzCetvoTqyXzbUtQJGPbslldLDoYA0K # GfqdmFNqi6pp01pBm/eWUu2vxid1d1IID+4g7LQ1TIyexbc58Qm7Hb1r+F1RSLj4 # NcZc+RGvJ+3D/hXUfj1dnT+yxUDsVAuf1NPONR9E9CD4q8gkvtA79Lwj3o/2Ks18 # 02ZPi8+vc5XmSjtwGVFdcxu4je89vvhzl4P+zwZMKOOU04bpsCG5chSRfSiGUnuz # jae/5YDOk4v6T61Yt3kDFc9CkuenhiDSHMiQy/PD/ufvBOlA3EzyIago3SO0DP9d # ZW+aVHOJ7SgcUPFbj6kkLo/FhXraXmKVo4vDhASoKHydoL1s6ZAR7TCAwLXa39Rq # z15OGtRzdQX48AkeUjeN+Mz6lxHusm4MmsBhMAnPxzhiGRjOH024SR2C9iSeuB4h # mMmYi25z48NLK5oilEhPAy37xUYUuRa+HoO07puQdLLReiuMyIWAwubhwMsog3MR # IULX57BlxrxqVSt3z7sLGAwBEz353ARYNSiDYR+2XXt8Qjy6kY7ONrSfeJMhjbH7 # wrYQ0+30Af+b7Lpm8kpapeEsn1KWYIJU//ji5tbgAmd0sSLCiAqZX6GwzFKoGUKO # u9Gc+A7vISxD5bBw33Z0Pp/zL1QUBom/pdZUHhaAGtKIuwLSA8s= # =iXpr # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Jun 2026 06:04:49 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20260616' of https://github.com/alistair23/qemu: (83 commits) hw/riscv: add create_fdt_socket_cpu_sifive() hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal() hw/riscv/spike.c: use create_fdt_socket_cpus() hw/riscv: add create_fdt_socket_cpus() hw/riscv: add fdt_create_cpu_socket_subnode() helper hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs hw/riscv: add create_fdt_clint() helper hw/riscv/spike.c: add intc_phandles array hw/riscv/sifive_u.c: add intc_phandles array hw/riscv: add create_fdt_socket_memory() helper hw/riscv/numa: make numa_enabled() public hw/riscv: add fdt-common helper hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc docs/system/riscv: add documentation for k230 machine tests/qtest: add test for K230 watchdog hw/watchdog: add k230 watchdog initial support hw/riscv: add k230 board initial support target/riscv: add thead-c908 cpu support disas/riscv: enable `mnret` disassembly target/riscv: rvv: Set mstatus.FS dirty when vector FP raises exceptions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>