From 07e9ea8f1c3e2af07f16ac263e3ca7dbcfb8d7a6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 9 Jun 2026 12:20:57 -0700 Subject: [PATCH] target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20260609192110.752384-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 2 ++ linux-user/aarch64/elfload.c | 2 ++ target/arm/tcg/cpu64.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9ff4473154..e46f5fdcd1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -76,6 +76,7 @@ the following architecture extensions: - FEAT_FP (Floating Point extensions) - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FP8 (FP8 convert instructions) +- FEAT_FP8FMA (FP8 multiply-accumulate to half-precision and single-precision instructions) - FEAT_FPAC (Faulting on AUT* instructions) - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) - FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions) @@ -166,6 +167,7 @@ the following architecture extensions: - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) - FEAT_SME_LUTv2 (Lookup table instructions with 4-bit indices and 8-bit elements) +- FEAT_SSVE_FP8FMA (SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode) - FEAT_SVE (Scalable Vector Extension) - FEAT_SVE_AES (Scalable Vector AES instructions) - FEAT_SVE_B16B16 (Non-widening BFloat16 arithmetic for SVE2) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 06c14e82ea..a82d65a681 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -226,6 +226,8 @@ abi_ulong get_elf_hwcap2(CPUState *cs) GET_FEATURE_ID(aa64_f8cvt, ARM_HWCAP2_A64_F8CVT | ARM_HWCAP2_A64_F8E4M3 | ARM_HWCAP2_A64_F8E5M2); + GET_FEATURE_ID(aa64_f8fma, ARM_HWCAP2_A64_F8FMA); + GET_FEATURE_ID(aa64_ssve_f8fma, ARM_HWCAP2_A64_SME_SF8FMA); return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7f79ee645b..38c0f0eafd 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1383,6 +1383,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64DFR0, t); t = GET_IDREG(isar, ID_AA64SMFR0); + t = FIELD_DP64(t, ID_AA64SMFR0, SF8FMA, 1); /* FEAT_SSVE_FP8FMA */ t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ t = FIELD_DP64(t, ID_AA64SMFR0, BI32I32, 1); /* FEAT_SME2 */ t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ @@ -1401,6 +1402,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = GET_IDREG(isar, ID_AA64FPFR0); t = FIELD_DP64(t, ID_AA64FPFR0, F8E5M2, 1); /* FEAT_FP8 */ t = FIELD_DP64(t, ID_AA64FPFR0, F8E4M3, 1); /* FEAT_FP8 */ + t = FIELD_DP64(t, ID_AA64FPFR0, F8FMA, 1); /* FEAT_FP8FMA */ t = FIELD_DP64(t, ID_AA64FPFR0, F8CVT, 1); /* FEAT_FP8 */ SET_IDREG(isar, ID_AA64FPFR0, t);